SiHD3N50DA www.vishay.com Vishay Siliconix D Series Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) at TJ max. • Optimal design - Low area specific on-resistance - Low input capacitance (Ciss) - Reduced capacitive switching losses - High body diode ruggedness - Avalanche energy rated (UIS) • Optimal efficiency and operation - Low cost - Simple gate drive circuitry - Low figure-of-merit (FOM): Ron x Qg - Fast switching • Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 550 RDS(on) max. at 25 °C (Ω) VGS = 10 V Qg (max.) (nC) 3.2 12 Qgs (nC) 2 Qgd (nC) 3 Configuration Single D DPAK (TO-252) D G G S APPLICATIONS S • Consumer electronics - Displays (LCD or plasma TV) • Server and telecom power supplies - SMPS • Industrial - Welding, induction heating, motor drives • Battery chargers N-Channel MOSFET ORDERING INFORMATION Package DPAK (TO-252) Lead (Pb)-free and Halogen-free SiHD3N50DA-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage Gate-Source Voltage Pulsed Drain LIMIT VDS 500 VGS Gate-Source Voltage AC (f > 1 Hz) Continuous Drain Current (TJ = 150 °C) SYMBOL VGS at 10 V TC = 25 °C TC = 100 °C Currenta ID IDM Linear Derating Factor ± 30 UNIT V 30 3.0 1.9 A 5.5 0.56 W/°C mJ Single Pulse Avalanche Energyb EAS 9 Maximum Power Dissipation PD 69 W TJ, Tstg -55 to +150 °C Operating Junction and Storage Temperature Range Drain-Source Voltage Slope TJ = 125 °C Reverse Diode dV/dtd Soldering Recommendations (Peak Temperature)c for 10 s dV/dt 24 0.22 300 V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 Ω, IAS = 2.8 A. c. 1.6 mm from case. d. ISD ≤ ID, starting TJ = 25 °C. S14-1304-Rev. A, 23-Jun-14 Document Number: 91614 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHD3N50DA www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 62 Maximum Junction-to-Case (Drain) RthJC - 1.8 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) VDS VGS = 0 V, ID = 250 μA 500 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.59 - V/°C VGS(th) VDS = VGS, ID = 250 μA 3 - 4.5 V Gate-Source Leakage IGSS VGS = ± 30 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 500 V, VGS = 0 V - - 1 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 10 - 2.6 3.2 Ω S Drain-Source On-State Resistance Forward Transconductance RDS(on) VGS = 10 V ID = 1.5 A gfs VDS = 8 V, ID = 1.5 A - 1 - VGS = 0 V, VDS = 100 V, f = 1 MHz - 177 - - 26 - - 7 - - 21 - - 28 - μA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Effective Output Capacitance, Energy Relatedb Co(er) Effective Output Capacitance, Time Relatedc Co(tr) pF VDS = 0 V to 400 V, VGS = 0 V Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time - 6 12 - 2 - Qgd - 3 - td(on) - 12 24 tr - 9 18 - 11 22 - 13 26 - 2.6 - - - 3 - - 5.5 - - 1.2 td(off) Fall Time tf Gate Input Resistance Rg VGS = 10 V ID = 1.5 A, VDS = 400 V VDD = 400 V, ID = 1.5 A Rg = 9.1 Ω, VGS = 10 V f = 1 MHz, open drain nC ns Ω Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Diode Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the integral reverse P - N junction diode D A G TJ = 25 °C, IS = 1.5 A, VGS = 0 V TJ = 25 °C, IF = IS = 1.5 A, dI/dt = 100 A/μs, VR = 25 V S V - 285 570 ns - 0.68 1.36 μC - 5 - A Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS. b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS. S14-1304-Rev. A, 23-Jun-14 Document Number: 91614 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHD3N50DA www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.0 6 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 4 RDS(on), Drain-to-Source On-Resistance (Normalized) 3 2 1 5 10 15 20 25 VDS, Drain-to-Source Voltage (V) 30 Fig. 1 - Typical Output Characteristics 1.5 1.0 VGS = 10 V 0.5 -40 -20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) 1000 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V TJ = 150 °C Ciss C, Capacitance (pF) ID, Drain-to-Source Current (A) 2.0 Fig. 4 - Normalized On-Resistance vs. Temperature 4 3 ID = 1.5 A 0 -60 0 0 2.5 2 100 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds shorted Crss = Cgd Coss = Cds + Cgd Coss 10 Crss 1 1 0 0 5 10 15 20 25 VDS, Drain-to-Source Voltage (V) 0 30 Fig. 2 - Typical Output Characteristics 100 200 300 400 VDS, Drain-to-Source Voltage (V) 500 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 6 1000 3 2.5 TJ = 25 °C 4 2 Coss (pF) ID, Drain-to-Source Current (A) 5 TJ = 150 °C 3 Eoss 100 1.5 2 Eoss (μJ) ID, Drain-to-Source Current (A) 5 TJ = 25 °C 1 Coss 1 0.5 VDS = 31.6 V 0 10 0 5 10 15 20 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S14-1304-Rev. A, 23-Jun-14 25 0 0 100 200 300 400 500 VDS Fig. 6 - Coss and Eoss vs. VDS Document Number: 91614 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHD3N50DA www.vishay.com Vishay Siliconix 3 VDS = 400 V VDS = 250 V VDS = 100 V 20 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 24 16 12 8 1 4 0 0 0 2 4 6 8 Qg, Total Gate Charge (nC) 10 25 12 50 75 100 125 150 TC, Case Temperature (°C) Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 10 - Maximum Drain Current vs. Case Temperature 625 VDS, Drain-to-Source Breakdown Voltage (V) 10 ISD, Reverse Drain Current (A) 2 TJ = 150 °C 1 TJ = 25 °C 0.1 VGS = 0 V 0.01 0.2 0.4 0.6 0.8 1.0 1.2 VSD, Source-Drain Voltage (V) 1.4 1.6 Fig. 8 - Typical Source-Drain Diode Forward Voltage 10 600 575 550 525 500 ID = 250 μA 475 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 11 - Typical Drain-to-Source Voltage vs. Temperature IDM Limited ID, Drain Current (A) 100 μs 1 Limited by RDS(on)* 1 ms Operation in this Area Limited by RDS(on) 0.1 10 ms TC = 25 °C TJ = 150 °C Single Pulse BVDSS Limited 0.01 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S14-1304-Rev. A, 23-Jun-14 Document Number: 91614 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHD3N50DA www.vishay.com Vishay Siliconix 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 Pulse Time (s) 0.1 1 Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case RD VDS VDS tp VGS VDD D.U.T. RG + - VDD VDS 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % IAS Fig. 13 - Switching Time Test Circuit Fig. 16 - Unclamped Inductive Waveforms VDS QG 10 V 90 % QGS 10 % VGS QGD VG td(on) td(off) tf tr Charge Fig. 14 - Switching Time Waveforms Fig. 17 - Basic Gate Charge Waveform L Vary tp to obtain required IAS Current regulator Same type as D.U.T. VDS 50 kΩ D.U.T RG + - IAS 12 V 0.2 µF 0.3 µF V DD + D.U.T. - VDS 10 V tp 0.01 Ω VGS 3 mA Fig. 15 - Unclamped Inductive Test Circuit IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S14-1304-Rev. A, 23-Jun-14 Document Number: 91614 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHD3N50DA www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91614. S14-1304-Rev. A, 23-Jun-14 Document Number: 91614 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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