ISL2110, ISL2111 Data Sheet March 8, 2012 100V, 3A/4A Peak, High Frequency Half-Bridge Drivers Features • Drives N-Channel MOSFET Half-Bridge The ISL2110, ISL2111 are 100V, high frequency, half-bridge N-Channel power MOSFET driver ICs. They are based on the popular HIP2100, HIP2101 half-bridge drivers, but offer several performance improvements. Peak output pull-up/ pull-down current has been increased to 3A/4A, which significantly reduces switching power losses and eliminates the need for external totem-pole buffers in many applications. Also, the low end of the VDD operational supply range has been extended to 8VDC. The ISL2110 has additional input hysteresis for superior operation in noisy environments and the inputs of the ISL2111, like those of the ISL2110, can now safely swing to the VDD supply rail. ISL2110ABZ PART MARKING 2110 ABZ TEMP RANGE (°C) • SOIC, DFN and TDFN Packages Compliant with 100V Conductor Spacing Guidelines per IPC-2221 • Pb-Free (RoHS Compliant) • Bootstrap Supply Max Voltage to 114VDC • On-Chip 1W Bootstrap Diode • Fast Propagation Times for Multi-MHz Circuits • Drives 1nF Load with Typical Rise/Fall Times of 9ns/7.5ns • CMOS Compatible Input Thresholds (ISL2110) • Independent Inputs Provide Flexibility PACKAGE (Pb-Free) PKG. DWG. # -40 to +125 8 Ld SOIC M8.15 ISL2110AR4Z 211 0AR4Z -40 to +125 12 Ld 4x4 DFN L12.4x4A ISL2111ABZ M8.15 2111 ABZ • SOIC, DFN and TDFN Package Options • 3.3V/TTL Compatible Input Thresholds (ISL2111) Ordering Information PART NUMBER (Notes 1, 2) FN6295.6 -40 to +125 8 Ld SOIC ISL2111AR4Z 211 1AR4Z -40 to +125 12 Ld 4x4 DFN • Outputs Unaffected by Supply Glitches, HS Ringing Below Ground or HS Slewing at High dv/dt • Low Power Consumption • Wide Supply Voltage Range (8V to 14V) L12.4x4A ISL2111ARTZ 211 1ARTZ -40 to +125 10 Ld 4x4 TDFN L10.4x4 ISL2111BR4Z 211 1BR4A -40 to +125 8 Ld 4x4 DFN • No Start-Up Problems L8.4x4 • Supply Undervoltage Protection • 1.6W/1W Typical Output Pull-Up/Pull-Down Resistance Applications NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. • Telecom Half-Bridge DC/DC Converters 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • Telecom Full-Bridge DC/DC Converters • Two-Switch Forward Converters • Active-Clamp Forward Converters • Class-D Audio Amplifiers 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL2110, ISL2111. For more information on MSL please see techbrief TB363. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2006-2009, 2011, 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL2110, ISL2111 Pinouts ISL2110AR4Z, ISL2111AR4Z (12 LD 4x4 DFN) TOP VIEW ISL2111ARTZ (10 LD 4x4 TDFN) TOP VIEW VDD 1 10 LO VDD 1 12 LO HB 2 9 VSS NC 2 11 VSS HO 3 8 LI NC 3 10 NC HS 4 7 HI HB 4 9 NC 6 NC HO 5 8 LI HS 6 7 HI EPAD* NC 5 *EPAD = Exposed PAD ISL2111BR4Z (8 LD 4x4 DFN) TOP VIEW ISL2110ABZ, ISL2111ABZ (8 LD SOIC) TOP VIEW VDD 1 8 LO HB 2 7 VSS HO 3 6 LI HS 4 5 VDD 1 8 LO HB 2 7 VSS HO 3 6 LI HS 4 5 HI HI EPAD* *EPAD = EXPOSED PAD Application Block Diagram +12V +100V SECONDARY CIRCUIT VDD HB DRIVE HI PWM CONTROLLER LI CONTROL HI HS DRIVE LO ISL2110 ISL2111 VSS 2 HO LO REFERENCE AND ISOLATION FN6295.6 March 8, 2012 ISL2110, ISL2111 Functional Block Diagram HB VDD UNDER VOLTAGE HO LEVEL SHIFT DRIVER HS HI ISL2111 ISL2111 UNDER VOLTAGE LO DRIVER LI VSS EPAD (DFN Package Only) *EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For best thermal performance connect the EPAD to the PCB power ground plane. +48V +12V PWM SECONDARY CIRCUIT ISL2110 ISL2111 ISOLATION FIGURE 1. TWO-SWITCH FORWARD CONVERTER +48V SECONDARY CIRCUIT +12V PWM ISL2110 ISL2111 ISOLATION FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE-CLAMP 3 FN6295.6 March 8, 2012 ISL2110, ISL2111 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD, VHB - VHS (Notes 4, 5) . . . . . . . . -0.3V to 18V LI and HI Voltages (Note 5) . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Voltage on LO (Note 5) . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Voltage on HO (Note 5) . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V Voltage on HS (Continuous) (Note 5) . . . . . . . . . . . . . . -1V to 110V Voltage on HB (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V Average Current in VDD to HB Diode . . . . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) Maximum Recommended Operating Conditions Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V Voltage on HB. . . . .VHS +7V to VHS +14V and VDD - 1V to VDD +100V HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns θJA (°C/W) θJC (°C/W) 8 Ld SOIC (Notes 6, 10). . . . . . . . . . . . 95 46 10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . 42 5.5 12 Ld DFN (Notes 7, 8) . . . . . . . . . . . . 40 5.5 8 Ld DFN (Notes 7, 8) . . . . . . . . . . . . . 40 4.0 Max Power Dissipation at +25°C in Free Air 8 Ld SOIC (Notes 6, 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3W 10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W 12 Ld DFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W 8 Ld DFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65°C to +150°C Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. The ISL2110 and ISL2111 are capable of derated operation at supply voltages exceeding 14V. Figure 22 shows the high-side voltage derating curve for this mode of operation. 5. All voltages referenced to VSS unless otherwise specified. 6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details. 7. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. For θJC, the “case temp” location is taken at the package top center. Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, unless otherwise specified. TJ = +25°C PARAMETERS SYMBOL TEST CONDITIONS TJ = -40°C to +125°C MIN TYP MAX MIN (Note 9) MAX (Note 9) UNITS SUPPLY CURRENTS VDD Quiescent Current IDD ISL2110; LI = HI = 0V - 0.1 0.25 - 0.3 mA VDD Quiescent Current IDD ISL2111; LI = HI = 0V - 0.3 0.45 - 0.55 mA VDD Operating Current IDDO ISL2110; f = 500kHz - 3.4 5.0 - 5.5 mA VDD Operating Current IDDO ISL2111; f = 500kHz - 3.5 5.0 - 5.5 mA Total HB Quiescent Current IHB LI = HI = 0V - 0.1 0.15 - 0.2 mA Total HB Operating Current IHBO f = 500kHz - 3.4 5.0 - 5.5 mA HB to VSS Current, Quiescent IHBS LI = HI = 0V; VHB = VHS = 114V - 0.05 1.5 - 10 µA HB to VSS Current, Operating IHBSO f = 500kHz; VHB = VHS = 114V - 1.2 - - - mA INPUT PINS Low Level Input Voltage Threshold VIL ISL2110 3.7 4.4 - 3.5 - V Low Level Input Voltage Threshold VIL ISL2111 1.4 1.8 - 1.2 - V High Level Input Voltage Threshold VIH ISL2110 - 6.6 7.4 - 7.6 V High Level Input Voltage Threshold VIH ISL2111 - 1.8 2.2 - 2.4 V VIHYS ISL2110 - 2.2 - - - V - 210 - 100 500 kΩ Input Voltage Hysteresis Input Pull-Down Resistance RI 4 FN6295.6 March 8, 2012 ISL2110, ISL2111 Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, unless otherwise specified. (Continued) TJ = +25°C PARAMETERS SYMBOL TEST CONDITIONS TJ = -40°C to +125°C MIN TYP MAX MIN (Note 9) MAX (Note 9) UNITS UNDERVOLTAGE PROTECTION VDD Rising Threshold VDDR 6.1 6.6 7.1 5.8 7.4 V VDD Threshold Hysteresis VDDH - 0.6 - - - V HB Rising Threshold VHBR 5.5 6.1 6.8 5.0 7.1 V HB Threshold Hysteresis VHBH - 0.6 - - - V BOOT STRAP DIODE Low Current Forward Voltage VDL IVDD-HB = 100µA - 0.5 0.6 - 0.7 V High Current Forward Voltage VDH IVDD-HB = 100mA - 0.7 0.9 - 1 V Dynamic Resistance RD IVDD-HB = 100mA - 0.7 1 - 1.5 Ω LO GATE DRIVER Low Level Output Voltage VOLL ILO = 100mA - 0.1 0.18 - 0.25 V High Level Output Voltage VOHL ILO = -100mA, VOHL = VDD - VLO - 0.16 0.23 - 0.3 V Peak Pull-Up Current IOHL VLO = 0V - 3 - - - A Peak Pull-Down Current IOLL VLO = 12V - 4 - - - A Low Level Output Voltage VOLH IHO = 100mA - 0.1 0.18 - 0.25 V High Level Output Voltage VOHH IHO = -100mA, VOHH = VHB - VHO - 0.16 0.23 - 0.3 V Peak Pull-Up Current IOHH VHO = 0V - 3 - - - A Peak Pull-Down Current IOLH VHO = 12V - 4 - - - A HO GATE DRIVER Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, unless otherwise specified. TJ = -40°C to +125°C TJ = +25°C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN (Note 9) MAX (Note 9) UNITS Lower Turn-Off Propagation Delay (LI Falling to LO Falling) tLPHL - 32 50 - 60 ns Upper Turn-Off Propagation Delay (HI Falling to HO Falling) tHPHL - 32 50 - 60 ns Lower Turn-On Propagation Delay (LI Rising to LO Rising) tLPLH - 39 50 - 60 ns Upper Turn-On Propagation Delay (HI Rising to HO Rising) tHPLH - 38 50 - 60 ns Delay Matching: Upper Turn-Off to Lower Turn-On tMON 1 8 - - 16 ns Delay Matching: Lower Turn-Off to Upper Turn-On tMOFF 1 6 - - 16 ns Either Output Rise Time (10% to 90%) tRC CL = 1nF - 9 - - - ns Either Output Fall Time (90% to 10%) tFC CL = 1nF - 7.5 - - - ns Either Output Rise Time (3V to 9V) tR CL = 0.1µF - 0.3 0.4 - 0.5 µs Either Output Fall Time (9V to 3V) tF CL = 0.1µF - 0.19 0.3 - 0.4 µs Minimum Input Pulse Width that Changes the Output tPW - - - - 50 ns Bootstrap Diode Turn-On or Turn-Off Time tBS - 10 - - - ns 5 FN6295.6 March 8, 2012 ISL2110, ISL2111 Pin Descriptions SYMBOL DESCRIPTION VDD Positive supply to lower gate driver. Bypass this pin to VSS. HB High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. HO High-side output. Connect to gate of high-side power MOSFET. HS High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. HI High-side input. LI Low-side input. VSS Chip negative supply, which will generally be ground. LO Low-side output. Connect to gate of low-side power MOSFET. NC No Connect. EPAD Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins. Timing Diagrams LI HI HI, LI tHPLH , tLPLH tHPHL, tLPHL LO tMOFF tMON HO, LO HO FIGURE 3. PROPAGATION DELAYS FIGURE 4. DELAY MATCHING Typical Performance Curves 10.0 10.0 T = -40°C IDDO (mA) IDDO (mA) T = -40°C T = +25°C 1.0 T = +25°C 1.0 T = +125°C T = +150°C T = +125°C 0.1 T = +150°C 10k 100k FREQUENCY (Hz) FIGURE 5. ISL2110 IDD OPERATING CURRENT vs FREQUENCY 6 1.103k 0.1 10k 100k 1.103k FREQUENCY (Hz) FIGURE 6. ISL2111 IDD OPERATING CURRENT vs FREQUENCY FN6295.6 March 8, 2012 ISL2110, ISL2111 Typical Performance Curves 10.0 (Continued) 10.0 T = +150°C 1.0 T = +150°C IHBSO (mA) IHBO (mA) T = -40°C T = +25°C 0.1 T = +125°C 1.0 T = -40°C T = +25°C 0.1 T = +125°C 0.01 10k 0.01 1.103k 100k 10k FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 7. IHB OPERATING CURRENT vs FREQUENCY FIGURE 8. IHBS OPERATING CURRENT vs FREQUENCY 300 200 VOHL, VOHH (mV) VOLL, VOLH (mV) VDD = VHB = 14V 250 200 150 100 50 -50 VDD = VHB = 8V VDD = VHB = 14V 150 100 VDD = VHB = 8V VDD = VHB = 12V 0 50 100 VDD = VHB = 12V 50 -50 150 0 TEMPERATURE (°C) 100 150 FIGURE 10. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE 6.7 0.70 6.5 0.65 VDDR 6.3 6.1 VDDH, VHBH (V) VDDR, VHBR (V) 50 TEMPERATURE (°C) FIGURE 9. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE VHBR 5.9 5.7 0 50 100 150 TEMPERATURE (°C) FIGURE 11. UNDERVOLTAGE LOCKOUT THRESHOLD vs TEMPERATURE 7 VHBH 0.60 0.55 0.50 0.45 5.5 5.3 -50 1.103k 100k 0.40 -50 VDDH 0 50 100 150 TEMPERATURE (°C) FIGURE 12. UNDERVOLTAGE LOCKOUT HYSTERESIS vs TEMPERATURE FN6295.6 March 8, 2012 ISL2110, ISL2111 Typical Performance Curves (Continued) 55 50 tLPLH, tLPHL, tHPLH, tHPHL (ns) tLPLH, tLPHL, tHPLH, tHPHL (ns) 55 tLPLH 45 40 tHPLH 35 tLPHL 30 tHPHL 25 -50 0 50 100 50 tLPLH 45 40 tHPLH 30 tHPHL 25 -50 150 0 TEMPERATURE (°C) tMON tMON, tMOFF (ns) tMON, tMOFF (ns) 7.5 6.5 tMOFF 5.5 5.0 4.5 4.0 -50 0 50 100 150 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 -50 tMOFF 0 50 100 150 TEMPERATURE (°C) FIGURE 15. ISL2110 DELAY MATCHING vs TEMPERATURE FIGURE 16. ISL2111 DELAY MATCHING vs TEMPERATURE 4.5 3.5 4.0 3.0 3.5 2.5 IOHL, IOHH (A) IOHL, IOHH (A) 150 tMON TEMPERATURE (°C) 2.0 1.5 1.0 3.0 2.5 2.0 1.5 1.0 0.5 0 100 FIGURE 14. ISL2111 PROPAGATION DELAYS vs TEMPERATURE 8.0 6.0 50 TEMPERATURE (°C) FIGURE 13. ISL2110 PROPAGATION DELAYS vs TEMPERATURE 7.0 tLPHL 35 0.5 0 2 4 6 VLO, VHO (V) 8 10 12 FIGURE 17. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE 8 0 0 2 4 6 VLO, VHO (V) 8 10 12 FIGURE 18. PEAK PULL-DOWN CURRENT vs OUTPUT VOLTAGE FN6295.6 March 8, 2012 ISL2110, ISL2111 120 110 100 90 80 70 60 50 40 30 20 10 0 (Continued) IDD IDD, IHB (µA) IDD, IHB (µA) Typical Performance Curves IHB 0 5 10 VDD, VHB (V) 15 20 FIGURE 19. ISL2110 QUIESCENT CURRENT vs VOLTAGE 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 5 10 VDD, VHB (V) 15 20 120 VHS TO VSS VOLTAGE (V) FORWARD CURRENT (A) IHB FIGURE 20. ISL2111 QUIESCENT CURRENT vs VOLTAGE 1.00 0.10 0.01 1.10-3 1.10-4 1.10-5 1.10-6 0.3 IDD 0.4 0.5 0.6 0.7 0.8 FORWARD VOLTAGE (V) FIGURE 21. BOOTSTRAP DIODE I-V CHARACTERISTICS 100 80 60 40 20 0 12 13 14 15 16 VDD TO VSS VOLTAGE (V) FIGURE 22. VHS VOLTAGE vs VDD VOLTAGE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN6295.6 March 8, 2012 ISL2110, ISL2111 Package Outline Drawing L10.4x4 10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 1/08 3.2 REF 4.00 A PIN #1 INDEX AREA 8X 0.80 BSC 6 B 5 1 10X 0 . 40 6 PIN 1 INDEX AREA 4.00 2.60 0.15 (4X) 10 6 0.10 M C A B 0.05 M C 4 10 X 0.30 TOP VIEW 3.00 BOTTOM VIEW ( 3.00 ) SEE DETAIL "X" 0 .75 ( 10 X 0.60 ) 0.10 C BASE PLANE SIDE VIEW ( 3.80) C SEATING PLANE 0.08 C ( 2.60) 0 . 2 REF C ( 8X 0 . 8 ) 0 . 00 MIN. 0 . 05 MAX. ( 10X 0 . 30 ) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 10 FN6295.6 March 8, 2012 ISL2110, ISL2111 Package Outline Drawing L12.4x4A 12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 3/11 3.2 REF 4.00 A PIN #1 INDEX AREA 10X 0.50 BSC 6 B 6 1 12X 0 . 45 6 PIN 1 INDEX AREA 4.00 1.58 0.15 (4X) 12 7 TOP VIEW 0.10 M C A B 0.05 M C 4 12 X 0.25 2.80 BOTTOM VIEW ( 2.80 ) SEE DETAIL "X" 1.00 MAX ( 12 X 0.65 ) 0.10 C BASE PLANE C SIDE VIEW ( 3.80) SEATING PLANE 0.08 C ( 1.58) 0 . 2 REF C ( 10X 0 . 5 ) 0 . 00 MIN. 0 . 05 MAX. ( 12X 0 . 25) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Lead width applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 11 FN6295.6 March 8, 2012 ISL2110, ISL2111 Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/11 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. 12 FN6295.6 March 8, 2012 ISL2110, ISL2111 Package Outline Drawing L8.4x4 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 11/09 2.4 REF 4.00 A PIN #1 INDEX AREA 6X 0.80 BSC 6 B 4 1 8X 0 . 40 ± 0.10 6 PIN 1 INDEX AREA 4.00 2.50 ± 0.10 0.15 (4X) 8 5 TOP VIEW 0.10 M C A B 0.05 M C 4 8 X 0.30 3.45 ± 0.10 BOTTOM VIEW ( 3.45 ) SEE DETAIL "X" 0 .9 ± 0.10 ( 8 X 0.60 ) 0.10 C BASE PLANE C SIDE VIEW ( 3.80) SEATING PLANE 0.08 C ( 2.50) 0 . 2 REF C ( 6X 0 . 8 ) 0 . 00 MIN. 0 . 05 MAX. ( 8X 0 . 30 ) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 13 FN6295.6 March 8, 2012