IRLI540G, SiHLI540G Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Isolated Package • High Voltage Isolation = 2.5 kVRMS (t = 60 s; f = 60 Hz) • Sink to Lead Creepage Distance = 4.8 mm • Logic-Level Gate Drive • RDS (on) Specified at VGS = 4 V and 5 V • Fast Switching • Ease of Paralleling • Compliant to RoHS Directive 2002/95/EC 100 RDS(on) (Ω) VGS = 5 V 0.077 Qg (Max.) (nC) 64 Qgs (nC) 9.4 Qgd (nC) 27 Configuration Single D TO-220 FULLPAK DESCRIPTION Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The TO-220 FULLPAK eliminates the need for additional insulating hardware in commercial-industrial applications. The molding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. This isolation is equivalent to using a 100 micron mica barrier with standard TO-220 product. The FULLPAK is mounted to a heatsink using a single clip or by a single screw fixing. G S G D S N-Channel MOSFET ORDERING INFORMATION Package TO-220 FULLPAK IRLI540GPbF SiHLI540G-E3 IRLI540G SiHLI540G Lead (Pb)-free SnPb ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 100 Gate-Source Voltage VGS ± 10 Continuous Drain Current VGS at 5 V TC = 25 °C TC = 100 °C Pulsed Drain Currenta ID IDM Linear Derating Factor Single Pulse Avalanche Energyb Maximum Power Dissipation TC = 25 °C Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque for 10 s 6-32 or M3 screw UNIT V 17 12 A 68 0.32 W/°C EAS 400 mJ PD 48 W dV/dt 5.5 V/ns TJ, Tstg - 55 to + 175 300d °C 10 lbf · in 1.1 N·m Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 2.1 mH, Rg = 25 Ω, IAS = 17 A (see fig. 12). c. ISD ≤ 28 A, dI/dt ≤ 170 A/μs, VDD ≤ VDS, TJ ≤ 175 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 90399 S10-1029-Rev. B, 03-May-10 www.vishay.com 1 IRLI540G, SiHLI540G Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 65 Maximum Junction-to-Case (Drain) RthJC - 3.1 UNIT °C/W SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage VDS VGS = 0 V, ID = 250 μA 100 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.12 - V/°C VGS(th) VDS = VGS, ID = 250 μA 1.0 - 2.0 V Gate-Source Leakage IGSS VGS = ± 10 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 100 V, VGS = 0 V - - 25 VDS = 80 V, VGS = 0 V, TJ = 150 °C - - 250 Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs VGS = 5 V ID = 10 Ab - - 0.077 VGS = 4 V Ab - - 0.11 12 - - - 2200 - ID = 8.5 VDS = 25 V, ID = 10 Ab μA Ω S Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Drain to Sink Capacitance C Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance tr td(off) VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 f = 1.0 MHz VGS = 5 V ID = 28 A, VDS = 80 V, see fig. 6 and 13b VDD = 50 V, ID = 28 A, Rg = 4.5 Ω, RD= 1.7 Ω, see fig. 10b tf LD LS Between lead, 6 mm (0.25") from package and center of die contact D - 560 - - 140 - - 12 - - - 64 - - 9.4 - - 27 - 8.5 - - 170 - - 35 - - 80 - - 4.5 - - 7.5 - - - 17 - - 68 pF nC ns nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 17 A, VGS = 0 S Vb TJ = 25 °C, IF = 28 A, dI/dt = 100 A/μsb - - 2.5 V - 130 260 ns - 1.5 2.9 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %. www.vishay.com 2 Document Number: 90399 S10-1029-Rev. B, 03-May-10 IRLI540G, SiHLI540G Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 3 - Typical Transfer Characteristics Fig. 2 - Typical Output Characteristics, TC = 175 °C Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 90399 S10-1029-Rev. B, 03-May-10 www.vishay.com 3 IRLI540G, SiHLI540G Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area www.vishay.com 4 Document Number: 90399 S10-1029-Rev. B, 03-May-10 IRLI540G, SiHLI540G Vishay Siliconix RD VDS VGS D.U.T. RG + - VDD 5V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature tr td(off) tf Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 90399 S10-1029-Rev. B, 03-May-10 www.vishay.com 5 IRLI540G, SiHLI540G Vishay Siliconix L VDS VDS Vary tp to obtain required IAS tp VDD D.U.T RG + - I AS V DD VDS 5V 0.01 Ω tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 5V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 90399 S10-1029-Rev. B, 03-May-10 IRLI540G, SiHLI540G Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?90399. Document Number: 90399 S10-1029-Rev. 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