ISL6263A ® Data Sheet 1 • Real-time GPU Power Monitor Output • Applications Up to 25A • Input Voltage Range: +5.0V to +25.0V • Programmable PWM Frequency: 200kHz to 500kHz • Pre-biased Output Start-up Capability • 5-bit Voltage Identification Input (VID) - 1.28750 to 0.41200V - 25.75mV Steps - Sequential or Non-sequential VID Change On-the-fly • Configurable PWM Modes - Forced Continuous Conduction Mode - Automatic Entry and Exit of Diode Emulation Mode - Selectable Audible Frequency PWM Filter • Integrated MOSFET Drivers and Bootstrap Diode • Choice of Current Sensing Schemes - Lossless inductor DCR Current Sensing - Precision Resistive Current Sensing • Overvoltage, Undervoltage, and Overcurrent Protection • Pb-free (RoHS compliant) Pinout AF_EN VR_ON PMON VID4 VID3 VID2 ISL6263A (32 LD 5x5 QFN) TOP VIEW PGOOD 32 31 30 29 28 27 26 25 23 VID0 OCSET 3 22 PVCC VW 4 THERMAL PAD 21 LGATE COMP 5 (BOTTOM) 20 PGND FB 6 19 PHASE VDIFF 7 18 UGATE VSEN 8 17 BOOT 9 10 11 12 13 14 15 16 VDD 2 VSS SOFT VIN 24 VID1 VSUM 1 VO RBIAS DFB The Render core voltage can be dynamically programmed from 0.41200V to 1.28750V by the five VID input pins without requiring sequential stepping of the VID states. The ISL6263A requires only one capacitor for both the soft-start slew-rate and the dynamic VID slew-rate by internally connecting the SOFT pin to the appropriate current source. Processor socket Kelvin sensing is accomplished with an integrated unity-gain true differential amplifier. • Precision Single-phase Core Voltage Regulator - 0.5% System Accuracy 0°C to +100°C - Differential Remote GPU Die Voltage Sensing - Differential Droop Voltage Sensing DROOP Intersil’s R3 Technology™ combines the best features of both fixed-frequency PWM and hysteretic PWM, delivering excellent light-load efficiency and superior load transient response by commanding variable switching frequency during the transitory event. For maximum conversion efficiency, the ISL6263A automatically enters diode emulation mode (DEM) should the inductor current attempt to flow negative. DEM is highly configurable and easy to setup. A PWM filter can be enabled that prevents the switching frequency from entering the audible spectrum as a result of extremely light load while in DEM. Features FDE The ISL6263A IC is a Single-Phase Synchronous-Buck PWM voltage regulator featuring Intersil’s Robust Ripple Regulator (R3) Technology™. The ISL6263A is an implementation of the Intel® Mobile Voltage Positioning (IMVP) protocol for GPU Render Engine core power. Integrated power monitor, droop amplifier, MOSFET drivers, and bootstrap diode result in smaller implementation area and lower component cost. FN9284.3 RTN 5-Bit VID Single-Phase Voltage Regulator with Power Monitor for IMVP-6+ Santa Rosa GPU Core July 8, 2010 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007, 2009, 2010. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. ISL6263A Ordering Information PART NUMBER (Notes 2, 3 PART MARKING TEMP RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL6263ACRZ ISL6263 ACRZ -10 to +100 32 Ld 5x5 QFN L32.5x5 ISL6263ACRZ-T (Note 1) ISL6263 ACRZ -10 to +100 32 Ld 5x5 QFN Tape and Reel L32.5x5 ISL6263AIRZ ISL6263 AIRZ -40 to +100 32 Ld 5x5 QFN ISL6263AIRZ-T (Note 1) ISL6263 AIRZ -40 to +100 32 Ld 5x5 QFN Tape and Reel L32.5x5 L32.5x5 NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6263A. For more information on MSL please see techbrief TB363. 2 FN9284.3 July 8, 2010 Block Diagram VR_ON PGOOD BOOT VDD VREF 1.545V + - PWM CONTROL POR VREF VSS 1:1 x2 DIODE EMULATION PGOOD 3 SCP SHORTCIRCUIT OVERCURRENT OCSET UNDERVOLTAGE + DFB - OVERVOLTAGE + FAULTLATCH + VO - PVCC LGATE DRIVER PGND + FDE Σ VSEN + RTN - + AF_EN VW + VDIFF VID0 VID1 VID2 VID3 ΔV W 20% ΔV W 30% X17.5 gmVin VW PWM R3 MODULATOR VID DAC ISS IDVID + VID4 + E/A - SOFT FB COMP PMON VIN FN9284.3 July 8, 2010 FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF THE ISL6263A gmVsoft VCOMP ISL6263A DROOP SHOOT-THROUGH PROTECTION SEVERE OVERVOLTAGE SOFT CROWBAR CONTROL OCP VSUM PHASE AUDIBLE FREQUENCY FILTER + RBIAS UGATE DRIVER ISL6263A Simplified Application Circuit for DCR Current Sensing RVDD V5V CVDD CPVCC VDD PVCC RRBIAS RBIAS VIN VIN CSOFT QHS SOFT CIN UGATE BOOT RPMON PGOOD LOUT CBOOT PMON CPMON VCCGFX PHASE VR_ON LGATE AF_EN PGND FDE VCC_SNS VSEN VSS_SNS RTN ISL6263A RS RNTC VSUM VW RFSET COUT QLS VID<0:4> RNTCP CN CFSET RNTCS VO CCOMP1 ROCSET RCOMP RDRP1 OCSET COMP CCOMP2 DFB FB VDIFF RDIFF2 RDRP2 CDIFF CDRP DROOP VSS RGND RDIFF1 0Ω FIGURE 2. ISL6263A GPU RENDER-CORE VOLTAGE REGULATOR SOLUTION WITH DCR CURRENT SENSING 4 FN9284.3 July 8, 2010 ISL6263A Simplified Application Circuit for Resistive Current Sensing RVDD V5V CPVCC CVDD VDD PVCC RRBIAS RBIAS VIN VIN CSOFT QHS SOFT CIN UGATE BOOT RPMON PGOOD LOUT CBOOT PMON CPMON RSNS VCCGFX PHASE VID<0:4> VR_ON LGATE AF_EN PGND FDE VCC_SNS VSEN VSS_SNS RTN ISL6263A RS VSUM VW RFSET COUT QLS CN CFSET VO CCOMP1 ROCSET COMP RCOMP RDRP1 OCSET CCOMP2 DFB FB VDIFF RDIFF2 RDRP2 CDIFF CDRP DROOP VSS RGND RDIFF1 0Ω FIGURE 3. ISL6263A GPU RENDER-CORE VOLTAGE REGULATOR SOLUTION WITH RESISTIVE CURRENT SENSING 5 FN9284.3 July 8, 2010 ISL6263A Absolute Voltage Ratings Thermal Information VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V VSS to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V PHASE to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to +28V (<100ns Pulse Width, 10µJ) -5.0V BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V BOOT to VSS or PGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V UGATE. . . . . . . . . . . . . . . . . . . (DC) -0.3V to PHASE, BOOT +0.3V (<200ns Pulse Width, 20µJ) -4.0V LGATE . . . . . . . . . . . . . . . . . . . . (DC) -0.3V to PGND, PVCC +0.3V (<100ns Pulse Width, 4µJ) -2.0V ALL Other Pins. . . . . . . . . . . . . . . . . . . . . -0.3V to VSS, VDD +0.3V Thermal Resistance (Typical, Notes 4, 5) θJA (°C/W) θJC (°C/W) 32 Ld QFN Package. . . . . . . . . . . . . . . 35 6 Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C Operating Temp. Range (ISL6263ACRZ) . . . . . . . .-10°C to +100°C Operating Temp. Range (ISL6263AIRZ) . . . . . . . . .-40°C to +100°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temp. Range ISL6263ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +100°C ISL6263AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +100°C VIN to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +25V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% FDE to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +3.3V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications These specifications apply for TA = -40°C to +100°C, unless otherwise stated. All typical specifications TA = +25°C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range, -40°C to +100°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS VIN VIN Input Resistance R VIN VIN Shutdown Current IVIN_SHDN VR_ON = 3.3V 1.0 VR_ON = 0V, VIN = 25V MΩ 1.0 µA 3.0 mA 1.0 µA 4.50 V VDD and PVCC VDD Input Bias Current IVDD VDD Shutdown Current IVDD_SHDN VR_ON = 3.3V 2.4 VR_ON = 0V, VDD = 5.0V VDD POR THRESHOLD Rising VDD POR Threshold Voltage V Falling VDD POR Threshold Voltage V 4.35 VDD_THR 3.85 4.10 V VID<4:0> = 00000 1.28750 V VID<4:0> = 11111 0.41200 V VID<4:0> = 00000 to 11110 (1.28750V to 0.51500V) 25.75 mV/step VID<4:0> = 11110 to 11111 (0.51500V to 0.41200V) 103 mV VDD_THF REGULATION V Output Voltage Range GFX_MAX V VID Voltage Step System Accuracy 6 GFX_MIN ISL6263ACRZ VID = 1.28750V to 0.74675V TA = 0°C to +100°C -0.5 0.5 % VID = 0.72100V to 0.51500V TA = 0°C to +100°C -1.0 1.0 % VID = 0.41200 TA = 0°C to +100°C -3.0 3.0 % FN9284.3 July 8, 2010 ISL6263A Electrical Specifications These specifications apply for TA = -40°C to +100°C, unless otherwise stated. All typical specifications TA = +25°C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range, -40°C to +100°C. (Continued) PARAMETER SYMBOL System Accuracy TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS ISL6263AIRZ VID = 1.28750V to 0.74675V TA = -40°C to +100°C -0.8 0.8 % VID = 0.72100V to 0.51500V TA = -40°C to +100°C -2.0 2.0 % VID = 0.41200 TA = -40°C to +100°C -4.5 4.5 % RFSET = 7kΩ, VCOMP = 2V (ISL6263ACRZ) 318 333 348 kHz RFSET = 7kΩ, VCOMP = 2V (ISL6263AIRZ) 318 333 352 kHz 500 kHz PWM f Nominal Frequency SW Frequency Range 200 f Audio Filter Frequency 28 AF kHz AMPLIFIERS Error Amplifier DC Gain (Note 7) AV0 90 dB Error Amplifier Gain-Bandwidth Product (Note 7) GBW CL = 20pF 18 MHz Error Amp Slew Rate (Note 7) SR CL = 20pF 5 V/µs IFB VFB = 1.28750V 10 150 nA 0.3 mV 1.495 1.515 1.535 V -47 -42 -37 µA |SOFT - REF|>100mV ±180 ±205 ±230 µA V V DROOP - O = 80mV, V to V = 1.2V 1.638 1.680 1.722 V V V DROOP - O = 20mV, V to V = 1.0V 0.308 0.350 0.392 V 2.8 3.0 FB Input Bias Current V Droop Amplifier Offset -0.3 DROOP_OFS V RBIAS Voltage RBIAS R RBIAS =150kΩ SOFT-START CURRENT Soft-Start Current ISS Soft Dynamic VID Current IDVID POWER MONITOR V Power Monitor Output Voltage Range PMON SEN SEN V Power Monitor Maximum Output Voltage SS SS PMONMAX V VPMON/250Ω VPMON/180Ω VPMON/130Ω Power Monitor Maximum Current Sinking Capability Power Monitor Sourcing Current ISC_PMON V V DROOP - O = 50mV, V to V = 1.0V 2.0 mA V V DROOP - O = 50mV, V to V = 1.0V 2.0 mA SEN Power Monitor Source Current ISK_PMON SEN SS SS IPMON ≤ ISK_PMON, IPMON ≤ ISC_PMON Power Monitor Impedance (Note 7) A Ω 7 GATE DRIVER UGATE Source Resistance (Note 7) RUGSRC 500mA Source Current 1.0 UGATE Source Current (Note 7) IUGSRC VUGATE_PHASE = 2.5V 2.0 UGATE Sink Resistance (Note 7) RUGSNK 500mA Sink Current 1.0 UGATE Sink Current (Note 7) IUGSNK VUGATE_PHASE = 2.5V 2.0 7 1.5 Ω A 1.5 Ω A FN9284.3 July 8, 2010 ISL6263A Electrical Specifications These specifications apply for TA = -40°C to +100°C, unless otherwise stated. All typical specifications TA = +25°C, VDD = 5V, PVCC = 5V. Boldface limits apply over the operating temperature range, -40°C to +100°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS 1.5 Ω LGATE Source Resistance (Note 7) RLGSRC 500mA Source Current 1.0 LGATE Source Current (Note 7) ILGSRC VLGATE_PGND = 2.5V 2.0 LGATE Sink Resistance (Note 7) RLGSNK 500mA Sink Current 0.5 LGATE Sink Current (Note 7) ILGSNK VLGATE_PGND = 2.5V 4.0 A 1.1 kΩ UGATE Pull-Down Resistor RPD A 0.9 Ω UGATE Turn-On Propagation Delay tPDRU PVCC = 5V, UGATE open 30 ns LGATE Turn-On Propagation Delay tPDRL PVCC = 5V, LGATE open 15 ns BOOTSTRAP DIODE Forward Voltage VF PVCC = 5V, IF = 10mA Reverse Leakage IR VR = 16V 0.56 0.69 0.795 V 5.0 µA 0.40 V 1.0 µA POWER GOOD and PROTECTION MONITOR PGOOD Low Voltage VPGOOD IPGOOD = 4mA PGOOD Leakage Current IPGOOD VPGOOD = 3.3V Overvoltage Threshold (VO-VSOFT) VOVP VO rising above VSOFT >1ms Severe Overvoltage Threshold VOVPS VO rising above 1.55V reference >0.5µs OCSET Reference Current IOCSET RRBIAS = 150kΩ OCSET Voltage Threshold Offset Undervoltage Threshold (VSOFT-VO) VOCSET_OFS VDROOP rising above VOCSET >120µs VUVF VO falling below VSOFT for >1ms 0.11 -1.0 155 195 235 mV 1.525 1.550 1.575 V 9.9 10.1 10.3 µA 3 mV -240 mV 1 V -3 -360 -300 CONTROL INPUTS VR_ON Input Low VVR_ONL VR_ON Input High VVR_ONH 2.3 AF_EN Input Low VAF_ENL AF_EN Input High VAF_ENH VR_ON Leakage IVR_ONL VVR_ON = 0V IVR_ONH VVR_ON = 3.3V IAF_ENL VAF_EN = 0V IAF_ENH VAF_EN = 3.3V AF_EN Leakage VID<4:0> Input Low VVIDL VID<4:0> Input High VVIDH FDE Input Low VFDEL FDE Input High VFDEH VID<4:0> Leakage FDE Leakage V 1 2.3 -1.0 V 0 0 -1.0 µA 1.0 0 0.45 1.0 µA 0.4 V V 0.3 0.7 VVID = 0V IVIDH VVID = 1.0V IFDEL VFDE = 0V IFDEH VFDE = 1.0V -1.0 V V 0 0.45 -1.0 µA µA 0.7 IVIDL V µA 1.0 0 0.45 µA µA 1.0 µA NOTES: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Limits established by characterization and are not production tested. 8 FN9284.3 July 8, 2010 ISL6263A Functional Pin Descriptions RBIAS (Pin 1) - Sets the internal 10µA current reference. Connect a 150kΩ ±1% resistor from RBIAS to VSS. SOFT (Pin 2) - Sets the output voltage slew-rate. Connect an X5R or X7R ceramic capacitor from SOFT to VSS. The SOFT pin is the non-inverting input of the error amplifier. OCSET (Pin 3) - Sets the overcurrent threshold. Connect a resistor from OCSET to VO. VW (Pin 4) - Sets the static PWM switching frequency in continuous conduction mode. Connect a resistor from VW to COMP. COMP (Pin 5) - Connects to the output of the control loop error amplifier. FB (Pin 6) - Connects to the inverting input of the control loop error amplifier. VDIFF (Pin 7) - Connects to the output of the VDIFF differential-summing amplifier. VSEN (Pin 8) - This is the VCC_SNS input of the processor socket Kelvin connection. Connects internally to one of two non-inverting inputs of the VDIFF differential-summing amplifier. RTN (Pin 9) - This is the VSS_SNS input of the processor socket Kelvin connection. Connects internally to one of two inverting inputs of the VDIFF differential-summing amplifier. DROOP (Pin 10) - Connects to the output of the droop differential amplifier and to one of two non-inverting inputs of the VDIFF differential-summing amplifier. DFB (Pin 11) - This is the feedback of the droop amplifier. Connects internally to the inverting input of the droop differential amplifier. VO (Pin 12) - Connects to one of two inverting inputs of the VDIFF differential-summing amplifier. VSUM (Pin 13) - Connects to the non-inverting input of the droop differential amplifier. VIN (Pin 14) - Connects to the R3 PWM modulator providing input voltage feed-forward. For optimum input voltage transient response, connect near the drain of the high-side MOSFETs. VSS (Pin 15) - Analog ground. VDD (Pin 16) - Input power supply for the IC. Connect to +5VDC and decouple with at least a 1µF MLCC capacitor from the VDD pin to the VSS pin. BOOT (Pin 17) - Input power supply for the high-side MOSFET gate driver. Connect an MLCC bootstrap capacitor from the BOOT pin to the PHASE pin. PHASE (Pin 19) - Current return path for the UGATE high-side MOSFET gate driver. Detects the polarity of the PHASE node voltage for diode emulation. Connect the PHASE pin to the drains of the low-side MOSFETs. PGND (Pin 20) - Current return path for the LGATE low-side MOSFET gate driver. The PGND pin only conducts current when LGATE pulls down. Connect the PGND pin to the sources of the low-side MOSFETs. LGATE (Pin 21) - Low-side MOSFET gate driver output. Connect to the gate of the low-side MOSFET. PVCC (Pin 22) - Input power supply for the low-side MOSFET gate driver, and the high-side MOSFET gate driver, via the internal bootstrap diode connected between the PVCC and BOOT pins. Connect to +5VDC and decouple with at least 1µF of an MLCC capacitor from the PVCC pin to the PGND pin. VID0:VID4 (Pin 23:Pin 27) - Voltage identification inputs. VID0 input is the least significant bit (LSB) and VID4 input is the most significant bit (MSB). PMON (Pin 28) - A voltage signal proportional to the output power of the converter. VR_ON (Pin 29) - A high logic signal on this pin enables the converter and a low logic signal disables the converter. AF_EN (Pin 30) - Used in conjunction with VID0:VID4 and FDE pins to program the diode-emulation and audio filter behavior. Refer to Table 1. PGOOD (Pin 31) - The PGOOD pin is an open-drain output that indicates when the converter is able to supply regulated voltage. Connect the PGOOD pin to a maximum of 5V through a pull-up resistor. FDE (Pin 32) - Used in conjunction with VID0:VID4 and AF_EN pins to program the diode-emulation and audio filter behavior. Refer to Table 1. BOTTOM - Connects to substrate. Electrically isolated but should be connected to VSS. Requires best practical thermal coupling to PCB. TABLE 1. DIODE-EMULATION MODE AND AUDIO-FILTER RENDER MODE PERFORMANCE SUSPEND FDE AF_EN DEM STATUS VOLTAGE WINDOW AUDIO FILTER 0 x DISABLED NOM x 1 x ENABLED 130% NOM x x 0 ENABLED 150% NOM x 1 1 ENABLED 130% NOM x 0 1 ENABLED 130% NOM ENABLED UGATE (Pin 18) - High-side MOSFET gate driver output. Connect to the gate of the high-side MOSFET. 9 FN9284.3 July 8, 2010 ISL6263A RENDER SUSPEND STATES RENDER PERFORMANCE STATES TABLE 2. VID TABLE FOR INTEL IMVP-6+ VCCGFX CORE Theory of Operation The R3 Modulator VID4 VID3 VID2 VID1 VID0 VCCGFX (V) x x x x x 0 0 0 0 0 0 1.28750 0 0 0 0 1 1.26175 0 0 0 1 0 1.23600 0 0 0 1 1 1.21025 0 0 1 0 0 1.18450 0 0 1 0 1 1.15875 0 0 1 1 0 1.13300 0 0 1 1 1 1.10725 0 1 0 0 0 1.08150 0 1 0 0 1 1.05575 0 1 0 1 0 1.03000 0 1 0 1 1 1.00425 0 1 1 0 0 0.97850 0 1 1 0 1 0.95275 0 1 1 1 0 0.92700 0 1 1 1 1 0.90125 1 0 0 0 0 0.87550 1 0 0 0 1 0.84975 1 0 0 1 0 0.82400 1 0 0 1 1 0.79825 1 0 1 0 0 0.77250 The PWM frequency is proportional to the difference in amplitude between V W and VCOMP. Operating on these large-amplitude, low noise synthesized signals allows the ISL6263A to achieve lower output ripple and lower phase jitter than either conventional hysteretic or fixed frequency PWM controllers. Unlike conventional hysteretic converters, the ISL6263A has an error amplifier that allows the controller to maintain tight voltage regulation accuracy throughout the VID range from 0.41200V to 1.28750V. 1 0 1 0 1 0.74675 Power-On Reset 1 0 1 1 0 0.72100 1 0 1 1 1 0.69525 1 1 0 0 0 0.66950 1 1 0 0 1 0.64375 The ISL6263A is disabled until the voltage at the VDD pin has increased above the rising VDD power-on reset (POR) VDD_THR threshold voltage. The controller will become disabled when the voltage at the VDD pin decreases below the falling POR VDD_THF threshold voltage. 1 1 0 1 0 0.61800 Start-Up Timing 1 1 0 1 1 0.59225 1 1 1 0 0 0.56650 1 1 1 0 1 0.54075 1 1 1 1 0 0.51500 1 1 1 1 1 0.41200 Figure 4 shows the ISL6263A start-up timing. Once VDD has ramped above VDD_THR, the controller can be enabled by pulling the VR_ON pin voltage above the input-high threshold VVR_ONH. Approximately 100µs later, the soft-start capacitor CSOFT begins slewing to the designated VID set-point as it is charged by the soft-start current source ISS. The VCCGFX output voltage of the converter follows the VSOFT voltage ramp to within 10% of the VID set-point then counts 13 switching cycles, then changes the open-drain output of the PGOOD pin to high impedance. During soft-start, the regulator always operates in continuous conduction mode (CCM). 10 The heart of the ISL6263A is Intersil’s Robust-RippleRegulator (R3) Technology™. The R3 modulator is a hybrid of fixed frequency PWM control, and variable frequency hysteretic control that will simultaneously affect the PWM switching frequency and PWM duty cycle in response to input voltage and output load transients. The term “Ripple” in the name “Robust-Ripple-Regulator” refers to the synthesized voltage-ripple signal VR that appears across the internal ripple-capacitor CR. The V R signal is a representation of the output inductor ripple current. Transconductance amplifiers measuring the input voltage of the converter and the output set-point voltage VSOFT, together produce the voltage-ripple signal VR. A voltage window signal V W is created across the VW and COMP pins by sourcing a current proportional to gmVsoft through a parallel network consisting of resistor RFSET and capacitor CFSET. The synthesized voltage-ripple signal VR along with similar companion signals are converted into PWM pulses. FN9284.3 July 8, 2010 ISL6263A VR_ON 90% ~100¬µ VSOFT/VCCGFX PGOOD 13 SWITCHING CYCLES FIGURE 4. ISL6263A START-UP TIMING Static Regulation The VCCGFX output voltage will be regulated to the value set by the VID inputs per Table 2. A true differential amplifier connected to the VSEN and RTN pins implements processor socket Kelvin sensing for precise core voltage regulation at the GPU voltage sense points. As the load current increases from zero, the VCCGFX output voltage will droop from the VID set-point by an amount proportional to the IMVP-6+ load line. The ISL6263A can accommodate DCR current sensing or discrete resistor current sensing. The DCR current sensing uses the intrinsic series resistance of the output inductor as shown in the application circuit of Figure 2. The discrete resistor current sensing uses a shunt connected in series with the output inductor as shown in the application circuit of Figure 3. In both cases the signal is fed to the non-inverting input of the DROOP amplifier at the VSUM pin, where it is measured differentially with respect to the output voltage of the converter at the VO pin and amplifier. The voltage at the DROOP pin minus the output voltage measured at the VO pin, is proportional to the total inductor current. This information is used exclusively to achieve the IMVP-6+ load line as well as the overcurrent protection. It is important to note that this current measurement should not be confused with the synthetic current ripple information created within the R3 modulator. When using inductor DCR current sensing, an NTC element is used to compensate the positive temperature coefficient of the copper winding thus maintaining the load-line accuracy. Processor Socket Kelvin Voltage Sensing The remote voltage sense input pins VSEN and RTN of the ISL6263A are to be terminated at the die of the GPU through connections that mate at the processor socket. (The signal names are VCC_SENSE and VSS_SENSE respectively). Kelvin sensing allows the voltage regulator to tightly control the processor voltage at the die, compensating for various resistive voltage drops in the power delivery path. 11 Since the voltage feedback is sensed at the processor die, removing the GPU will open the voltage feedback path of the regulator, causing the output voltage to rise towards VIN. The ISL6263A will shut down when the voltage between the VO and VSS pins exceeds the severe overvoltage protection threshold VOVPS of 1.55V. To prevent this issue from occurring, it is recommended to install resistors ROPN1 and ROPN2 as shown in Figure 5. These resistors provide voltage feedback from the regulator local output in the absence of the GPU. These resistors should be in the range of 20Ω to 100Ω. High Efficiency Diode Emulation Mode The ISL6263A operates in continuous-conduction-mode (CCM) during heavy load for minimum conduction loss by forcing the low-side MOSFET to operate as a synchronous rectifier. An improvement in light-load efficiency is achieved by allowing the converter to operate in diode-emulation mode (DEM) where the low-side MOSFET behaves as a smart-diode, forcing the device to block negative inductor current flow. Positive-going inductor current flows from either the source of the high-side MOSFET, or the drain of the low-side MOSFET. Negative-going inductor current flows into the source of the high-side MOSFET, or into the drain of the low-side MOSFET. When the low-side MOSFET conducts positive inductor current, the phase voltage will be negative with respect to the VSS pin. Conversely, when the low-side MOSFET conducts negative inductor current, the phase voltage will be positive with respect to the VSS pin. Negative inductor current occurs when the output DC load current is less than ½ the inductor ripple current. Sinking negative inductor current through the low-side MOSFET lowers efficiency through unnecessary conduction losses. Efficiency can be further improved with a reduction of unnecessary switching losses by reducing the PWM frequency. The PWM frequency can be configured to automatically make a step-reduction upon entering DEM by forcing a step-increase of the window voltage V W. The window voltage can be configured to increase approximately 30%, 50%, or not at all. The characteristic PWM frequency reduction, coincident with decreasing load, is accelerated by the step-increase of the window voltage. An audio filter can be enabled that briefly turns on the low-side MOSFET gate driver LGATE approximately every 35µs. The converter will enter DEM after detecting three consecutive PWM pulses with negative inductor current. The negative inductor current is detected during the time that the high-side MOSFET gate driver output UGATE is low, with the exception of a brief blanking period. The voltage between the PHASE pin and VSS pin is monitored by a comparator that latches upon detection of the positive phase voltage. The converter will return to CCM after detecting three consecutive PWM pulses with positive inductor current. The inductor current is considered positive if the phase comparator has not been latched while UGATE is low. FN9284.3 July 8, 2010 ISL6263A VDD + DROOP − VSUM ESR DFB RDRP1 CDRP + Σ + CFILTER1 VSEN + RFILTER1 RFILTER2 RTN − RNTC VO − CN RDRP2 DROOP + RNTCP + COUT RS RNTCS OCP ROCSET ROPN1 OCSET − DCR PHASE VDIFF CFILTER2 CFILTER3 ROPN2 10µA LOUT TO VCC_SNS PROCESSOR SOCKET VSS_SNS KELVIN CONNECTIONS FIGURE 5. SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH GPU SOCKET KELVIN SENSING AND INDUCTOR DCR CURRENT SENSING Smooth mode transitions are facilitated by the R3 modulator which correctly maintains the internally synthesized ripple current information throughout mode transitions. Power Monitor The ISL6263A features an IMVP-6+ compliant power monitor output. The voltage between the PMON and VSS pins is proportional to the product of the regulated output voltage and the output inductor current. The output voltage is measured between the VSEN and VSS pins. The output inductor current is proportional to the voltage between the DROOP and VO pins. The PMON pin has source and sink capability for close tracking of transient power events. The power monitor output is expressed as Equation 1: V PMON = V SEN ⋅ ( V DROOP – V O ) ⋅ ( 17.5 ) (EQ. 1) Protection The ISL6263A provides overcurrent protection (OCP), overvoltage protection (OVP), and undervoltage protection (UVP) as shown in Table 3. Overcurrent protection is tied to the voltage droop, which is determined by the resistors selected in “Static and Dynamic Droop using Discrete Resistor Sensing” on page 17. After the load line is set, the OCSET resistor can be selected. The OCP threshold detector is checked every 15µs and will increment a counter if the OCP threshold is exceeded, conversely the counter will be decremented if the load current is below the OCP threshold. The counter will latch an OCP fault when the counter reaches eight. The fastest OCP response for overcurrent levels that are no more than 2.5x the OCP threshold is 120µs, which is eight counts at 15µs 12 each. The ISL6263A protects against hard shorts by latching an OCP fault within 2µs for overcurrent levels exceeding 2.5x the OCP threshold. The value of ROCSET is calculated as Equation 2: I OC ⋅ R droop R OCSET = ---------------------------------10.1μA (EQ. 2) For example: The desired overcurrent trip level, IOC, is 30A, Rdroop load-line is 8mΩ, Equation 2 gives ROCSET = 24kΩ. Undervoltage protection is independent of the overcurrent protection. If the output voltage measured on the VO pin is less than +300mV below the voltage on the SOFT pin for longer than 1ms, the controller will latch a UVP fault. If the output voltage measured on the VO pin is greater than 195mV above the voltage on the SOFT pin for longer than 1ms, the controller will latch an OVP fault. Keep in mind that VSOFT will equal the voltage level commanded by the VID states only after the soft-start capacitor CSOFT has slewed to the VID DAC output voltage. The UVP and OVP detection circuits act on static and dynamic VSOFT voltage. When an OCP, OVP, or UVP fault has been latched, PGOOD becomes a low impedance and the gate driver outputs UGATE and LGATE are pulled low. The energy stored in the inductor is dissipated as current flows through the low-side MOSFET body diode. The controller will remain latched in the fault state until the VR_ON pin has been pulled below the falling VR_ON threshold voltage VVR_ONL or until VDD has gone below the falling POR threshold voltage VVDD_THF. FN9284.3 July 8, 2010 ISL6263A TABLE 3. FAULT PROTECTION SUMMARY OF ISL6263A FAULT TYPE FAULT DURATION PRIOR TO PROTECTION PROTECTION ACTIONS FAULT RESET Overcurrent 120µs LGATE, UGATE, and Cycle PGOOD latched low VR_ON or VDD Short Circuit <2µs LGATE, UGATE, and Cycle PGOOD latched low VR_ON or VDD Overvoltage (+195mV) between VO pin and SOFT pin 1ms LGATE, UGATE, and Cycle PGOOD latched low VR_ON or VDD Severe Overvoltage (+1.55V) between VO pin and VSS pin Immediately Cycle UGATE, and PGOOD latched low, VDD only LGATE toggles ON when VO >1.55V OFF when VO <0.77V until fault reset Undervoltage (-300mV) between VO pin and SOFT pin 1ms LGATE, UGATE, and Cycle PGOOD latched low VR_ON or VDD PWM LGATE 1V UGATE 1V t PDRU t PDRL Gate-Driver Outputs LGATE and UGATE The ISL6263A has internal high-side and low-side N-Channel MOSFET gate-drivers. The LGATE driver is optimized for low duty-cycle applications where the low-side MOSFET conduction losses are dominant. The LGATE pull-down resistance is very low in order to clamp the gate-source voltage of the MOSFET below the VGS(th) at turnoff. The current transient through the low-side gate at turnoff can be considerable due to the characteristic large switching charge of a low r DS(ON) MOSFET. Adaptive shoot-through protection prevents the gate-driver outputs from going high until the opposite gate-driver output has fallen below approximately 1V. The UGATE turn-on propagation delay tPDRU and LGATE turn-on propagation delay tPDRL are found in the “Electrical Specifications” table on page 7. The power for the LGATE gate-driver is sourced directly from the PVCC pin. The power for the UGATE gate-driver is sourced from a boot-strap capacitor connected across the BOOT and PHASE pins. The boot capacitor is charged from PVCC through an internal boot-strap diode each time the low-side MOSFET turns on, pulling the PHASE pin low. FIGURE 6. GATE DRIVER TIMING DIAGRAM Internal Bootstrap Diode 2.0 The ISL6263A has an integrated boot-strap Schottky diode connected from the PVCC pin to the BOOT pin. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. 1.8 1.6 CBOOT_CAP (¬µF A severe overvoltage protection fault occurs immediately after the voltage between the VO and VSS pins exceed the rising severe-overvoltage threshold VOVPS, which is 1.545V, the same reference voltage used by the VID DAC. The ISL6263A will latch UGATE and PGOOD low but unlike other protective faults, LGATE remains high until the voltage between VO and VSS falls below approximately 0.77V, at which time LGATE is pulled low. The LGATE pin will continue to switch high and low at 1.545V and 0.77V until VDD has gone below the falling POR threshold voltage VVDD_THF. This provides maximum protection against a shorted high-side MOSFET while preventing the output voltage from ringing below ground. The severe-overvoltage fault circuit can be triggered after another fault has already been latched. 1.4 The minimum value of the bootstrap capacitor can be calculated from Equation 3: 1.2 1.0 0.8 nC 50 0.4 Q GATE C BOOT ≥ -----------------------ΔV BOOT QGATE = 100nC 0.6 0.2 20nC 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 ΔVBOOT_CAP (V) 0.8 0.9 1.0 FIGURE 7. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE 13 (EQ. 3) where QGATE is the amount of gate charge required to fully charge the gate of the upper MOSFET. The ΔVBOOT term is defined as the allowable droop in the rail of the upper drive. As an example, suppose an upper MOSFET has a gate charge, QGATE , of 25nC at 5V and also assume the droop in FN9284.3 July 8, 2010 ISL6263A the drive voltage at the end of a PWM cycle is 200mV. One will find that a bootstrap capacitance of at least 0.125µF is required. The next larger standard value capacitance is 0.15µF. A good quality ceramic capacitor is recommended. Soft-Start and Soft Dynamic VID Slew Rates The output voltage of the converter tracks VSOFT, the voltage across the SOFT and VSS pins. Shown in Figure 1, the SOFT pin is connected to the output of the VID DAC through the unidirectional soft-start current source ISS or the bidirectional soft-dynamic VID current source IDVID, and the non-inverting input of the error amplifier. Current is sourced from the SOFT pin when ISS is active. The SOFT pin can both source and sink current when IDVID is active. The soft-start capacitor CSOFT changes voltage at a rate proportional to ISS or IDVID. The ISL6263A automatically selects ISS for the soft-start sequence so that the inrush current through the output capacitors is maintained below the OCP threshold. Once soft-start has completed, IDVID is automatically selected for output voltage changes commanded by the VID inputs, charging CSOFT when the output voltage is commanded to rise, and discharging CSOFT when the output voltage is commanded to fall. The IMVP-6+ Render Voltage Regulator specification requires a minimum of 10mV/µs for SLEWRATEGFX. The value for CSOFT must guarantee the minimum slew-rate of 10mV/µs when the soft-dynamic VID current source I DVID is the minimum specified value in the “Electrical Specifications” table on page 8. The value of CSOFT, can be calculated from Equation 4: I DVIDmin 180μA C SOFT = ------------------------- = ------------------ = 0.018μF 10k 10mV⎞ ⎛ --------------⎝ μs ⎠ (EQ. 4) Choosing the next lower standard component value of 0.015µF will guarantee 10mV/µs SLEWRATEGFX. This choice of CSOFT controls the startup slew-rate as well. One should expect the output voltage during soft-start to slew to the voltage commanded by the VID settings at a nominal rate given by Equation 5: I SS dV SOFT 42μA 2.8mV - = ----------------------- ≈ ---------------------------------------- = -----------------dt C SOFT 0.015μF μs (EQ. 5) Note that the slewrate is the average rate of change between the initial and final voltage values. RBIAS Current Reference The RBIAS pin is internally connected to a 1.545V reference through a 3kΩ resistance. A bias current is established by connecting a ±1% tolerance, 150kΩ resistor between the RBIAS and VSS pins. This bias current is mirrored, creating the reference current I OCSET that is sourced from the OCSET pin. Do not connect any other components to this pin, as they will have a negative impact on the performance of the IC. 14 Setting the PWM Switching Frequency The R3 modulator scheme is not a fixed-frequency architecture, lacking a fixed-frequency clock signal to produce PWM. The switching frequency increases during the application of a load to improve transient performance. The static PWM frequency varies slightly depending on the input voltage, output voltage, and output current, but this variation is normally less than 10% in continuous conduction mode. Refer to Figure 2 and find that resistor R FSET is connected between the V W and COMP pins. A current is sourced from VW through RFSET creating the synthetic ripple window voltage signal V W which determines the PWM switching frequency. The relationship between the resistance of RFSET and the switching frequency in CCM is approximated by Equation 6: –6 ( T – 0.5 × 10 ) R FSET = ----------------------------------------– 12 400 × 10 (EQ. 6) For example, the value of RFSET for 300kHz operation is approximately: –6 –6 ( 3.33 × 10 – 0.5 × 10 ) 3 7.1 ×10 = -------------------------------------------------------------------– 12 400 × 10 (EQ. 7) This relationship only applies to operation in constant conduction mode because the PWM frequency naturally decreases as the load decreases while in diode emulation mode. Static Droop Design Using DCR Sensing The ISL6263A has an internal differential amplifier to accurately regulate the voltage at the processor die. For DCR sensing, the process to compensate the DCR resistance variation takes several iterative steps. Figure 2 shows the DCR sensing method. Figure 8 shows the simplified model of the droop circuitry. The inductor DC current generates a DC voltage drop on the inductor DCR. Equation 8 gives this relationship: V DCR = I o ⋅ DCR (EQ. 8) An R-C network senses the voltage across the inductor to get the inductor current information. RNTCEQ represents the NTC network consisting of RNTC, RNTCS, and RNTCP. The choice of RS will be discussed in the following section. The first step in droop load line compensation is to adjust RNTCEQ, and RS such that the correct droop voltage appears even at light loads between the VSUM and VO pins. As a rule of thumb, the voltage drop VN across the RNTCEQ network, is set to be 0.3x to 0.8x VDCR. This gain, defined as G1, provides a reasonable amount of light load signal from which to derive the droop voltage. FN9284.3 July 8, 2010 ISL6263A It is recommended to begin your droop design using the RNTC, RNTCS, and RNTCP component values of the evaluation board available from Intersil. The NTC network resistor value is dependent on temperature and is given by Equation 9: ( R NTC + R NTCS ) ⋅ R NTCP R N ( T ) = -----------------------------------------------------------------------R NTC + R NTCS + R NTCP (EQ. 9) The gain of the droop amplifier circuit is shown in Equation 15: R DRP2 k droopamp = 1 + ------------------R DRP1 G1, the gain of VN to VDCR, is also dependent on the temperature of the NTC thermistor shown in Equation 10: RN ( T ) G 1 ( T ) = ------------------------------RN ( T ) + RS After determining RS and RNTCEQ networks, use Equation 16 to calculate the droop resistances RDRP1 and RDRP2. (EQ. 10) The inductor DCR is a function of temperature and is approximately given by Equation 11: DCR ( T ) = DCR 25°C ⋅ ( 1 + 0.00393 ⋅ ( T – 25°C ) ) (EQ. 15) R droop ⎞ ⎛⎛ ⎞ R DRP2 = ⎜ ⎜ -------------------------------------------⎟ – 1⎟ ⋅ R DRP1 DCR ⋅ G ⎝⎝ ⎠ 1 ( 25°C )⎠ (EQ. 11) (EQ. 16) The droop amplifier output voltage divided by the total load current is given by Equation 12: Rdroop is 8mΩ per Intel IMVP-6+ specification and RDRP1 is typically 1kΩ. R droop = G 1 ( T ) ⋅ DCR 25°C ⋅ ( 1 + 0.00393 ⋅ ( T – 25°C ) ) ⋅ k droopamp The effectiveness of the RNTCEQ network is sensitive to the coupling coefficient between the NTC thermistor and the inductor. The NTC thermistor should be placed in the closet proximity of the inductor. (EQ. 12) Rdroop is the actual load line slope, and 0.00393 is the temperature coefficient of the copper. To make Rdroop independent of the inductor temperature, it is desired to have: G 1 ( T ) ⋅ ( 1 + 0.00393 ⋅ ( T – 25°C ) ) ≅ G 1t arg et To see whether the NTC network successfully compensates the DCR change over-temperature, one can apply full load current and wait for the thermal steady state and see how much the output voltage deviates from the initial voltage reading. A good compensation can limit the drift to less than 2mV. If the output voltage is decreasing when the temperature increases, that ratio between the NTC thermistor value and the rest of the resistor divider network has to be increased. Following the evaluation board value and layout of NTC placement will minimize the engineering time. (EQ. 13) where G1target is the desired ratio of Vn / VDCR. Therefore, the temperature characteristics G1 is described by Equation 14: G 1t arg et G 1 ( T ) = --------------------------------------------------------------------( 1 + 0.00393 ⋅ ( T – 25°C ) ) (EQ. 14) VDD 10µA OCSET + RS VSUM DFB DROOP VO VDCR RDRP1 − + DROOP − RNTCEQ + CN OCP ROCSET RDRP2 − FIGURE 8. EQUIVALENT MODEL FOR DROOP CIRCUIT USING INDUCTOR DCR CURRENT SENSING 15 FN9284.3 July 8, 2010 ISL6263A VDD 10µA OCSET OCP + DROOP − + RS VSUM DFB DROOP VO VRSNS RDRP1 − CN + ROCSET RDRP2 − FIGURE 9. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DISCRETE RESISTOR CURRENT SENSING The current sensing traces should be routed directly to the inductor pads for accurate DCR voltage drop measurement. However, due to layout imperfection, the calculated RDRP2 may still need slight adjustment to achieve optimum load line slope. It is recommended to adjust RDRP2 after the system has achieved thermal equilibrium at full load. For example, if the maximum load current is 20A, one should apply a 20A load current and look for 160mV output voltage droop. If the voltage droop is 155mV, the new value of RDRP2 is calculated in Equation 17: 160mV R DRP2new = ------------------- ⋅ ( R DRP1 + R DRP2 ) – R DRP1 155mV Vcore ΔIcore Vcore ΔVcore ΔVcore= ΔIcore×Rdroop FIGURE 10. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS (EQ. 17) For the best accuracy, the effective resistance on the DFB and VSUM pins should be identical so that the bias current of the droop amplifier does not cause an offset voltage. Dynamic Droop Capacitor Design Using DCR Sensing Figure 10 shows the desired waveforms during load transient response. VCCGFX needs to follow the change in Icore as close as possible. The transient response of VCCGFX is determined by several factors, namely the choice of output inductor, output capacitor, compensator design, and the design of droop capacitor CN. If CN is designed correctly, the voltage VDROOP -VO will be an excellent representation of the inductor current. Given the correct CN design, VCCGFX has the best chance of tracking ICORE, if not, its voltage will be distorted from the actual waveform of the inductor current and worsens the transient response. Figure 11 shows the transient response when CN is too small allowing VCCGFX to sag excessively during the load transient. Figure 12 shows the transient response when CN is too large. VCCGFX takes too long to droop to its final value. 16 icore icore Vcore Vcore FIGURE 11. LOAD TRANSIENT RESPONSE WHEN CN IS TOO SMALL icore Vcore Vcore FIGURE 12. LOAD TRANSIENT RESPONSE WHEN CN IS TOO LARGE FN9284.3 July 8, 2010 ISL6263A The current sensing network consists of RNTCEQ, RS, and CN. The effective resistance is the parallel of RNTCEQ and RS. The RC time constant of the current sensing network needs to match the L/DCR time constant of the inductor to get the correct representation of the inductor current waveform. Equation 18 shows this relationship: Equation 22 shows the droop amplifier gain. So the actual droop is given by Equation 22: ⎛ R NTCEQ ⋅ R S ⎞ L -⎟ ⋅ C N ------------- = ⎜ -------------------------------------DCR ⎝ R NTCEQ + R S⎠ ⎛ R droop ⎞ R DRP2 = R DRP1 ⋅ ⎜ ------------------- – 1⎟ ⎝ R SNS ⎠ (EQ. 18) (EQ. 19) For example: L = 0.45µH, DCR = 1.1mΩ, RS = 7.68kΩ, and RNTCEQ = 3.4kΩ: ⎛ 0.45μH --------------------⎞ ⎝ 1.1mΩ ⎠ C N = ------------------------------------------------- = 174nF 3.4kΩ ⋅ 7.68kΩ ⎞ ⎛ -----------------------------------------⎝ 3.4kΩ + 7.68kΩ⎠ (EQ. 20) Since the inductance and the DCR typically have 20% and 7% tolerance respectively, CN needs to be fine tuned on the actual board by examining the transient voltage. It is recommended to choose the minimum capacitance based on the maximum inductance. CN also needs to be a high-grade capacitor such as NPO/COG or X7R with tight tolerance. The NPO/COG caps are only available in small capacitance values. In order to use such capacitors, the resistors and thermistors surrounding the droop voltage sensing and droop amplifier need to be scaled up 10X to reduce the capacitance by 10X. Static and Dynamic Droop using Discrete Resistor Sensing Figure 3 shows a detailed schematic using discrete resistor sensing of the inductor current. Figure 9 shows the equivalent circuit. Since the current sensing resistor voltage represents the actual inductor current information, RS and CN simply provide noise filtering. A low ESL sensing resistor is strongly recommended for RSNS because this parameter is the most significant source of noise that affects discrete resistor sensing. It is recommended to start out using 100Ω for RS and 47pF for CN. Since the current sensing resistance changes very little with temperature, the NTC network is not needed for thermal compensation. Discrete resistor sensing droop design follows the same approach as DCR sensing. The voltage on the current sensing resistor is given by Equation 21: V RSNS = I o ⋅ R SNS (EQ. 21) 17 (EQ. 22) Solution to RDRP2 yields Equation 23: (EQ. 23) For example: Rdroop = 8.0mΩ, RSNS = 1.0mΩ, and RDRP1 = 1kΩ, RDRP2 then = 7kΩ. Solution of CN yields Equation 19: L ⎞ ⎛ ------------⎝ DCR⎠ C N = -------------------------------------------⎛ R NTCEQ ⋅ R S ⎞ ⎜ ---------------------------------------⎟ ⎝ R NTCEQ + R S⎠ R DRP2⎞ ⎛ R droop = R SNS ⋅ ⎜ 1 + -------------------⎟ R DRP1⎠ ⎝ The current sensing traces should be routed directly to the current sensing resistor pads for accurate measurement. However, due to layout imperfection, the calculated RDRP2 may still need slight adjustment to achieve optimum load line slope. It is recommended to adjust RDRP2 after the system has achieved thermal equilibrium at full load. Dynamic Mode of Operation - Compensation Parameters The voltage regulator is equivalent to a voltage source in series with the output impedance. The voltage source is the VID state and the output impedance is 8.0mΩ in order to achieve the 8.0mV/A load line. It is highly recommended to design the compensation such that the regulator output impedance is 8.0mΩ. Intersil provides a spreadsheet to calculate the compensator parameters. Caution needs to be used in choosing the input resistor to the FB pin. Excessively high resistance will cause an error to the output voltage regulation due to the bias current flowing through the FB pin. It is recommended to keep this resistor below 3kΩ. Layout Considerations As a general rule, power should be on the bottom layer of the PCB and weak analog or logic signals are on the top layer of the PCB. The ground-plane layer should be adjacent to the top layer to provide shielding. Inductor Current Sensing and the NTC Placement It is crucial that the inductor current be sensed directly at the PCB pads of the sense element, be it DCR sensed or discrete resistor sensed. The effect of the NTC on the inductor DCR thermal drift is directly proportional to its thermal coupling with the inductor and thus, the physical proximity to it. Signal Ground and Power Ground The ground plane layer should have a single point connection to the analog ground at the VSS pin. The VSS island should be located under the IC package along with the weak analog traces and components. The paddle on the bottom of the ISL6263A QFN package is not electrically connected to the IC however, it is recommended to make a good thermal connection to the VSS island using several vias. Connect the input capacitors, the output capacitors, and the source of the lower MOSFETs to the power ground plane. FN9284.3 July 8, 2010 ISL6263A LGATE, PVCC, and PGND RBIAS PGND is the return path for the pull-down of the LGATE low-side MOSFET gate driver. Ideally, PGND should be connected to the source of the low-side MOSFET with a low-resistance, low-inductance path. The LGATE trace should be routed in parallel with the trace from the PGND pin. These two traces should be short, wide, and away from other traces because of the high peak current and extremely fast dv/dt. PVCC should be decoupled to PGND with a ceramic capacitor physically located as close as practical to the IC pins. The resistor RRBIAS should be placed in close proximity to the ISL6263A using a noise-free current return path to the VSS pin. VIAS TO GROUND PLANE GND VOUT INDUCTOR HIGH-SIDE MOSFETS OUTPUT CAPACITORS SCHOTTKY DIODE PHASE NODE LOW-SIDE MOSFETS INPUT CAPACITORS VIN FIGURE 13. TYPICAL POWER COMPONENT PLACEMENT UGATE, BOOT, and PHASE PHASE is the return path for the entire UGATE high-side MOSFET gate driver. The layout for these signals require similar treatment, but to a greater extent, than those for LGATE, PVCC, and PGND. These signals swing from approximately VIN to VSS and are more likely to couple into other signals. VSEN and RTN These traces should be laid out as noise sensitive. For optimum load line regulation performance, the traces connecting these two pins to the Kelvin sense leads of the processor should be laid out away from rapidly rising voltage nodes, (switching nodes) and other noisy traces. The filter capacitors CFILTER1, CFILTER2, and CFILTER3 used in conjunction with filter resistors RFILTER1 and RFILTER2 form common mode and differential mode filters as shown in Figure 8. The noise environment of the application and actual board layout conditions will drive the extent of filter complexity. The maximum recommended resistance for RFILTER1 and RFILTER2 is approximately 10Ω to avoid interaction with the 50kΩ input resistance of the remote sense differential amplifier. The physical location of these resistors is not as critical as the filter capacitors. Typical capacitance values for CFILTER1, CFILTER2, and CFILTER3 range between 330pF to 1000pF and should be placed near the IC. PMON, SOFT, OCSET, V W, COMP, FB, VDIFF, DROOP, DFB, VO, and VSUM The traces and components associated with these pins require close proximity to the IC as well as close proximity to each other. This section of the converter circuit needs to be located above the island of analog ground with the single-point connection to the VSS pin. Resistor RS Resistor RS is preferably located near the boundary between the power ground and the island of analog ground connected to the VSS pin. VID<0:4>, AF_EN, PGOOD, and VR_ON These are logic signals that do not require special attention. FDE This logic signal should be treated as noise sensitive and should be routed away from rapidly rising voltage nodes, (switching nodes) and other noisy traces. VIN The VIN signal should be connected near the drain of the high-side MOSFET. Copper Size for the Phase Node The parasitic capacitance and parasitic inductance of the phase node should be kept very low to minimize ringing. It is best to limit the size of the PHASE node copper in strict accordance with the current and thermal management of the application. An MLCC should be connected directly across the drain of the high-side MOSFET and the source of the low-side MOSFET to suppress turn-off voltage spikes. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN9284.3 July 8, 2010 ISL6263A Package Outline Drawing L32.5x5 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 02/07 4X 3.5 5.00 28X 0.50 A B 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 32 25 1 5.00 24 3 .10 ¬± 0 . 1 17 (4X) 8 0.15 9 16 TOP VIEW 0.10 M C A B + 0.07 32X 0.40 ¬± 0.1 4 32X 0.23 - 0.05 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ¬± 0. C BASE PLANE SEATING PLANE 0.08 C ( 4. 80 TYP ) ( ( 28X 0 . 5 ) SIDE VIEW 3. 10 ) (32X 0 . 23 ) C 0 . 2 REF 5 ( 32X 0 . 60) 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ¬± 0.0 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 19 FN9284.3 July 8, 2010