ISL8118 Data Sheet August 12, 2014 FN6325.3 3.3V to 20V, Single-Phase PWM Controller with Integrated 2A/4A MOSFET Drivers Features The ISL8118 is a single-phase PWM controller featuring an input voltage range of +3.3V to +20V and integrated MOSFET drivers. Utilizing voltage-mode operation with input voltage feed-forward compensation, the ISL8118 maintains a constant loop gain, providing optimal transient response for applications with a wide input operating voltage range. • High-Speed 2A/4A MOSFET Gate Drivers that Operate from 2.9V to 5.6V The output voltage can be precisely regulated down to 0.591V with a system tolerance of ±1.0% over the industrial temperature range and line and load variations. A external reference input is provided to bypass the internal reference for voltage tracking or DDR memory applications. The compact 28 Ld 5x5 QFN package, integrated linear regulator as well as the external linear regulator drive option, integrated differential remote sense amplifier and integrated voltage margining with adjustable upper and lower settings decrease external component count and reduce board space requirements. • Internal Linear Regulator Programmable soft-start with pre-biased load capability, adjustable operating frequency from 250kHz to 2MHz, sourcing and sinking overcurrent protection, overvoltage and undervoltage protection, and power-good indication with programmable delay combine to make the ISL8118 a superior choice for many power supply systems. Pinout • Wide Input Voltage Range: +3.3V to +20V • Operating Junction Temperature Range –40°C to +125°C • External Reference Input • Input Voltage Feed-forward Compensation • External Linear Regulator Drive Available • High System Accuracy: - ±0.68% Over the Range of 0°C to +70°C - ±1.00% Over the Range of -40°C to +85°C • Programmable Operating Frequency from 250kHz to 2MHz • Programmable Soft-Start with Pre-biased Load Capability • Integrated Unity-Gain Differential Remote Sense Amplifier • Enable Input with Voltage Monitoring Capability • Integrated Voltage Margining with Independent Upper and Lower Settings • Overvoltage and Undervoltage Protection • Low-Side and High-Side MOSFET Current Sensing • Overcurrent Protection for Sourcing and Sinking Currents • Power-Good Indicator with Programmable Delay • Compact 28 Ld 5x5 QFN Package ISL8118 (28 LD 5x5 QFN) TOP VIEW VDIFF GND FB COMP FSET BSOC TSOC • Pb-Free (RoHS Compliant) 28 27 26 25 24 23 22 Applications • Telecom and Datacom Servers • Point of Load Modules VSENSP 1 21 BOOT • Routers and Switchers VSENSN 2 20 TGATE • High Current Distributed Power Supplies REFOUT 3 19 LX Ordering Information 18 PGND 17 BGATE 16 PVCC GND REFIN 4 SS 5 OFSP 6 BOTTOM SIDE PAD PART NUMBER (Note) ISL8118CRZ ISL8118CRZ ISL8118IRZ 15 7 1 14 VIN 13 VFF 12 EN 11 PGOOD 10 PGDLY 9 MARGIN 8 VCC OFSN EXDRV PART MARKING ISL8118IRZ TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # 0 to +70 28 Ld 5x5 QFN L28.5x5 -40 to +85 28 Ld 5x5 QFN L28.5x5 Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2006, 2009, 2012, 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Submit Document Feedback Block Diagram VCC EN EXDRV VIN POWER-ON REFERENCE VREF = 0.591V REFIN RESET (POR) INTERNAL SERIES LINEAR EXTERNAL SERIES LINEAR DRIVER TSOC REFOUT 2 100A MARGIN OFSP OFSN BOOT SOFT-START AND FAULT LOGIC VOLTAGE MARGINING SOURCE OCP TGATE OTA FB EA GATE CONTROL LOGIC LX COMP PVCC VCC OV/UV COMP 800mV OSCILLATOR BGATE SOURCE OCP PGND PGOOD COMP VSENSP G = -1 VSENSN GND GND G=1 UNITY GAIN DIFF AMP 100A SINKING OCP FN6325.3 August 12, 2014 VDIFF PGDLY PGOOD BSOC VFF FSET ISL8118 PWM COMP SS ISL8118 Typical Application I (Internal Linear Regulator with Remote Sense) +3.3V to +20V LIN RCC DBOOT CHFIN CF2 CF1 RBOOT VCC VIN CBIN PVCC INTERNAL 5.6V BIAS LINEAR REGULATOR VFF BOOT RTSOC TSOC CF3 CBOOT CTSOC TGATE Q1 LOUT VOUT EN VCC LX REFIN CPGDLY RFSET CHFOUT REFOUT BGATE PGOOD PGND BSOC PGDLY Q2 RBSOC ISL8118 10 CBSOC FSET 10 COMP C2 C1 MARGIN C3 ZFB R3 R2 R1 FB ROFSP ZIN VDIFF OFSP RMARG ROFSN CBOUT RFB VSENSP OFSN VSENSE+ CSEN ROS SS VSENSN EXDRV CSS Submit Document Feedback 3 GND VSENSE- GND FN6325.3 August 12, 2014 ISL8118 Typical Application II (External Linear Regulator without Remote Sense) +3.3V to +20V LIN DBOOT CHFIN CF2 CLC RLC RDRV RCC CF1 VCC CBIN RBOOT PVCC BOOT EXDRV RTSOC TSOC VIN CBOOT CF3 CTSOC VFF TGATE Q1 LOUT REFOUT VCC VOUT LX REFIN EN PGOOD CPGDLY RFSET PGDLY CHFOUT Q2 BGATE PGND RBSOC BSOC ISL8118 FSET COMP CBSOC ZFB C2 C3 C1 MARGIN ROFSP R3 R2 ZIN R1 FB OFSP ROS VDIFF RMARG ROFSN CBOUT VCC OFSN VSENSP Rvdiff1 SS CSS Submit Document Feedback VSENSN GND 4 GND RvdiffOS FN6325.3 August 12, 2014 ISL8118 Typical Application III (Dual Data Rate I or II) VDDQ 1.8V or 2.5V LIN DBOOT 5V CHFIN RCC CBIN CF2 CF1 VIN REN1 REN2 VCC PVCC VFF BOOT EN TSOC RTSOC CBOOT CF4 CTSOC VTT TGATE Q1 LOUT 1.25V (DDR I) 0.9V (DDR II) 1K LX REFIN 15nF 1K CHFOUT REFOUT BGATE PGOOD PGND DIMM CPGDLY RFSET PGDLY Q2 RBSOC BSOC ISL8118 FSET COMP CBSOC ZFB C2 C3 C1 MARGIN ROFSP R3 R2 R1 FB OFSP CBOUT ZIN VDIFF RMARG ROFSN RFB VSENSP OFSN VSENSN CSEN SS EXDRV CSS Submit Document Feedback 5 GND GND FN6325.3 August 12, 2014 ISL8118 Absolute Maximum Ratings Thermal Information Input Voltage, VIN, VFF . . . . . . . . . . . . . . . . . . . . . . -0.3V to +22.0V Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +36V LX Voltage, VLX . . . . . . . . . . . . . . . . . VBOOT - 6V to VBOOT + 0.3V Boot to LX Voltage, VBOOT - VLX . . . . . . . . . . . . . . . . . . . . . . . . .6V Other Input or Output Voltages . . . . . . . . . . . . . -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Thermal Resistance (Notes 1, 2) JA (°C/W) JC (°C/W) QFN Package . . . . . . . . . . . . . . . . . . 32 5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profilesee link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Input Voltage, VIN, VFF . . . . . . . . . . . . . . . . . . . . 3.3V to 20V 10% Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . 2.9V to 5.6V Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . 2.9V to 5.6V Boot to LX Voltage (Overcharged), VBOOT - VLX . . . . . . . . . . . .<6V Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. 2. JC, "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS INPUT SUPPLY CURRENTS Nominal VIN Supply Current IVIN VIN = VCC = PVCC = 5V, Fs = 600kHz, TGATE and BGATE Open - 0.5 1 mA Nominal VCC Supply Current IVCC VIN = VCC = PVCC = 5V, Fs = 600kHz, TGATE and BGATE Open - 8 13 mA Nominal PVCC Supply Current IPVCC VIN = VCC = PVCC = 5V; Fs = 600kHz, TGATE and BGATE Open - 3 4 mA Shutdown VIN Supply Current IVIN_S EN = 0V, VCC = PVCC = VIN = 5V - 0.5 1 mA Shutdown VCC Supply Current IPVCC_S EN = 0V, VCC = PVCC = VIN = 5V - 1 2 mA IVCC_S EN = 0V, VCC = PVCC = VIN = 5V - 3 4 mA Shutdown PVCC Supply Current ENABLE Input Reference Voltage VEN_REF 0.485 0.500 0.515 V Hysteresis Source Current IEN_HYS 7.5 10 11.5 µA VEN - VCC+0.3 - V Maximum Input Voltage OSCILLATOR Nominal Maximum Frequency OSCFMAX (Note 3) - 2000 - kHz Nominal Minimum Frequency OSCFMIN (Note 3) - 250 - kHz -17 - +17 % - 0.16*VFF - VP-P Total Variation OSC Ramp Amplitude VOSC Ramp Bottom FSET = 250kHz to 2MHz, VFF = 3.3V to 20V VOSC_MIN Minimum Usable VFF Voltage VFF VCC = 5V - 1.0 - V - 3.3 - V POWER-ON RESET Rising VCC Threshold PORVCC_R 2.79 - 2.89 V Falling VCC Threshold PORVCC_F 2.59 - 2.69 V Submit Document Feedback 6 FN6325.3 August 12, 2014 ISL8118 Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL VCC Hysteresis TEST CONDITIONS MIN TYP MAX UNITS PORVCC_H 187 215 250 mV Rising PVCC Threshold PORPVCC_R 2.79 - 2.91 V Falling PVCC Threshold PORPVCC_F 2.59 - 2.70 V PVCC Hysteresis PORPVCC_H 193 215 250 mV PORVFF_R 1.48 - 1.54 V Falling VFF Threshold PORVFF_F 1.35 - 1.41 V VFF Hysteresis PORVFF_H 127 137 146 mV Rising VFF Threshold REFERENCE Reference Voltage System Accuracy VREF_COM TA = 0°C to +70°C 0.587 0.591 0.595 V VREF_IND TA = -40°C to +85°C 0.585 0.591 0.597 V VSYS_COM TA = 0°C to +70°C -0.68 - 0.68 % VSYS_IND TA = -40°C to +85°C -1.0 - 1.0 % 0.068 - VCC-1.8V V -1.8 0 2.2 mV - 19 - mA REFERENCE TRACKING Input Voltage Range VREFIN External Reference Offset VREFIN_OS Maximum Drive Current VCC = 5V REFIN = 0.6V IREFOUT CL = 1µF, VCC = 5V, REFOUT = 1.25V VREFOUT CL = 1µF 0.01 - VCC-1.8V V Maximum Output Voltage Offset VREFOUT_OS CL = 1µF REFOUT = 1.25V -6 - 11 mV Minimum Load Capacitance CREFOUT_MIN REFOUT = 1.25V - 1.0 - µF VCC-0.6 - VCC-0.58 V Output Voltage Range Input Disable Voltage VREFIN_DIS VCC = 5V ERROR AMPLIFIER RL = 10k, CL = 100p, at COMP Pin - 88 - dB UGBW RL = 10k, CL = 100p, at COMP Pin - 15 - MHz SR RL = 10k, CL = 100p, at COMP Pin - 6 - V/µs UG Standard Instrumentation Amplifier - 0 - dB - 20 - MHz DC Gain Unity Gain-Bandwidth Slew Rate DIFFERENTIAL AMPLIFIER DC Gain Unity Gain Bandwidth UGBW Slew Rate SR COMP = 10pF - 10 - V/µs -1.9 0 1.9 mV - 6 Input Common Mode Range Max - VCC-1.8 - V Input Common Mode Range Min - -0.2 - V - VCC - V Offset Negative Input Source Current IVSENSN VSENSN Disable Voltage VVSEN_DIS µA OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA) DC Gain CSS = 0.1µF, at SS Pin - 88 - dB Drive Capability CSS = 0.1µF, at SS Pin 30 37 44 µA PWM Maximum Duty Cycle DMAX Leading and Trailing-edge Modulation - 100 - % Minimum Duty Cycle DMIN Leading and Trailing-edge Modulation - 0 - % RTGATE 500mA Source Current, PVCC = 5.0V - 1.0 - GATE DRIVERS TGATE Source Resistance Submit Document Feedback 7 FN6325.3 August 12, 2014 ISL8118 Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS TGATE Source Saturation Current ITGATE VTGATE-LX = 2.5V, PVCC = 5.0V - 2.0 - A TGATE Sink Resistance RTGATE 500mA Sink Current, PVCC = 5.0V - 1.0 - TGATE Sink Saturation Current ITGATE VTGATE-LX = 2.5V, PVCC = 5.0V - 2.0 - A Bgate Source Resistance RBGATE 500mA Source Current, PVCC = 5.0V - 1.0 - Bgate Source Saturation Current IBGATE VBGATE = 2.5V, PVCC = 5.0V - 2.0 - A Bgate Sink Resistance RBGATE 500mA Sink Current, PVCC = 5.0V - 0.4 - Bgate Sink Saturation Current IBGATE VBGATE = 2.5V, PVCC = 5.0V - 4.0 - A - 200 - mA - 2 3.9 5.3 5.5 5.71 V VIN = 0V to VIN step, PVCC < 2.0V at VIN application; VIN > 6.5V - 1 - V/µs VIN = 2.0V to VIN step, 2.0V < PVCC at VIN application; VIN > 6.5V - 0.05 - V/µs LIN_DRV = VIN = 20V 1.30 4.17 5.30 mA LIN_DRV = VIN = 3.3V 1.67 3.88 4.67 mA BSOC = 0V to VCC - 1.0V, TA = 0°C to +70°C 86 100 107 µA BSOC = 0V to VCC - 1.0V, TA = -40°C to +85°C 84 100 109 µA - ±2 - mV 91 100 106 µA TSOC = 0.8V to 22V TA = -40°C to +85°C 89 100 107 µA TSOC = 0.3V to 0.8V 84 - 107 µA - ±2 - mV INTERNAL LINEAR REGULATOR Maximum Current IVIN Saturated Equivalent Impedance RLIN VIN = 3.3V Linear Regulator Voltage PVCC VIN = 20V, Load = 0 to 100mA Maximum VIN DV/DT VINDV/DT_Max EXTERNAL LINEAR REGULATOR Maximum Sinking Drive Current LIN_DRV OVERCURRENT PROTECTION (OCP) Bottom Side OCP (BSOC) Current Source IBSOC BSOC Maximum Offset Error IBSOC_OFSET Top Side OCP (TSOC) Current Source ITSOC ITSOC_LOW TSOC Maximum Offset Error ITSOC_OFSET Vcc = 2.9V and 5.6V tSAMPLE < 10µs TSOC = 0.8V to 22V TA = 0°C to +70°C VCC = 2.9V and 5.5V tSAMPLE < 10µs POWER GOOD MONITOR Undervoltage Rising Trip Point VUVR -7% -9% -11% VSS Undervoltage Falling Trip Point VUVF -13% -15% -17% VSS Overvoltage Rising Trip Point VOVR 13% 15% 17% VSS Overvoltage Falling Trip Point VOVF 7% 9% 11% VSS - 7.1 - ms PGOOD Delay tPGDLY CPGDLY = 0.1µF PGOOD Delay Source Current IPGDLY 17 21 24 µA PGOOD Delay Threshold Voltage VPGDLY 1.45 1.49 1.52 V PGOOD Low Output Voltage IPG_LOW IPGOOD = 5mA - - 0.150 V Maximum Sinking Current IPG_MAX VPGOOD = 0.8V 23 - - mA Maximum Open Drain Voltage VPG_MAX VCC = 3.3V - 6 - V MARGINING CONTROL Minimum Margining Voltage of Internal Reference VMARG RMARG = 10k, ROFSN = 6.01k, MAR_CRTL = 0V -187 -197 -209 mV Maximum Margining Voltage of Internal Reference VMARG RMARG = 10k, ROFSP = 6.01k, MAR_CRTL = VCC 185 197 208 mV Submit Document Feedback 8 FN6325.3 August 12, 2014 ISL8118 Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL TEST CONDITIONS NMARG = (VOFSN-VOFSP)/VMARG MIN TYP MAX UNITS Margining Transfer Ratio NMARG 4.84 5 5.22 SDR Positive Margining Threshold MARGIN 1.51 1.8 2.02 V Negative Margining Threshold MARGIN 0.75 0.9 1.05 V Tri-state Input Level MARGIN 1.21 1.325 1.40 V Disable Mode NOTE: 3. Limits should be considered typical and are not production tested. Functional Pin Descriptions VSENSP (Pin 1) This pin provides differential remote sense for the ISL8118. It is the positive input of a standard instrumentation amplifier topology with unity gain, and should connect to the positive rail of the load/processor. The voltage at this pin should be set equal to the internal system reference voltage (0.591V typical). VSENSN (Pin 2) This pin provides differential remote sense for the regulator. It is the negative input of the instrumentation amplifier, and should connect to the negative rail of the load/processor. Typically 6µA is sourced from this pin. The output of the remote sense buffer is disabled (High Impedance) by pulling VSENSN to VCC. REFOUT (Pin 3) This pin connects to the unmargined system reference through an internal buffer. It has a 19mA drive capability with an output common mode range of GND to VCC. The REFOUT buffer requires at least 1µF of capacitive loading to be stable. This pin should not be left floating. REFIN (Pin 4) reference is developed at the OFSP pin across resistor ROFSP. The voltage on OFSP is driven from OFSN through RMARG. The resulting voltage differential between OFSP and OFSN is divided by 5 and imposed on the system reference. The maximum designed offset of 1V between OFSP and OFSN pins translates to a 200mV offset. OFSN (Pin 7) This pin sets the negative margining offset voltage. Resistors should be connected to GND (ROFSN) and OFSP (RMARG) from this pin. With MARGIN logic low, the internal 0.591V reference is developed at the OFSN pin across resistor ROFSN. The voltage on OFSN is driven from OFSP through RMARG. The resulting voltage differential between OFSP and OFSN is divided by 5 and imposed on the system reference. The maximum designed offset of -1V between OFSP and OFSN pins translates to a -200mV offset of the system reference. VCC (Pin 8, Analog Circuit Bias) This pin provides power for the ISL8118 analog circuitry. The pin should be connected to a 2.9V to 5.6V bias through an RC filter from PVCC to prevent noise injection into the analog circuitry. This pin can be powered off the internal or external linear regulator options. When the external reference pin (REFIN) is NOT within ~800mV of VCC, the REFIN pin is used as the system reference instead of the internal 0.591V reference. The recommended REFIN input voltage range is ~60mV to VCC - 1.8V. MARGIN (Pin 9) SS (Pin 5) Provides the ability to delay the output of the PGOOD assertion by connecting a capacitor from this pin to GND. A 0.1µF capacitor produces approximately a 5ms delay. This pin provides soft-start functionality for the ISL8118. A capacitor connected to ground along with the internal 38µA Operational Transconductance Amplifier (OTA), sets the softstart interval of the converter. This pin is directly connected to the non-inverting input of the Error Amplifier. To prevent noise injection into the error amplifier, the SS capacitor should be located within 150 mils of the SS and GND pins. OFSP (Pin 6) This pin sets the positive margining offset voltage. Resistors should be connected to GND (ROFSP) and OFSN (RMARG) from this pin. With MARGIN logic low, the internal 0.591V Submit Document Feedback 9 The MARGIN pin controls margining function, a logic high enables positive margining, a logic low sets negative margining, a high impedance disables margining. PGDLY (Pin 10) PGOOD (Pin 11) Provides an open drain Power Good signal when the output is within 9% of nominal output regulation point with 6% hysteresis (15%/9%), and after soft-start is complete. PGOOD monitors the VDIFF pin. EN (Pin 12) This pin is compared with an internal 0.50V reference and enables the soft-start cycle. This pin also can be used for FN6325.3 August 12, 2014 ISL8118 voltage monitoring. A 10µA current source to GND is active while the part is disabled, and is inactive when the part is enabled. This provides functionality for programmable hysteresis when the EN pin is used for voltage monitoring. TGATE (Pin 20) This pin provides the drive for the top side MOSFET and should be connected to its gate. BOOT (Pin 21) VFF (Pin 13) The voltage at this pin is used for input voltage feed forward compensation and sets the internal oscillator ramp peak to peak amplitude at 0.16*VFF. An external RC filter may be required at this pin in noisy input environments. The minimum recommended VFF voltage is 2.97V. VIN (Pin 14, Internal Linear Regulator Input) This pin should be tied directly to the input rail when using the internal or external linear regulator options. It provides power to the External/Internal Linear drive circuitry. When used with an external 3.3V to 5V supply, this pin should be tied directly to PVCC. EXDRV (Pin 15, External Linear Regulator Drive) This pin allows the use of an external pass element to power the IC for input voltages above 5.0V. It should be connected to GND when using an external 5V supply or the internal linear regulator. When using the external linear regulator option, this pin should be connected to the gate of a PMOS pass element, a pull-up resistor must be connected between the PMOS device’s gate and source for proper operation. PVCC (Pin 16, Driver Bias Voltage) This pin is the output of the internal series linear regulator. It also provides the bias for both bottom side and top side MOSFET drivers. The maximum voltage differential between PVCC and PGND is 6V. Its recommended operational voltage range is 2.9V to 5.6V. At minimum, a 10µF capacitor is required for decoupling PVCC to PGND. For proper operation the PVCC capacitor must be within 150 mils of the PVCC and the PGND pins and must be connected to these pins with dedicated traces. This pin provides the bootstrap bias for the top side driver. The absolute maximum voltage differential between BOOT and LX is 6.0V (including the voltage added due to the overcharging of the bootstrap capacitor); its operational voltage range is 2.5V to 5.6V with respect to LX. It is recommended that a 2.2 resistor be placed in series with the bootstrap diode to prevent over charging of the BOOT capacitor during normal operation. TSOC (Pin 22) The top side sourcing current limit is set by connecting this pin with a resistor and capacitor to the drain of the top side MOSEFT. A 100µA current source develops a voltage across the resistor which is then compared with the voltage developed across the top side MOSFET. An initial ~120ns blanking period is used to eliminate sampling error due to the switching noise before the current is measured. BSOC (Pin 23) The bottom side source and sinking current limit is set by placing a resistor (RBSOC) and capacitor between this pin and PGND. A 100µA current source develops a voltage across RBSOC which is then compared with the voltage developed across the bottom side MOSFET when on. The sinking current limit is set at 1x of the nominal sourcing limit in ISL8118. An initial ~120ns blanking period is used to eliminate the sampling error due to switching noise before the current is measured. FSET (Pin 24) This pin provides oscillator switching frequency adjustment by placing a resistor (RFSET) from this pin to GND. COMP (Pin 25) BGATE (Pin 17) This pin provides the drive for the bottom side MOSFET and should be connected to its gate. PGND (Pin 18, Power Ground) This pin connects to the bottom side MOSFET's source and provides the ground return path for the lower MOSFET driver and internal power circuitries. In addition, PGND is the return path for the bottom side MOSFET’s rDS(ON) current sensing circuit. LX (Pin 19) This pin connects to the source of the top side MOSFET and the drain of the bottom side MOSFET. This pin represents the return path for the top side gate driver. During normal switching, this pin is used for top side and bottom side current sensing. This pin is the error amplifier output. It should be connected to the FB pin through the desired compensation network. FB (Pin 26) This pin is the inverting input of the error amplifier and has a maximum usable voltage of VCC-1.8V. When using the internal differential remote sense functionality, this pin should be connected to VDIFF by a standard feedback network. In the event the remote sense buffer is disabled, the VDIFF pin should be connected to VOUT by a resistor divider along with FB’s compensation network. GND (Pin 27, Analog Ground) Signal ground for the IC. All voltage levels are measured with respect to this pin. This pin should not be left floating. VDIFF (Pin 28) This pin is the output of the differential remote sense instrumentation amplifier. It is connected internally to the Submit Document Feedback 10 FN6325.3 August 12, 2014 ISL8118 OV/UV/PGOOD comparators. The VDIFF pin should be connected to the FB pin by a standard feedback network. In the event that the remote sense buffer is disabled, the VDIFF pin should be connected to VOUT by a resistor divider along with FB’s compensation network. An RC filter should be used if VDIFF is to be connected directly to FB instead of to VOUT through a separate resistor divider network. GND (Bottom Side Pad, Analog Ground) Signal ground for the IC. All voltage levels are measured with respect to this pin. This pin should not be left floating. Functional Description The ISL8118 automatically initializes upon receipt of power without requiring any special sequencing of the input supplies. The Power-On Reset (POR) function continually monitors the input supply voltages (PVCC,VFF, VCC) and the voltage at the EN pin. Assuming the EN pin is pulled to above ~0.50V, the POR function initiates soft-start operation after all input supplies exceed their POR thresholds. HIGH = ABOVE POR; LOW = BELOW POR VCC POR AND SOFT-START PVCC POR EN POR FIGURE 1. SOFT-START INITIALIZATION LOGIC With all input supplies above their POR thresholds, driving the EN pin above 0.50V initiates a soft-start cycle. In addition to normal TTL logic, the enable pin can be used as a voltage monitor with programmable hysteresis through the use of the internal 10mA sink current and an external resistor divider. This feature is especially designed for applications that have input rails greater than a 3.3V and require specific input rail POR and Hysteresis levels for better undervoltage protection. Consider for a 12V application choosing RUP = 100k and RDOWN = 5.76k there by setting the rising threshold (VEN_RTH) to 10V and the falling threshold (VEN_FTH) to 9V, for 1V of hysteresis (VEN_HYS). Care should be taken to prevent the voltage at the EN pin from exceeding VCC when using the programmable UVLO functionality. Submit Document Feedback RUP VREF Sys_Enable RDOWN IEN_HYS = 10µA V EN_HYS R UP = -------------------------I EN_HYS R UP V EN_REF R DOWN = --------------------------------------------------------V EN_FTH – V EN_REF V EN_FTH = V EN_RTH – V EN_HYS Initialization VFF POR VIN 11 FIGURE 2. ENABLE POR CIRCUIT Soft-start The POR function activates the internal 38µA OTA which begins charging the external capacitor (CSS) on the SS pin to a target voltage of VCC. The ISL8118’s soft-start logic continues to charge the SS pin until the voltage on COMP exceeds the bottom of the oscillator ramp, at which point, the driver outputs are enabled, with the bottom side MOSFET first being held low for 200ns to provide for charging of the bootstrap capacitor. Once the driver outputs are enabled, the OTA’s target voltage is then changed to the margined (if margining is being used) reference voltage (VREF_MARG), and the SS pin is ramped up or down accordingly. This method reduces start-up surge currents due to a pre-charged output by inhibiting regulator switching until the control loop enters its linear region. By ramping the positive input of the error amplifier to VCC and then to VREF_MARG, it is even possible to mitigate surge currents from outputs that are pre-charged above the set output voltage. As the SS pin connects directly to the non-inverting input of the Error Amplifier, noise on this pin should be kept to a minimum through careful routing and part placement. To prevent noise injection into the error amplifier, the SS capacitor should be located within 150 mils of the SS and GND pins. Soft-start is declared done when the drivers have been enabled and the SS pin is within ±3mV of VREF_MARG. Power Good The power good comparator references the voltage on the soft-start pin to prevent accidental tripping during margining. The trip points are shown on Figure 3. Additionally, power good will not be asserted until after the completion of the soft-start cycle. A 0.1µF capacitor at the PGDLY pin will add an additional ~7.1ms delay to the assertion of power good. PGDLY does not delay the deassertion of power good. FN6325.3 August 12, 2014 ISL8118 parallel with RBSOC to prevent on chip parasitics from impacting the accuracy of the OCP measurement. VDIFF +15% +9% VREF_MARG -9% -15% OV UV FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW 1.5V T PGDLY = C PGDLY --------------30A Undervoltage and Overvoltage Protection The Undervoltage (UV) and Overvoltage (OV) protection circuitry compares the voltage on the VDIFF pin with the reference that tracks with the margining circuitry to prevent accidental tripping. UV and OV functionality is not enabled until the end of soft-start. An OV event is detected asynchronously and causes the top side MOSFET to turn off, the bottom side MOSFET to turn on (effectively a 0% duty cycle), and PGOOD to pull low. The regulator stays in this state and overrides sourcing and sinking OCP protections until the OV event is cleared. A UV event is detected asynchronously and results in the PGOOD pulling low. Overcurrent Protection The ISL8118 monitors both the top side MOSFET and bottom side MOSFET for overcurrent events. Dual sensing allows the ISL8118 to detect overcurrent faults at the very low and very high duty cycles that can result from the ISL8118’s wide input range. The OCP function is enabled with the drivers at start-up and detects the peak current during each sensing period. A resistor and a capacitor between the BSOC pin and GND set the bottom side source and sinking current limits. A 100µA current source develops a voltage across the resistor which is then compared with the voltage developed across the bottom side MOSFET at conduction mode. The measurement comparator uses offset correcting circuitry to provide precise current measurements with roughly ±2mV of offset error. An ~120ns blanking period, implemented on the upper and lower MOSFET current sensing circuitries, is used to reduce the current sampling error due to the leading-edge switching noise. An additional 120ns low pass filter is used to further reduce measurement error due to noise. In sourcing current applications, the BSOC voltage is inverted and compared with the voltage across the MOSFET while on. When this voltage exceeds the BSOC set voltage, a sourcing OCP fault is triggered. A 1000pF or greater filter capacitor should be used in Submit Document Feedback I OC_SOURCE r DS ON Botside R BSOC = -----------------------------------------------------------------------------------100A Detailed Bottom Side OCP Equations I I + ----- r OC_SOURCE 2 DS ON B R BSOC = ------------------------------------------------------------------------------------I BSOC N B GOOD GOOD UV Simple Bottom Side OCP Equation 12 V IN - V OUT V OUT I = -------------------------------- ---------------FS L V IN I BSOC N B R BSOC I I OC_SINK = ---------------------------------------------------------- – ----2 r DS ON B N B = Number of Bottom side MOSFETs The ISL8118’s sinking current limit is set to the same voltage as its sourcing limit. In sinking applications, when the voltage across the MOSFET is greater than the voltage developed across the resistor (RBSOC) a sinking OCP event is triggered. To avoid non-synchronous operation at light load, the peak-to-peak output inductor ripple current should not be greater than twice of the sinking current limit. The top side sourcing current limit is set by connecting the TSOC pin with a resistor (RTSOC) and a capacitor to the drain of the top side MOSEFT. A 100µA current source develops a voltage across the resistor which is then compared with the voltage developed across the top side MOSFET while on. When the voltage drop across the MOSFET exceeds the voltage drop across the resistor, a sourcing OCP event occurs. A 1000pF or greater filter capacitor should be used in parallel with RTSOC to prevent on chip parasitics from impacting the accuracy of the OCP measurement and to smooth the voltage across RTSOC in the presence of switching noise on the input bus. Sourcing OCP faults cause the regulator to disable (TGATE and BGATE drives pulled low, PGOOD pulled low, soft-start capacitor discharged) itself for a fixed period of time after which a normal soft-start sequence is initiated. The period of time the regulator waits before attempting a soft-start sequence is set by three charge and discharge cycles of the soft-start capacitor. Simple Top Side OCP Equation I OC_SOURCE r DS ON T R TSOC = -------------------------------------------------------------------100A Detailed Top Side OCP Equation I I + ----- r OC_SOURCE 2 DS ON T R TSOC = ------------------------------------------------------------------------------------I TSOC N T N T = Number of top side MOSFETs FN6325.3 August 12, 2014 ISL8118 Sinking OCP faults cause the bottom side MOSFET drive to be disabled, effectively operating the ISL8118 in a non-synchronous manner. The fault is maintained for three clock cycles at which point it is cleared and normal operation is restored. OVP fault implementation overrides sourcing and sinking OCP events, immediately turning on the bottom side MOSFET and turning off the top side MOSFET. The OC trip point varies mainly due to the MOSFETs rDS(ON) variations and system noise. To avoid overcurrent tripping in the normal operating load range, find the RTSOC and/or RBSOC resistor from the previous detailed equations with: 1. Maximum rDS(ON) at the highest junction temperature; 2. Minimum IBSOC and/or ITSOC from specification table; 3. Determine the overcurrent trip point greater than the maximum output continuous current at maximum inductor ripple current. Frequency Programming By tying a resistor to GND from FSET pin, the switching frequency can be set between 250kHz and 2MHz. Oscillator/VFF The Oscillator is a triangle waveform, providing for leading and falling edge modulation. The bottom of the oscillator waveform is set at 1.0V. The ramp's peak-to-peak amplitude is determined from the voltage on the VFF (Voltage Feed Forward) pin by Equation 1: D VOSC = 0.16 VFF (EQ. 1) An internal RC filter of 233k and 2pF (341kHz) provides filtering of the VFF voltage. An external RC filter may be required to augment this filter in the event that it is insufficient to prevent noise injection or control loop interactions. Voltages below 2.9V on the VFF pin may result in undesirable operation due to extremely small peak-to-peak oscillator waveforms. The oscillator waveform should not exceed VCC -1.0V. For high VFF voltages the internal/external 5.6V linear regulator should be used. 5.6V on VCC provides sufficient headroom for 100% duty cycle operation when using the maximum VFF voltage of 22V. In the event of sustained 100% duty cycle operation, defined as 32 clock cycles where no BG pulse is detected, BG will be pulsed on to refresh the design’s Bootstrap capacitor. 100 10 Fs Hz 1.178 10 RT – 0.973 (R T TO GND) (EQ. 2) Internal Series Linear Regulator The VIN pin is connected to PVCC with a 2 internal series linear regulator, which is internally compensated. The external Series Linear regulator option should be used for applications requiring pass elements of less than 2. When using the internal regulator, the EXDRV pin should be connected directly to GND. The PVCC and VIN pins should have a bypass capacitor (at least 10µF on PVCC is required) connected to PGND. For proper operation, the PVCC capacitor must be within 150 mils of the PVCC and the PGND pins, and be connected to these pins with dedicated traces. The internal series linear regulator’s input (VIN) can range between 3.3V to 20V ±10%. The internal linear regulator is to provide power for both the internal MOSFET drivers through the PVCC pin and the analog circuitry through the VCC pin. The VCC pin should be connected to the PVCC pin with an RC filter to prevent high frequency driver switching noise from entering the analog circuitry. When VIN drops below 5.6V, the pass element will saturate; PVCC will track VIN, minus the dropout of the linear regulator: PVCC = VIN-2xIVIN. When used with an external 5V supply, the VIN pin should be tied directly to PVCC. External Series Linear Regulator The EXDRV pin provides sinking drive capability for an external pass element linear regulator controller. The external linear options are especially useful when the internal linear dropout is too large for a given application. When using the external linear regulator option, the EXDRV pin should be connected to the gate of a PMOS device, and a resistor should be connected between its gate and source. A resistor and a capacitor should be connected from gate to source to compensate the control loop. A PNP device can be used instead of a PMOS device, in which case the EXDRV pin should be connected to the base of the PNP pass element. The maximum sinking capability of the EXDRV pin is 0.5mA, and should not be exceeded if using an external resistor for a PMOS device. The designer should take care in designing a stable system when using external pass elements. The VCC pin should be connected to the PVCC pin with an RC filter to prevent high frequency driver switching noise from entering the analog circuitry. RESISTANCE (k High Speed MOSFET Gate Driver 10 1 100k 1M FREQUENCY (Hz) 10M The integrated driver has similar drive capability and features to Intersil's ISL6605 stand alone gate driver. The PWM tri-state feature helps prevent a negative transient on the output voltage when the output is being shut down. This eliminates the Schottky diode that is used in some systems for protecting the microprocessor from reversed-output-voltage damage. See the ISL6605 datasheet for specification parameters that are not defined in the current ISL8118 Electrical Specifications table. FIGURE 4. RFS RESISTANCE vs FREQUENCY Submit Document Feedback 13 FN6325.3 August 12, 2014 ISL8118 A 1 to 2 resistor is recommended to be in series with the bootstrap diode when using VCCs above 5.0V to prevent the bootstrap capacitor from overcharging due to the negative swing of the trailing edge of the LX node. Margining Control When MARGIN is pulled high or low, the positive or negative margining functionality is respectively enabled. When MARGIN is left floating, the function is disabled. Upon positive margining, an internal buffer drives the OFSN pin from VCC to maintain OFSP at 0.591V. The resistor divider, RMARG and ROFSP, causes the voltage at OFSN to be increased. Similarly, upon Negative margining, an internal buffer drives the OFSP pin from VCC to maintain OFSN at 0.591V. The resistor divider, RMARG and ROFSN, causes the voltage at OFSP to be increased. In both modes, the voltage difference between OFSP and OFSN is then sensed with an instrumentation amplifier and is converted to the desired margining voltage by a 5:1 ratio. The maximum designed margining range of the ISL8118 is ±200mV; this sets the MINIMUM value of ROFSP or ROFSN at approximately 5.9k for an RMARG of 10k for a MAXIMUM of 1V across RMARG. The OFS pins are completely independent and can be set to different margining levels. The maximum usable reference voltage for the ISL8118 is VCC - 1.8V, and should not be exceeded when using the margining functionality, i.e, VREF_MARG < VCC - 1.8V. V REF R MARG V MARG_POS = --------------- --------------------5 R OFSP (EQ. 3) V REF R MARG V MARG_NEG = --------------- --------------------5 R OFSN (EQ. 4) An alternative calculation provides for a desired percentage change in the output voltage when using the internal 0.591V reference: R MARG V PCT_POS = 20 --------------------R OFSP (EQ. 5) R MARG V PCT_NEG = 20 --------------------R OFSN (EQ. 6) When not used in a design OFSP, OFSN, and MARGIN should be left floating. To prevent damage to the part, OFSP and OFSN should not be tied to VCC or PVCC. Reference Output Buffer The internal buffer’s output tracks the unmargined system reference. It has a 19mA drive capability, with maximum and minimum output voltage capabilities of VCC and GND respectively. Its capacitive loading can range from 1µF to above 17.6µF, which is designed for 1 to 8 DIMM systems in DDR (Dual Data Rate) applications. 1µF of capacitance should always be present on REFOUT. It is not designed to drive a resistive load and any such load added to the system should be kept above 300ktotal impedance. Submit Document Feedback 14 Reference Input The REFIN pin allows the user to bypass the internal 0.591V reference with an external reference. Asynchronously, if REFIN is NOT within ~800mV of VCC, the external reference pin is used as the control reference instead of the internal 0.591V reference. The minimum usable REFIN voltage is ~60mV while the maximum is VCC - 1.8V - VMARG (if present). The limitation is set by the error amplifier's maximum common mode input range of VCC - 1.8V for the industrial temperature ranges. VCC REFERENCE VREF = 0.591V ISL8118 STATE MACHINE REFIN 800mV REFOUT MARGINING BLOCK VREF_MARG OTA FIGURE 5. SIMPLIFIED REFERENCE BUFFER Internal Reference and System Accuracy The internal reference is trimmed to 0.591V. The total DC system accuracy of the system is within 0.85% over commercial temperature range, and 1.25% over industrial temperature range. System accuracy includes error amplifier offset, OTA error, and bandgap error. Differential remote sense offset error is not included. As a result, if the differential remote sense is used, then an extra 3mV of offset error enters the system. The use of REFIN may add up to 1.8mV of additional offset error. Differential Remote Sense Buffer The differential remote sense buffer is essentially an instrumentation amplifier with unity gain. The offset is trimmed to 3mV for high system accuracy. As with any instrumentation amplifier, typically 6µA are sourced from the VSENSN pin. The output of the remote sense buffer is connected directly to the internal OV/UV comparator. As a result, a resistor divider should be placed on the input of the buffer for proper regulation, as shown in Figure 6. The VDIFF pin should be connected to the FB pin by a standard feed-back network. A small capacitor, CSEN in Figure 6, can be added to filter out noise, typically CSEN is chosen so the corresponding time constant does not reduce the overall phase margin of the design, typically this is 2x to 10x switching frequency of the regulator. As some applications will not use the differential remote sense, the output of the remote sense buffer can be disabled (high impedance) by pulling VSENSN within 800mV of VCC. FN6325.3 August 12, 2014 ISL8118 VSENSE(REMOTE) VOUT (LOCAL) 10 GND (LOCAL) 10 VSENSE+ (REMOTE) RFB ROS CSEN VCC VSENSN ZIN VSENSP ZFB VDIFF OV/UV COMP 800mV COMP FB ERROR AMP GAIN = 1 VSS FIGURE 6. SIMPLIFIED UNITY GAIN DIFFERENITAL SENSING IMPLEMENTATION VIN ISL8118 TGATE Q1 LO VOUT LX CIN Q2 BGATE LOAD As the VDIFF pin is connected internally to the OV/UV/PGOOD comparator, an external resistor divider must then be connected to VDIFF to provide correct voltage information for the OV/UV comparator. An RC filter should be used if VDIFF is to be connected directly to FB instead of to VOUT through a separate resistor divider network. This filter prevents noise injection from disturbing the OV/UV/PGOOD comparators on VDIFF. VDIFF may also be connected to the SS pin, which completely bypasses the OV/UV/PGOOD functionality. CO PGND Application Guidelines Layout Considerations RETURN Figure 7 shows the critical power components of the converter. To minimize the voltage overshoot/undershoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 8 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the ISL8118 within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL8118 must be sized to handle up to 4A peak current. FIGURE 7. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS Proper grounding of the IC is important for correct operation in noisy environments. The PGND pin should be connected to board ground at the source of the bottom side MOSFET with a wide short trace. The GND pin should be connected to a large copper fill under the IC which is subsequently connected to board ground at a quite location on the board, typically found at an input or output bulk (electrolytic) capacitor. BOOT +VIN D1 CBOOT SS ISL8118 PVCC GND VOUT LX +5V CSS Q1 L O Q2 LOAD As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. CO CPVCC PGND FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES Submit Document Feedback 15 FN6325.3 August 12, 2014 ISL8118 Figure 8 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS pin and locate the capacitor, CSS close to the SS pin (as described earlier) as the internal current source is only 38µA. Provide local decoupling between PVCC and PGND pins as described earlier. Locate the capacitor, CBOOT as close as practical to the BOOT and LX pins. C2 COMP R2 C3 R3 C1 - R1 FB E/A + VREF Compensating the Converter VDIFF The ISL8118 single-phase converter is a voltage-mode controller. This section highlights the design considerations for a voltage-mode controller requiring external compensation. To address a broad range of applications, a type-3 feedback network is recommended (see Figure 9). - RFB VSENSN CSEN ROS + VSENSP VOUT OSCILLATOR C2 VIN R2 C1 FB C3 R3 PWM CIRCUIT COMP VOSC R1 TGATE ISL8118 HALF-BRIDGE DRIVE VDIFF L DCR LX C ESR BGATE FIGURE 9. COMPENSATION CONFIGURATION FOR ISL8118 WHEN USING DIFFERENTIAL REMOTE SENSE Figure 10 highlights the voltage-mode control loop for a synchronous-rectified buck converter, when using an internal differential remote sense amplifier. The output voltage (VOUT) is regulated to the reference voltage, VREF, level. The error amplifier output (COMP pin voltage) is compared with the oscillator (OSC) triangle wave to provide a pulse-width modulated wave with an amplitude of VIN at the LX node. The PWM wave is smoothed by the output filter (L and C). The output filter capacitor bank’s equivalent series resistance is represented by the series resistor ESR. The modulator transfer function is the small-signal transfer function of VOUT /VCOMP. This function is dominated by a DC gain, given by dMAXVIN /VOSC, and shaped by the output filter, with a double pole break frequency at FLC and a zero at FCE . For the purpose of this analysis C and ESR represent the total output capacitance and its equivalent series resistance. 1 F LC = --------------------------2 L C (EQ. 7) 1 F CE = --------------------------------2 C ESR (EQ. 8) ISL8118 FIGURE 10. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN The compensation network consists of the error amplifier (internal to the ISL8118) and the external R1-R3, C1-C3 components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F0; typically 0.1 to 0.3 of FSW) and adequate phase margin (better than 45°). Phase margin is the difference between the closed loop phase at F0dB and 180°. The equations that follow relate the compensation network’s poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figures 9 and 10. Use the following guidelines for locating the poles and zeros of the compensation network: 1. Select a value for R1 (1k to 10k, typically). Calculate value for R2 for desired converter bandwidth (F0). If setting the output voltage to be equal to the reference set voltage as shown in Figure 9, the design procedure can be followed as presented. However, when setting the output voltage via a resistor divider placed at the input of the differential amplifier (as shown in Figure 10), in order to compensate for the attenuation introduced by the resistor divider, the below obtained R2 value needs be multiplied by a factor of (ROS + RFB)/ROS. The remainder of the calculations remain unchanged, as long as the compensated R2 value is used. V OSC R 1 F 0 R 2 = --------------------------------------------d MAX V IN F LC Submit Document Feedback 16 EXTERNAL CIRCUIT (EQ. 9) FN6325.3 August 12, 2014 ISL8118 A small capacitor, CSEN in Figure 10, can be added to filter out noise, typically CSEN is chosen so the corresponding time constant does not reduce the overall phase margin of the design, typically this is 2x to 10x switching frequency of the regulator. As the ISL8118 supports 100% duty cycle, dMAX equals 1. The ISL8118 also uses feed-forward compensation, as such VOSC is equal to 0.16 multiplied by the voltage at the VFF pin. When tying VFF to VIN, Equation 9 simplifies to: 0.16 R 1 F 0 R 2 = ---------------------------------F LC (EQ. 10) 2. Calculate C1 such that FZ1 is placed at a fraction of the FLC, at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to desired number). The higher the quality factor of the output filter and/or the higher the ratio FCE/FLC, the lower the FZ1 frequency (to maximize phase boost at FLC). 1 C 1 = ----------------------------------------------2 R 2 0.5 F LC (EQ. 11) 3. Calculate C2 such that FP1 is placed at FCE. C1 C 2 = -------------------------------------------------------2 R 2 C 1 F CE – 1 (EQ. 12) 4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such that FP2 is placed below FSW (typically, 0.5 to 1.0 times FSW). FSW represents the regulator’s switching frequency. Change the numerical factor to reflect desired placement of this pole. Placement of FP2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the HF ripple component at the COMP pin and minimizing resultant duty cycle jitter. COMPENSATION BREAK FREQUENCY EQUATIONS 1 F Z1 = ------------------------------2 R 2 C 1 (EQ. 19) 1 F Z2 = ------------------------------------------------2 R 1 + R 3 C 3 (EQ. 20) 1 F P2 = ------------------------------2 R 3 C 3 (EQ. 22) 1 F P1 = --------------------------------------------C1 C2 2 R 2 --------------------C1 + C2 (EQ. 21) Figure 11 shows an asymptotic plot of the DC/DC converter’s gain vs. frequency. The actual modulator gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown. Using the above guidelines should yield a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 against the capabilities of the error amplifier. The closed loop gain, GCL, is constructed on the loglog graph of Figure 11 by adding the modulator gain, GMOD (in dB), to the feedback compensation gain, GFB (in dB). This is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain. (EQ. 14) It is recommended that a mathematical model is used to plot the loop response. Check the loop gain against the error amplifier’s open-loop gain. Verify phase margin results and adjust as necessary. The following equations describe the frequency response of the modulator (GMOD), feedback compensation (GFB) and closed-loop response (GCL): d MAX V IN 1 + s f ESR C G MOD f = ------------------------------ ----------------------------------------------------------------------------------------------------------2 V OSC 1 + s f ESR + DCR C + s f L C (EQ. 15) 1 + s f R2 C1 G FB f = ---------------------------------------------------- s f R1 C1 + C2 (EQ. 16) 1 + s f R1 + R3 C3 ----------------------------------------------------------------------------------------------------------------------- C1 C2 ------------------- 1 + s f R3 C3 1 + s f R2 C 1 + C 2 where s f = 2 f j 17 (EQ. 17) FP1 FP2 GAIN 1 C 3 = ------------------------------------------------2 R 3 0.7 F SW (EQ. 18) R2 20 log -------- R1 MODULATOR GAIN COMPENSATION GAIN CLOSED LOOP GAIN OPEN LOOP E/A GAIN d MAX V IN 20 log --------------------------------V OSC 0 GFB GCL LOG (EQ. 13) Submit Document Feedback 1 V IN d MAX V IN ------------------------------ = -------------------------- = 6.25 V OSC 0.16 V IN FZ1 FZ2 R1 R 3 = ---------------------F SW ------------ – 1 F LC G CL f = G MOD f G FB f As before, when tying VFF to VIN, terms in the previous equations can be simplified as follows: GMOD LOG FLC FCE F0 FREQUENCY FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN A stable control loop has a gain crossing with close to a -20dB/decade slope and a phase margin greater than 45°. Include worst case component variations when determining phase margin. The mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. When designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the switching frequency, FSW. FN6325.3 August 12, 2014 ISL8118 Component Selection Guidelines Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. For example, Intel recommends that the high frequency decoupling for the Pentium Pro be composed of at least forty (40) 1.0µF ceramic capacitors in the 1206 surface-mount package. Follow on specifications have only increased the number and quality of required ceramic decoupling capacitors. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: V IN - V OUT V OUT I = -------------------------------- ---------------FS x L V IN The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: L O I TRAN t RISE = -------------------------------V IN – V OUT (EQ. 25) L O I TRAN t FALL = ------------------------------V OUT (EQ. 26) where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a lower input source such as 1.8V or 3.3V, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement (EQ. 23) (EQ. 24) VOUT= I x ESR Submit Document Feedback One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL8118 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. 18 FN6325.3 August 12, 2014 ISL8118 components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the top and the bottom MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the following equations). The upper MOSFET exhibits turn-on and turn-off switching losses as well as the reverse recover loss, while the synchronous rectifier exhibits body-diode conduction losses during the leading and trailing edge dead times. 0.6 0.5Io 0.5 KICM 0.4 0.25Io 0.3 DI = 0Io 0.2 DS ON B I 2 r------------------------- 1 – D + P DEAD P BOTTOM = I O 2 + ------ N 12 0.1 B 0.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY CYCLE (D) 0.8 0.9 1.0 FIGURE 12. INPUT-CAPACITOR CURRENT MULTIPLIER FOR SINGLE-PHASE BUCK CONVERTER for the input capacitor of a buck regulator is approximated in the following. I IN RMS = DS ON ,T I 2 r--------------------------P TOP = I O 2 + ------ D + P SW + P Qrr N 12 (EQ. 30) T I I t P SW = I O + ----+ I – ------ t VIN F S (EQ. 31) 12 OFF O 12 ON VO D = ---------VIN I2 2 D – D2 + -------- D IO 12 (EQ. 28) I I V ------ P DEAD = I O + ----DT t DT + I O – 12 V DB t DB F S 12 (EQ. 29) (EQ. 27) OR I IN RMS = K ICM I O For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MVGX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. MOSFET Selection/Considerations The ISL8118 requires 2 N-Channel power MOSFETs. These should be selected based upon rDS(ON), gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss P Qrr = Q rr VIN F S (EQ. 32) where D is the duty cycle = VO / VIN; Qrr is the reverse recover charge; tDLand tDT are leading and trailing edge dead time, and tON & tOFF are the switching intervals. These equations do not include the gate-charge losses that are proportional to the total gate charge and the switching frequency and partially dissipated by the internal gate resistance of the MOSFETs. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. ISL8118 DC/DC Converter Application Circuit Detailed information on the application circuit, including a complete Bill of Materials and circuit board description, can be found in application note AN1204. See Intersil’s home page on the web: http://www.intersil.com. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 19 FN6325.3 August 12, 2014 ISL8118 Package Outline Drawing L28.5x5 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/07 4X 3.0 5.00 24X 0.50 A B 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 28 22 1 5.00 21 3 .10 ± 0 . 15 15 (4X) 7 0.15 8 14 TOP VIEW 0.10 M C A B - 0.07 4 28X 0.25 + 0.05 28X 0.55 ± 0.10 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0.1 C BASE PLANE SEATING PLANE 0.08 C ( 4. 65 TYP ) ( 24X 0 . 50) ( SIDE VIEW 3. 10) (28X 0 . 25 ) C 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. ( 28X 0 . 75) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. Submit Document Feedback 20 FN6325.3 August 12, 2014