FEATURES FUNCTIONAL BLOCK DIAGRAM VBAT OFSN VREF OFFSET NULL AD8338 VGA CORE INPR + INMR – OUTP + OUTPUT STAGE 0dB – OUTM 0dB TO 80dB VREF INPD Front end for inductive telemetry systems Ultrasonic signal receivers Signal compression for driving an ADC AGC amplifiers COMM MODE GAIN FBKM AUTOMATIC GAIN CONTROL GAIN INTERFACE INMD APPLICATIONS DETO VAGC Figure 1. 100 GENERAL DESCRIPTION 80 The basic gain function is linear-in-dB and is controlled by the voltage applied to Pin GAIN. The nominal gain range spans from 0 dB to 80 dB for control voltages between 0.1 V to 1.1 V with a slope of 12.5 mV/dB. The nominal gain range can be shifted up or down via direct access to Pin INPD and Pin INMD, the current inputs of the VGA. For example, driving the INPD and INMD pins with 50 Ω resistors shifts the gain range up by 20 dB, that is, 20 dB to 100 dB, and lowers the input referred noise of the device to 1.5 nV/√Hz. Additionally, the gain slope can be inverted via logic Pin MODE. The AD8338 includes additional circuit blocks to enable input offset correction and automatic gain control (AGC). DC offset voltages are removed by the offset correction circuit, which behaves like a high-pass filter whose corner is set with an external capacitor. The AGC function varies the gain of the AD8338 to maintain a constant RMS output voltage. An externally applied voltage to Pin VAGC with respect to the voltage at Pin VREF sets the output RMS amplitude. A capacitor from Pin DETO to ground sets the response time of the AGC circuit. VGAIN = 1.1V VGAIN = 1.0V VGAIN = 0.9V 60 VGAIN = 0.8V VGAIN = 0.7V GAIN (dB) The AD8338 is a variable gain amplifier (VGA) for applications that require a fully differential signal path, low power, low noise, and a well-defined gain over frequency. While the inputs are differential, the device can also be driven with a single-ended source if required. Rev. A FBKP 11279-001 Voltage controlled gain range of 0 dB to 80 dB 3 mA supply current at gain of 40 dB Low frequency (LF) to 18 MHz operation Supply range: 3.0 V to 5.0 V Low noise: 4.5 nV/√Hz at 80 dB gain Fully differential signal path Offset correction (offset null) feature Internal 1.5 V reference 16-lead LFCSP Automatic gain control feature Wide gain range for high dynamic range signals 40 VGAIN = 0.6V VGAIN = 0.5V VGAIN = 0.4V 20 0 VGAIN = 0.3V VGAIN = 0.2V VGAIN = 0.1V –20 –40 10k 100k 1M 10M FREQUENCY (Hz) 100M 11279-005 Data Sheet Low Power, 18 MHz Variable Gain Amplifier AD8338 Figure 2. Gain vs. Frequency The AD8338 offers additional versatility by providing access to the internal summing nodes of the VGA core and the output amplifiers. With the addition of a few external passive components, users can customize the gain, bandwidth, input impedance, and noise profile of the part to fit their application. The AD8338 uses a single supply voltage of 3.0 V to 5.0 V and is very power efficient, consuming as little as 3 mA quiescent current at mid gain. The AD8338 is available in a 3 mm × 3 mm, RoHS compliant, 16-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8338 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................6 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 12 General Description ........................................................................... 1 Introduction ................................................................................ 12 Functional Block Diagram .............................................................. 1 Explanation of the Gain Function............................................ 16 Revision History ............................................................................... 2 Adjusting The Output Common Mode .................................. 17 Specifications..................................................................................... 3 Applications Information .............................................................. 18 AC Specifications.......................................................................... 3 Simple On-Off Keyed (OOK) Receiver ................................... 18 Absolute Maximum Ratings ............................................................ 4 Interfacing the AD8338 to an ADC ......................................... 19 Thermal Resistance ...................................................................... 4 Outline Dimensions ....................................................................... 20 ESD Caution .................................................................................. 4 Ordering Guide .......................................................................... 20 Pin Configuration and Function Descriptions ............................. 5 REVISION HISTORY 11/13—Rev. 0 to Rev. A Changes to Features Section, Applications Section, and General Descriptions Section ........................................................................ 1 Changes to Table 1 ............................................................................ 3 Changes to Pin 13 and Pin 14 Descriptions .................................. 5 Added Conditions to Typical Performance Characteristics; Changes to Figure 4 and Figure 5; Changes to Figure 6, Figure 7, Figure 8 Captions .............................................................................. 6 Changes to Figure 12 and Figure 13............................................... 7 Changes to Figure 18 and Figure 19............................................... 8 Changes to Figure 22 ........................................................................ 9 Changes to Figure 35 and Figure 36............................................. 11 Replaced Theory of Operation Section ....................................... 12 Changes to Figure 50 ...................................................................... 18 Changes to Ordering Guide .......................................................... 20 4/13—Revision 0: Initial Version Rev. A | Page 2 of 20 Data Sheet AD8338 SPECIFICATIONS AC SPECIFICATIONS VBAT = 3.0 V, TA = 25°C, CL = 2 pF on OUTP and OUTM, RL = ∞, MODE pin high, RIN = 2 × 500 Ω, VGAIN = 0.6 V, differential operation, unless otherwise noted. Table 1. Parameter INPUT INTERFACE Input Voltage Range −3 dB Bandwidth Input Resistance Input Capacitance OUTPUT INTERFACE Small Signal Bandwidth Peak Slew Rate Peak-to-Peak Output Swing Common-Mode Voltage Input-Referred Voltage Noise Using Internal Resistors Using External 47 Ω Resistors Offset Voltage POWER SUPPLY VBAT IVBAT GAIN CONTROL Gain Range Gain Span Gain Voltage Gain Slope Gain Accuracy VREF REFERENCE OUTPUT Output Voltage Output Current Accuracy DETO OUTPUT CURRENT MODE INPUT Logic High Logic Low AGC CONTROL Maximum Target Amplitude Test Conditions/Comments INPD, INMD, INPR, INMR pins Standard configuration using the INPR and INMR inputs Min Typ 0.8 3 18 1 OUTP and OUTM pins VGAIN = 0.6 V VGAIN = 0.6 V Differential output VGAIN = 1.1 V VGAIN = 0.6 V VGAIN = 0.1 V VGAIN = 1.1 V RTO, VGAIN = 0.1 V, offset null enabled RTO, VGAIN = 0.6 V, offset null enabled RTO, VGAIN = 0.1 V, offset null disabled RTO, VGAIN = 0.6 V, offset null disabled 18 50 2.8 1.5 MHz V/µs V p-p V 4.5 15 150 1.5 +10 +10 +50 +200 nV/√Hz nV/√Hz nV/√Hz nV/√Hz mV mV mV mV 5.0 8.0 3.8 6.0 V mA mA mA 80 dB 1.1 83 13 +2 dB V dB/V mV/dB dB 6.0 3.0 4.5 0 VGAIN relative to COMM 0.1 77 12 −2 1.2 V p-p MHz kΩ pF 3.0 Standard configuration using the INPR and INMR inputs Unit 2 −10 −10 −50 −200 Min gain, VGAIN = 0.1 V Mid gain, VGAIN = 0.6 V Max gain, VGAIN = 1.1 V Max 80 Standard configuration using the INPR and INMR inputs; 0.1 V < VGAIN < 1.1 V 80 12.5 +0.5 1.5 5 2 ±10 2.5 COMM MODE = 0 V Expected rms output value for target = VAGC − VREF = 1.0 V Rev. A | Page 3 of 20 V mA % µA VBAT 0.6 1.0 V V V rms AD8338 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter VBAT to COMM INPR, INPD, INMD, INMR, MODE, GAIN, FBKM, FBKP, OUTM, OUTP, VAGC, VREF, OFSN Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Rating −0.3 V to +5.5 V COMM to VBAT Table 3. Thermal Resistance −40°C to +85°C −65°C to +150°C 150°C 300°C ESD CAUTION Package Type 16-Lead LFCSP Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 4 of 20 θJA 48.75 Unit °C/W Data Sheet AD8338 14 OFSN 13 VAGC 16 VREF 15 VBAT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 12 FBKP INPR 1 INPD 2 AD8338 11 OUTP INMD 3 TOP VIEW (Not to Scale) 10 OUTM INMR 4 NOTES 1. THE EXPOSED PAD SHOULD BE TIED TO A QUIET ANALOG GROUND. 11279-002 GAIN 7 FBKM DETO 8 MODE 6 COMM 5 9 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 0 1 2 3 4 5 6 Mnemonic EPAD INPR INPD INMD INMR COMM MODE 7 8 9 10 11 12 13 GAIN DETO FBKM OUTM OUTP FBKP VAGC 14 OFSN 15 16 VBAT VREF Description Exposed Pad. The exposed pad should be tied to a quiet analog ground. Positive 500 Ω Resistor Input for Voltage Input Applications. Positive Input for Current Input Applications. Negative Input for Current Input Applications. Negative 500 Ω Resistor Input for Voltage Input Applications. Ground. Gain Mode. This pin selects positive or negative gain slope for gain control. When this pin is tied to VBAT, the gain of the AD8338 increases proportionally with an increase of the voltage on the GAIN pin. When this pin is tied to COMM, the gain decreases with an increase of the voltage on the GAIN pin. Gain Control Input, 12.5 mV/dB or 80 dB/V. Detector Output Terminal, ±10 µA. If the AGC feature is not used, tie DETO to COMM. Negative Feedback Node. For more information, see the FBKP, FBKM, OUTP, and OUTM Pins section. Negative Output. Positive Output. Positive Feedback Node. For more information, see the FBKP, FBKM, OUTP, and OUTM Pins section. Voltage for Automatic Gain Control Circuit. This pin controls the target rms output voltage for the AGC circuit. For more information, see the AGC Circuit, VAGC Pin section. If the AGC feature is not used, tie VAGC to VREF. Offset Null Terminal. For more information, see the Offset Correction Circuit, OFSN Pin section. If the offset null feature is not used, tie OFSN to ground; otherwise, a capacitor to VREF is used to set the offset null high-pass corner. Positive Supply Voltage. Internal 1.5 V Voltage Reference. Rev. A | Page 5 of 20 AD8338 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VBAT = 3.0 V, TA = 25°C, CL = 2 pF on OUTP and OUTM, RL = ∞, MODE pin high, RIN = 2 × 500 Ω, VGAIN = 0.6 V, differential operation; unless otherwise noted. 80 80 70 MODE PIN LOW 60 MODE PIN HIGH 60 40 GAIN (dB) GAIN (dB) 50 40 VGAIN = 600mV VGAIN = 350mV VGAIN = 100mV 20 0 30 –20 20 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VGAIN (V) –60 100k 11279-003 0 0.1 100M Figure 7. Gain vs. Frequency, RIN = 50 Ω, 20 dB Steps 80 N = 962 60 60 40 50 20 GAIN (dB) 70 40 0 30 –20 20 –40 10 –60 78.3 78.6 78.9 79.2 79.5 79.8 80.1 80.4 GAIN SLOPE (dB/V) 100M VS = 3V f = 1MHz VGAIN = 1.0V 3 GAIN ERROR (dB) VGAIN = 0.8V VGAIN = 0.6V VGAIN = 0.5V VGAIN = 0.3V VGAIN = 0.2V VGAIN = 0.1V 2 1 –40°C 0 +25°C –1 –2 –3 +85°C –20 +105°C 100k 1M 10M FREQUENCY (Hz) 100M 11279-106 –4 –40 10k 10M 4 VGAIN = 1.1V VGAIN = 0.4V 0 1M 5 VGAIN = 0.7V 20 VGAIN = 100mV Figure 8. Gain vs. Frequency, RIN = 5 kΩ, 20 dB Steps VGAIN = 0.9V 40 VGAIN = 350mV FREQUENCY (Hz) 100 60 VGAIN = 600mV –80 100k Figure 5. Gain Slope Histogram 80 VGAIN = 850mV Figure 6. Gain vs. Frequency, 8 dB Steps –5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VGAIN (V) Figure 9. Gain Error vs. VGAIN over Temperature Rev. A | Page 6 of 20 1.1 11279-006 78.0 11279-105 0 VGAIN = 1100mV 11279-107 80 NUMBER OF HITS 10M FREQUENCY (Hz) Figure 4. Gain vs. VGAIN GAIN (dB) 1M 11279-109 –40 10 Data Sheet AD8338 1.0 5 0.5 4 3 OFFSET VOLTAGE (mV) REFERRED TO OUTPUT –1.0 –1.5 10kHz 100kHz 1MHz 2MHz 4MHz 8MHz 10MHz 12MHz 14MHz –2.0 –2.5 –3.0 –3.5 0.1 0.2 2 1 0 –1 –2 –3 –4 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VGAIN (V) –5 0.1 –40°C +25°C +85°C +105°C 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 11279-012 –0.5 11279-007 GAIN ERROR (dB) 0 1.1 VGAIN (V) Figure 13. Differential Offset Voltage vs. VGAIN, Offset Null On Figure 10. Gain Error vs. VGAIN over Frequency 350 30 300 25 250 IMPEDANCE (Ω) DELAY (ns) 20 15 10 DIFFERENTIAL 200 150 100 5 50 10M 100M FREQUENCY (Hz) 11279-110 1M 0 100k 100M Figure 14. Output Impedance vs. Frequency 20 OFFSET NULL ENABLED RELATIVE TO OUTPUT VGAIN = 0.6V N = 962 0 BALANCE ERROR (dB) 50 40 30 20 10 –20 –40 GAIN = 1000 GAIN = 100 GAIN = 10 –60 GAIN = 1 –80 0 –3 –2 –1 0 1 DIFFERENTIAL OFFSET VOLTAGE (mV) 2 –120 100k 1M 10M FREQUENCY (Hz) Figure 15. Output Balance Error vs. Frequency Figure 12. Differential Offset Voltage Histogram Rev. A | Page 7 of 20 100M 11279-015 –100 11279-111 NUMBER OF HITS 10M FREQUENCY (Hz) Figure 11. Group Delay vs. Frequency 60 1M 11279-112 SINGLE-ENDED 0 100k AD8338 Data Sheet 0 1k –10 GAIN = 1, OFSN DISABLED –20 100 GAIN = 10, OFSN DISABLED NOISE (nV/ Hz) CMRR (dB) –30 –40 –50 –60 GAIN = 100, OFSN DISABLED 10 GAIN = 1000, OFSN ENABLED GAIN = 10000, OFSN ENABLED –70 0dB 20dB 40dB 60dB 80dB –100 10k 100k 1M 10M 0.1 10k FREQUENCY (Hz) 1M 10M 100M FREQUENCY (Hz) Figure 16. CMRR vs. Frequency over Gain, Offset Null On, Referred to Input Figure 19. Input Referred Noise vs. Frequency 100k 0 HD2, HD3, HD2, HD3, HARMONIC DISTORTION (dBc) –10 +85°C NOISE (nV/ Hz) 100k 11279-117 –90 1 11279-115 –80 10k +25°C 1k –40°C –20 1kΩ 1kΩ 10kΩ 10kΩ VOUT = 0.5V p-p –30 –40 –50 –60 –70 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 VGAIN (V) –90 50k 11279-017 100 500k 11279-118 –80 5M FREQUENCY (Hz) Figure 20. Harmonic Distortion vs. Frequency Figure 17. Output Referred Noise vs. VGAIN 0 1k HARMONIC DISTORTION (dBc) 100 +85°C 10 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 –30 –40 HD3 –50 HD2 –60 –70 –40°C 0 –20 0.9 1.0 VGAIN (V) 1.1 1.2 –80 0.5 1.0 1.5 2.0 2.5 VOUT (V p-p) Figure 21. Harmonic Distortion vs. Output Amplitude Figure 18. Input Referred Noise vs. VGAIN Rev. A | Page 8 of 20 3.0 11279-120 +25°C 11279-119 NOISE (nV/ Hz) –10 Data Sheet AD8338 0 0 –10 –10 –20 –20 IMD3 DISTORTION (dBc) –30 –40 HD3, MODE PIN LOW –50 HD3, MODE PIN HIGH HD2, MODE PIN LOW –60 –30 –40 –50 –60 HD2, MODE PIN HIGH 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VGAIN (V) –80 20k 11279-123 –80 0.1 2M 20M FREQUENCY (Hz) Figure 25. IMD3 Distortion vs. Frequency Figure 22. Harmonic Distortion vs. VGAIN 2.0 20 VOUT = 2V p-p f = 1MHz GAIN = 0dB OUTPUT 10 1.5 0 1.0 –10 0.5 VOUT (V) P1dB COMPRESSION (dBm) 200k 11279-124 –70 –70 –20 –30 0 –0.5 –40 INPUT –1.0 –50 –1.5 –60 0.3 0.5 0.7 0.9 1.1 VGAIN (V) –2.0 11279-122 –70 0.1 0 100 200 300 400 500 600 700 800 TIME (ns) 11279-027 HARMONIC DISTORTION (dBc) VOUT = 0.5V p-p Figure 26. Large Signal Pulse Response vs. Time, VGAIN = 0 V Figure 23. Input and Output 1 dB Compression vs. VGAIN 2.0 25 VOUT = 2V p-p f = 1MHz GAIN = 80dB 1.5 20 1.0 0.5 VOUT (V) 15 10 0 –0.5 1MHz –1.0 5 0 0.1 0.3 0.5 0.7 VGAIN (V) 0.9 1.1 –2.0 0 0.2 0.4 0.6 0.8 TIME (µs) Figure 27. Large Signal Pulse Response vs. Time, VGAIN = 1.0 V Figure 24. OIP3 vs. VGAIN Rev. A | Page 9 of 20 11279-028 –1.5 11279-125 OIP3 (dBm) 100kHz AD8338 Data Sheet 1.5 2.0 f = 100kHz VIN LOW = 2mV VIN HIGH = 20mV 1.0 GAIN = 40dB VOUT = 2V p-p f = 1MHz GAIN = 40dB 1.5 OUTPUT VOLTAGE (V) 1.0 VOUT (V) 0.5 0 –0.5 0.5 0 –0.5 –1.0 –1.0 0 0.2 0.4 0.6 0.8 TIME (µs) –1.5 11279-030 –2.0 0 20 60 100 120 140 160 180 200 12 –40°C, MODE PIN HIGH +25°C, MODE PIN HIGH +85°C, MODE PIN HIGH –40°C, MODE PIN LOW +25°C, MODE PIN LOW +85°C, MODE PIN LOW 10 40 8 20 IDD (mA) 0 –20 6 4 –40 –60 2 VOUT = 100mV p-p f = 1.5MHz GAIN = 1 –100 0 0.2 0.4 0.6 0.8 TIME (µs) 0 11279-031 –80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 VGAIN (V) Figure 29. Small Signal Pulse Response vs. Time (Varying Capacitive Loads) 11279-131 VOUT (mV) 80 Figure 31. Overdrive Recovery vs. Time CL = 0pF CL = 10pF CL = 20pF CL = 47pF 80 60 TIME (µs) Figure 28. Large Signal Pulse Response vs. Time, VGAIN = 0.6 V 100 40 11279-018 –1.5 Figure 32. Supply Current vs. VGAIN 50 OFFSET NULL OFF 40 VGAIN 0.6 30 10µF GAIN (dB) 0.1 VOUT 1.0 0.1µF 10 0.01µF 0 –10 0 –20 –1.0 –30 1 2 3 4 5 6 7 8 TIME (µs) 9 10 Figure 30. Gain Step Response vs. Time –40 20 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 33. Offset Null Bandwidth vs. Offset Null Capacitor Rev. A | Page 10 of 20 11279-134 GAIN = 100 0 11279-127 GAIN STEP (V) 1µF 20 Data Sheet AD8338 3.0 OUTPUT COMMON-MODE VOLTAGE (V) –10 –20 PSRR (dB) –30 –40 –50 –60 –70 –80 1k 10k 100k 1M 10M FREQUENCY (Hz) 2.0 1.5 VS = 3V 1.0 VS = 5V 0.5 0 20k 11279-133 –90 –100 100 2.5 100k RESISTANCE (Ω) Figure 34. PSRR vs. Frequency 11279-135 0 Figure 37. Output Common-Mode Voltage vs. RCM to VBAT 3.0 0.1 OUTPUT VOLTAGE 1.0 0 0 5 10 15 20 25 30 35 40 TIME (µs) 11279-019 –1.0 Figure 35. AGC Response vs. Time, No Load, Input 100 mV Differential VAGC VOLTAGE VOLTAGE (V) 0.6 0.1 OUTPUT VOLTAGE 1.0 0 0 1 2 3 4 5 TIME (ms) 6 7 8 9 10 11279-020 –1.0 Figure 36. AGC Response vs. Time, CL = 0.01 μF, Input 100 mV Differential Rev. A | Page 11 of 20 2.5 VS = 3V 2.0 1.5 1.0 0.5 0 10k 100k RESISTANCE (Ω) Figure 38. Output Common-Mode Voltage vs. RCM to COMM 11279-136 VOLTAGE (V) 0.6 OUTPUT COMMON-MODE VOLTAGE (V) VAGC VOLTAGE AD8338 Data Sheet THEORY OF OPERATION INTRODUCTION VGA CORE The AD8338 is a single supply variable gain amplifier (VGA) with an adjustable gain range of 80 dB. More accurately, the AD8338 is an input variable gain amplifier (IVGA), which has been designed to accept a wide range of input amplitudes, and via its variable gain, compress it to either a narrow range of output amplitudes or a constant output amplitude (for example, automatic gain control applications). Like other VGAs from Analog Devices, Inc., the AD8338 possesses a constant bandwidth over the entire gain range. Therefore, with a bandwidth of 18 MHz, the AD8338 achieves a gain-bandwidth product of 180 GHz at its highest gain setting (gain of 80 dB). Additionally, the differential output of the AD8338 allows the VGA to directly drive differential input ADCs without the need of a single-ended-to-differential converter. Figure 40 shows a simplified diagram of the VGA core at the heart of the AD8338. The key concepts regarding the operation of this VGA core are as follows: First, the ratio of the collector currents in the two differential pairs (Q1, Q2 and Q3, Q4) is identical given that the two differential pairs share the same base drive. This ratio is represented by the modulation factor, x, where values of x range from −1 and +1. Second, the input current signal is forced into the collectors of the input differential pair (Q1, Q2) by means of the loop amplifier to modulate the fixed tail current, ID, and set the modulation factor, x. The value of x in the input differential pair is replicated to the output differential pair (Q3, Q4) to modulate its fixed tail current, IN, and generate a differential output current. Third, the current gain of this cell is exactly G = IN/ID over many decades of variable bias current. Figure 39 shows a block schematic of the AD8338 depicting the key sections of the VGA and a general overview of its features. The AD8338 signal path is comprised by the 500 Ω input resistors, the VGA core, and the transimpedance output amplifiers. The gain of the signal path is adjusted by the linearin-dB gain interface and the voltage at Pin GAIN with respect to its local ground, Pin COMM. The automatic gain control (AGC) circuit block, is a current output RMS detector that can be used to drive the GAIN pin and configure the AD8338 as an AGC amplifier with constant RMS output amplitude. This output amplitude is adjusted by the voltage at Pin VAGC with respect to the voltage at Pin VREF. The offset null circuit block allows the AD8338 to auto zero any dc offset voltages. To enable the offset null functionality, connect a capacitor between the OFSN and VREF pins. To disable the offset null functionality, connect Pin OFSN to ground. The INPD, INMD, FBKP, and FBKM pins provide access to internal nodes in the VGA core of the AD8338 and output amplifiers allowing the user to adjust the gain range, output common-mode voltage, and bandwidth of the device. VBAT OFSN By varying IN, the overall function of the cell is that of a twoquadrant analog multiplier, exhibiting a linear relationship to both the signal modulation factor, x, and this numerator current. On the other hand, by varying ID, the overall function is that of a two-quadrant analog divider, having a hyperbolic gain function with respect to the modulation factor, x, controlled by this denominator current. Because the AD8338 is an input VGA, it controls ID to adjust the amplifier’s gain. However, because a hyperbolic gain function is generally of less value than one in which the decibel gain is a linear function of a control input, the AD8338 includes a special interface to provide either increasing or decreasing exponential control of ID. OFFSET NULL OUTP INPD IOUT VREF INMD OUTM –26dB TO +54dB 9.5kΩ 500Ω MODE GAIN AUTOMATIC GAIN CONTROL DETO VAGC 11279-200 FBKM GAIN INTERFACE COMM (1+x) IN 2 (1–x) IN 2 + – Q4 Q1 Q2 Q3 NUMERATOR DENOMINATOR BIAS CURRENT BIAS CURRENT IN Figure 40. Simplified Diagram of the VGA Core VGA CORE INMR (1–x) ID 2 ID FBKP 9.5kΩ 500Ω IIN (1–x) ID 2 OUTPUT IS xlN LOOP AMPLIFIER VREF AD8338 INPR G = IN/ID INPUT IS xlD Figure 39. Block Schematic Rev. A | Page 12 of 20 11279-146 OVERALL STRUCTURE OF THE AD8338 Data Sheet AD8338 NORMAL OPERATING CONDITIONS Normal operating conditions for the AD8338 are defined as follows: • • • +VOUT/2 + VREF 500Ω INPD The input pins, INPR and INMR, are voltage driven (the source impedance is assumed to be zero). The output pins, OUTP and OUTM, are open circuited (the load impedance is assumed to be infinite). Pin COMM is grounded. Pin MODE is either tied to a logic high or left unconnected, to set the noninverted gain slope gain mode. lD IIN 1.5V INMD INMR 500Ω OUTM –VOUT/2 + VREF 11279-045 • OUTP INPR 0dB TO 80dB Figure 42. Input Current Applied to the INPD and INMD Pins INPR, INMR, INPD, and INMD Pins OUTP INPR +VOUT/2 + VREF 500Ω INPD VIN 1.5V IIN INMD 500Ω OUTM –VOUT/2 + VREF 0dB TO 80dB 11279-044 INMR 50Ω INPD VIN +VOUT/2 + VREF 500Ω 1.5V IIN 50Ω INMD 500Ω INMR OUTM –VOUT/2 + VREF 20dB TO 80dB Figure 43. Using External Resistors at the INPD and INMD Pins FBKP, FBKM, OUTP, and OUTM Pins Output voltage pins, OUTP and OUTM, have a default common-mode voltage of 1.5 V, the voltage at the VREF reference pin. This output common-mode voltage can be adjusted by injecting common-mode currents into Pin FBKP and Pin FBKM, the summing nodes of the output amplifiers, which are also biased at 1.5 V. The output amplifiers of the AD8338 possess rail-to-rail output stages which allow the output common mode of the VGA to be shifted from ground to the positive supply, though the use of such extreme values leaves only a small range for the differential output signal swing. Adding feedback capacitors, CFBK, across nodes (OUTP, FBKP and OUTM, FBKM) reduces bandwidth of the output amplifiers of the AD8338 and the signal path of the VGA. These capacitors and the feedback resistors of the output amplifiers form a low-pass filter with a cut-off frequency of approximately: fC = Figure 41. Input Voltage Applied to the INPR and INMR Pins The INPD and INMD pins are current input pins (see Figure 42) where the differential input current is directly applied to the VGA core input. This input current can either be generated with an external current source like an unbiased photodiode, or with a voltage source and external coupling resistors (see Figure 43). The latter method allows the gain range of the AD8338 to be shifted as explained in the Explanation of the Gain Function section. When using the INPD and INMD inputs, the INPR and INMR pins should be shorted to one another to prevent stability issues. OUTP INPR 11279-046 The input signal to the AD8338 is accepted at the INPR/INMR and the INPD/INMD differential input ports. These pins are internally biased to approximately 1.5 V, the voltage at reference Pin VREF. The INPR and INMR pins are voltage input pins (see Figure 41) where the differential input voltage and the internal input resistors generate current, IIN, the input current for the VGA core. While the voltage inputs can be driven in either a single-sided or a differential manner, operation using a differential drive is preferable, and is assumed in all specifications, unless otherwise stated. The pin-to-pin input resistance between the voltage inputs is specified as 1000 Ω ± 20%. In most cases, the voltage input pins are ac-coupled via two capacitors chosen to provide adequate low frequency transmission. This results in the minimum input noise that increases when a common-mode voltage other than 1.5 V is forced onto these input pins. The short-circuit (INPR shorted to INMR) input-referred noise at maximum gain is approximately 4.5 nV/√Hz. 1 2π × RFBK × C FBK (1) where RFBK are the internal feedback resistors of the output amplifiers. RFBK is specified as 9800 Ω ± 20%. Reducing the bandwidth of the AD8338 minimizes output noise and simplifies the design of the antialiasing filter when using the VGA to drive an ADC. Rev. A | Page 13 of 20 AD8338 Data Sheet Linear-in-dB Gain Control, GAIN Pin Offset Correction Circuit, OFSN Pin To facilitate the use of an 80 dB gain range, the AD8338 has a linear-in-dB gain control. The gain is controlled by the voltage at Pin GAIN with respect to the local ground COMM. In normal operating conditions, adjusting the voltage at Pin GAIN from 0.1 V to 1.1 V adjusts the gain from its lowest value of 0 dB to its highest value of 80 dB. The basic gain equation is The AD8338 includes an internal offset correction circuit that cancels out any dc offsets that may be present in the VGA. Connecting a capacitor, COFSN, between Pin OFSN and Pin VREF enables the offset correction circuit. G (dB ) = VGAIN − 8 dB 12.5 mV (2) The offset correction circuit uses an internal autozero feedback loop, which introduces small signal high-pass filter characteristics to the signal path. The −3 dB corner frequency is fOFSN = where VGAIN is in volts. Alternatively, the gain equation can be expressed as a numerical gain magnitude VGAIN GN = 0.398 × 10 250 mV (3) where VGAIN is in volts. Inversion of the Gain Slope, MODE Pin Pin MODE controls the polarity of the gain adjustment. That is, Pin MODE allows the slope of the gain function to be inverted. If Pin MODE is tied to VBAT, the gain of the AD8338 increases exponentially (or linear-in-dB) with an increase in the voltage at Pin GAIN. If Pin MODE is tied to COMM, the gain of the AD8338 decreases exponentially (or linear-in-dB) with an increase in the voltage at Pin GAIN. Figure 44 shows the two gain control modes when the AD8338 is configured in normal operating conditions. To provide a dc-coupled signal path, the offset correction circuit can be disabled by connecting Pin OFSN to Pin COMM. Exercise caution when operating the AD8338 with the offset correction circuit disabled, because at large gains, dc offsets will cause large dc errors at the outputs of the VGA. 70 HIGH MODE 60 40 30 20 10 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VGAIN (V) 1.1 11279-103 GAIN (dB) 50 0 0.1 (4) Even though the AD8338 exhibits a high-pass filter characteristic in its transfer function when the offset correction circuit is enabled, the latter should not be used as a high-pass filter due to the narrow voltage range of dc input voltages the circuit can reject. If signals at frequencies below the band of interest need to be rejected, for best performance, incorporate a high-pass filter preceding the AD8338. This can be achieved by accoupling the inputs as shown in Figure 41. 80 LOW MODE 1 2π × 400 Ω × COFSN Figure 44. Two Gain Control Modes of the AD8338 Rev. A | Page 14 of 20 Data Sheet AD8338 AGC Circuit, VAGC Pin OUTPUT AMPLITUDE (mV rms) In this configuration, the AGC circuit compares the RMS output amplitude of the VGA with the desired RMS output amplitude (voltage at Pin VAGC with respect to the voltage at Pin VREF), and drives Pin GAIN to minimize their difference. Therefore, in steady state conditions, the circuit forces the RMS output amplitude of the AD8338 to be the voltage at Pin VAGC with respect to the voltage at Pin VREF. Because the AGC circuit uses negative feedback, the gain slope of the AD8338 needs to be inverted by connecting Pin MODE to ground. The bandwidth of the AGC circuit is dictated by Capacitor CDETO. Choose this capacitor carefully to ensure that the bandwidth of the AGC circuit is high enough so that it can react to fast changes in the input signal’s amplitude, but low enough to prevent the AGC circuit from distorting the signal of interest. For example, in an on-off keying (OOK) application with a carrier frequency of 6.8 MHz and a bit rate of 10 kb/s, it is recommended to use a 0.01 µF capacitor. This capacitor value ensures that the gain reacts to the bit energy but does not react to the carrier signal. OFSN 1200 1000 1000 800 800 600 600 400 400 200 200 0 –1.0 –0.8 0 –0.6 –0.4 –0.2 0 0.2 The AD8338 includes an internal 1.5 V voltage reference that is used to set the quiescent bias voltages of many key nodes in the VGA. These nodes include inputs pins (INPR, INMR, INPD, and INMD), output pins (OUTP and OUTM), and feedback pins (FKBP and FBKM). The output voltage of the internal reference, Pin VREF, maybe bypassed with a 0.1 µF capacitor to Pin COMM, but do not force it externally. VREF AD8338 FBKP OUTP OUTPUT STAGE 0dB OUTM INMR 0dB TO 80dB VREF INPD FBKM DETO VAGC AUTOMATIC GAIN CONTROL GAIN INTERFACE GAIN 1.0 Internal Reference, Pin VREF INPR MODE 0.8 Not all applications require the AGC circuit. Therefore, the AGC circuit can be disabled by connecting Pin DETO to ground, and connecting Pin VAGC to Pin VREF. VGA CORE CAGC 0.01µF AGC SETPOINT 11279-148 COMM 0.6 VAGC – VREF (V) OFFSET NULL INMD 0.4 Figure 45. Output RMS Voltage and VGAIN vs. VAGC – VREF As mentioned previously, the AGC circuit forces the RMS output amplitude of the AD8338 to be the voltage at Pin VAGC with respect to the voltage at Pin VREF. Furthermore, the input to the AGC circuit, Pin VAGC, is symmetrical with respect to Pin VREF. In other words, the AGC circuit responds to the VBAT 1200 11279-147 The AD8338 includes a current output RMS detector that can be used to configure the AD8338 as an AGC amplifier (see Figure 46). VGAIN (mV) absolute value of the difference in voltage between Pin VAGC and Pin VREF (see Figure 45). Figure 46. AD8338 Configured as an AGC Amplifier Rev. A | Page 15 of 20 AD8338 Data Sheet EXPLANATION OF THE GAIN FUNCTION Equation 8 and Equation 9 show that the gain range of the AD8338 can be shifted by using external input resistors, RP and RN. For example, driving the INPD and INMD pins with an RP and RN of 50 Ω shifts the gain range of the AD8338 up by 20 dB, from 20 dB to 100 dB (see Figure 43). Similarly, driving the INPD and INMD pins with an RP and RN of 5 kΩ, shifts the gain range down by 20 dB, from −20 dB to +60 dB. The signal chain of the AD8338 can be broken down into three stages. The first stage is a differential voltage-to-current converter comprised by the input resistors, RP and RN, of the VGA. These input resistors may either be the internal 500 Ω resistors coupled to Pin INPR and Pin INMR, or external resistors coupled to Pin INPD and Pin INMD. The transresistance of the voltage-to-current converter is RP + RN such that the current flowing in the resistors is given by: I IN = VINPx − VINMx As shown in Figure 43, when using external resistors to drive the INPD and INMD pins, short the INPR and INMR pins to one another to prevent stability issues. (5) RP + RN The current in the input resistors, IIN, is fed to the second stage of the AD8338, the VGA core. The VGA core is a fully differential variable gain current amplifier with a gain range of 80 dB. In the noninverting gain slope setting (Pin MODE connected to Pin VBAT), the current gain of the VGA core spans from −26 dB (VGAIN = 0.1 V) to +54 dB (VGAIN = 1.1 V). In numerical gain magnitude, the gain of the VGA core is given by I OUT ,VGA = I IN × 10 (80 VGAIN −34 ) / 20 ≈ I IN × 0.02 × 10 VGAIN 250 mV (6) The differential output current of the VGA core is fed to the third stage of the AD8338, a fully differential current-to-voltage converter comprised by the output amplifiers and their corresponding feedback resistors, RFBK. The overall transimpedance of the current to voltage converter is 2RFBK, such that the differential output voltage of the stage is given by: VOUT ,DIFF = IOUT ,VGA × 2 × RFBK Effects of Using External Resistors When the gain range is shifted through the use of external resistors, several trade-offs must be considered. External resistors connected to Pin INPD and Pin INMD load the current inputs of the VGA core changing the dynamic behavior of the block and the −3 dB bandwidth of the AD8338. The −3 dB bandwidth of the AD8338 with external resistors is 500 Ω × REXT fCL = 18 MHz× 500 Ω + R EXT (7) − 34 (8) Alternatively, the gain equation can be expressed as a numerical gain magnitude, VGAIN mV 2 × RFBK GN = 0.02 × × 10 250 RP + RN (10) For example, with 50 Ω external resistors, the input-referred noise at maximum gain decreases to approximately 1 nV/√Hz and the gain range shifts up by 20 dB. However, the −3 dB bandwidth is reduced from 18 MHz to approximately 1.8 MHz. Therefore, the overall voltage gain of the AD8338 is: 2 × R FBK G (dB ) = 80 × VGAIN × 20 × log RP + RN × 1 500 Ω (9) Rev. A | Page 16 of 20 Data Sheet AD8338 ADJUSTING THE OUTPUT COMMON-MODE VOLTAGE FBKP 9.5kΩ FBKP OUTP = 1.5V – R1 lOUT 9.5kΩ (0 – 1.5V) × 9.5kΩ R2 + VOUT/2 R2 VBAT FBKM COMM Figure 48. Increasing the Output Common-Mode Voltage OUTP = 1.5V – (VBAT – 1.5V) × 9.5kΩ R1 Table 5 and Table 6 show suggested values for the external resistors shown in Figure 47 and Figure 48. + VOUT/2 Table 5. Resistor Values for Decreasing the Output Common-Mode Voltage VREF = 1.5V OUTM = 1.5V – 9.5kΩ (VBAT – 1.5V) × 9.5kΩ R2 + VOUT/2 R2 FBKM VBAT Figure 47. Decreasing the Output Common-Mode Voltage 11279-150 lOUT + VOUT/2 VREF = 1.5V OUTM = 1.5V – R1 9.5kΩ (0 – 1.5V) × 9.5kΩ 11279-151 The output common-mode voltage of the AD8338 differential outputs is nominally set to 1.5 V, the voltage at Pin VREF. This output common-mode voltage can be adjusted by connecting a resistor from each of the output amplifier’s summing nodes (Pin FBKP and Pin FBKM) to either Pin COMM or Pin VBAT. Connecting a resistor from Pin FBKP and Pin FBKM to Pin VBAT decreases the output common-mode voltage, whereas connecting a resistor from Pin FBKP and Pin FBKM to Pin COMM increases the output common-mode voltage (see Figure 47 and Figure 48). COMM R1 VBAT (V) 5.0 3.3 3.0 Target VOCM (V) 0.9 0.9 0.9 Resistor Value (Ω) 55,417 28,500 23,750 Tied to VBAT VBAT VBAT Table 6. Resistor Values for Increasing the Output Common-Mode Voltage VBAT (V) Any Any Any Rev. A | Page 17 of 20 Target VOCM (V) 1.8 2.0 2.5 Resistor Value (Ω) 47,500 28,500 14,250 Tied to COMM COMM COMM AD8338 Data Sheet APPLICATIONS INFORMATION The AD8338 amplifies the signal (the gain is set by an external controller) and drives a full-wave rectifier bridge. The output of this bridge is then low-pass filtered into 100 Ω terminations. This design provides excellent rejection of RF and excellent baseband information recovery for the decision stage that follows. The excellent performance of the AD8338 results in a flat response over various gains with rail-to-rail output signal swing, high drive capability, and a very high dynamic range at a low 12 mW. These features make the AD8338 an exceptional choice for use in batteryoperated equipment, low frequency and baseband applications, and many other applications. The reactive filter components—Capacitors C1 through C4 and Inductors L1 and L2—set the baseband recovery performance. A design trade-off exchanges baseband response for RF attenuation. SIMPLE ON-OFF KEYED (OOK) RECEIVER For low complexity, low power data communications, a simple link built using a modulating carrier tone in an on/off state provides a fast and cost-effective solution to the designer. Such designs are used in a variety of applications, including nearfield communications among noninterference mechanical systems, low data rate sensors, RFID tags, and so on. Table 7 provides typical values for these components at two data rates. Note that Capacitors C1 through C4 are all of equal value, and Inductor L2 has the same value as L1. Table 7. Typical Values for Components in Reactive Filter The schematic shown in Figure 49 demonstrates a complete inductive telemetry on-off keyed (OOK) front end. The crystal is cut for the target receive frequency of interest, creating a very narrow-band filter, typically around the 6.78 MHz ISM band. VREF U1 COMM OUTM D4 OFSN DETO GAIN D2 C1 C2 R1 100Ω OUTP AD8338 INMR C6 0.01µF OOK_P D1 INPR L1 and L2 240 µH 82 µH L1 MODE CTUNE ANTENNA CRYSTAL C1 to C4 12 nF 3.9 nF R2 100Ω L2 D3 OOK_M C3 C5 0.1µF VREF Figure 49. Complete, Low Power OOK Receiver Rev. A | Page 18 of 20 C4 11279-048 3.0V Data Rate 19,200 bps 57,600 bps Carrier Attenuation (f = 6.78 MHz) −101 dB −73 dB Data Sheet AD8338 The AD8338 can be coupled directly to the AD7450 for full dc-to-18 MHz operation at the highest level of performance with low operating power (160 mW typical). The glueless interface enables a physically small, high performance data acquisition system that is ideal for many field instruments. A filter before the VGA provides the antialiasing function and noise limiting. INTERFACING THE AD8338 TO AN ADC The AD8338 is well suited to drive a high speed analog-to-digital converter (ADC) and is compatible with many ADCs from Analog Devices. This example illustrates the interfacing of the AD8338 to the AD7450. The AD7450 is a low power, 3.0 V ADC, which is also competitively priced for a low cost total solution. In applications where the modulated information is not encoded in the signal amplitude, use the AGC feature of the AD8338 to reduce any bit errors in the sampled signal. Figure 50 shows the basic connections between the AD8338 and the AD7450. The common-mode voltage provided by the AD8338 is within the specifications of the AD7450. 3.0V 3.0V U1 AD8338 OUTP VREF VIN+ OUTM VIN– U2 AD7450 SCLK SDATA TO MICROCONTROLLER CS C2 0.1µF Figure 50. Basic Connections to the AD7450 ADC Rev. A | Page 19 of 20 11279-149 C1 0.1µF GND OFSN MODE COMM INMR DETO FILTER OUTPUT INPR C4 0.1µF VREF GAIN CONTROL VDD C4 0.1µF R1 5.1Ω C3 0.1µF GAIN VBAT 3.0V AD8338 Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR 0.30 0.23 0.18 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.75 1.60 SQ 1.45 9 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 4 8 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. 08-16-2010-E 3.10 3.00 SQ 2.90 Figure 51. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters ORDERING GUIDE Model1 AD8338ACPZ-R7 AD8338ACPZ-RL AD8338-EVALZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] AD8338 Evaluation Board Z = RoHS Compliant Part. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11279-0-11/13(A) Rev. A | Page 20 of 20 Package Option CP-16-22 CP-16-22 Branding Y4K Y4K