Precision Quad Comparator HA-4902/883 Features The HA-4902/883 is a monolithic, quad, precision comparator offering fast response time, low offset voltage, low offset current and virtually no channel-to-channel crosstalk for applications requiring accurate, high speed, signal level detection. This comparator can sense signals at ground level while being operated from either a single +5V supply (digital systems) or from dual supplies (analog networks) up to ±15V. The HA-4902/883 contains a unique current driven output stage which can be connected to logic system supplies (VLOGIC+ and VLOGIC -) to make the output levels directly compatible (no external components needed) with any standard logic or special system logic levels. In combination analog/digital systems, the design employed in the HA-4902/883 input and output stages prevents troublesome ground coupling of signals between analog and digital portions of the system. • This circuit is processed in accordance to MIL-STD-883 and is fully conformant under the provisions of Paragraph 1.2.1 This comparators’ combination of features make it an ideal component for signal detection and processing in data acquisition systems, test equipment and microprocessor/analog signal interface networks. Pin Configuration HA-4902/883 (16 LD CERDIP) TOP VIEW VL+ 1 OUT 1 2 -IN 1 3 +IN 1 4 V- 5 +IN 2 6 -IN 2 7 OUT 2 8 1 + + 2 - • Low Input Sensitivity - Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5mV - Typical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.05mV • Low Offset Current (+25°C) - Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35nA - Typical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10nA • Single or Dual Voltage Supply Operation • Selectable Output Logic Levels • Active Pull-Up/Pull-Down Output Circuit. No External Resistors Required • Threshold Detector 15 -IN 4 14 +IN 4 13 V+ + 3 - • Low Offset Voltage (+25°C) - Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0mV - Typical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0mV Applications 16 OUT 4 4 + • Fast Response Time (+25°C) - Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215ns - Typical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180ns • Zero Crossing Detector • Window Detector • Analog Interfaces for Microprocessors • High Stability Oscillators • Logic System Interfaces 12 +IN 3 11 -IN 3 Ordering Information 10 OUT 3 9 VL- PART NUMBER PART MARKING TEMP RANGE (°C) PACKAGE PKG. DWG. # HA1-4902/883 HA1-4902/883 -55 to +125 16 Ld CERDIP F16.3 May 3, 2012 FN3929.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 1994, 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. HA-4902/883 Absolute Maximum Ratings Thermal Information Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . 35V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50mA Output Short Circuit Current Duration . . . . . . . . . . . . . . . . . . . . . . Indefinite (One Amplifier Shorted to GND) ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V Thermal Resistance (Typical, Note 1) θJA (°C/W) θJC (°C/W) CERDIP Package . . . . . . . . . . . . . . . . . . . . . 76 17 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to +150°C Package Power Dissipation Limit at +75°C CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.31W Package Power Dissipation Derating Factor Above +75°C CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1mW/°C Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . . . . . . . +300°C Recommended Operating Conditions Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V Logic Supply Voltage (VL+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V Logic Reference Voltage (VL-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: Supply Voltage = ±15V, VL+ = 5V, VL- = 0V, unless otherwise specified. D.C. PARAMETERS Input Offset Voltage Input Bias Current SYMBOL VIO VCM = 0V, VOUT = 1.4V (See Note 4) +IB VCM = 0V -IB Input Offset Current Input Sensitivity Output Voltage Levels VCM = 0V IIO VCM = 0V INSEN (See Note 4) VOL ISINK = 3mA VOH Output Current ISOURCE = 3mA ISINK VOUT ≤0.4V ISOURCE Supply Current +ICC VOUT ≥3.5V VOUT = VOL, VOH -ICC Logic Current CONDITIONS VOUT = VOL, VOH IL VOUT = VOL, VOH 2 GROUP A SUBGROUPS TEMP (°C) MIN MAX UNITS 1 +25 -5 5 mV 2, 3 +125, -55 -8 8 mV 1 +25 -150 150 nA 2, 3 +125, -55 -200 200 nA 1 +25 -150 150 nA 2, 3 +125, -55 -200 200 nA 1 +25 -35 35 nA 2, 3 +125, -55 -45 45 nA 1 +25 -0.5 0.5 mV 2, 3 +125, -55 -0.6 0.6 mV 1 +25 - 0.4 V 2, 3 +125, -55 - 0.4 V 1 +25 3.5 - V 2, 3 +125, -55 3.5 - V 1 +25 3 - mA 2, 3 +125, -55 3 - mA 1 +25 - -3 mA 2, 3 +125, -55 - -3 mA 1 +25 - 20 mA 2, 3 +125, -55 - 20 mA 1 +25 - 8 mA 2, 3 +125, -55 - 10 mA 1 +25 - 6 mA 2, 3 +125, -55 - 8 mA FN3929.1 May 3, 2012 HA-4902/883 TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Table 2 Intentionally left blank. See A. C. Specifications on Table 3. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Characterized at: Supply Voltage = ±15V, VL+ = 5V, VL- = 0V, unless otherwise specified. PARAMETER SYMBOL Response Time Common Mode Range CONDITIONS NOTES TEMP (°C) MIN MAX UNITS tpd0 +100mV Input Step, +10mV Overdrive 2, 3 +25 - 200 ns tpd1 -100mV Input Step, -10mV Overdrive 2, 3 +25 - 200 ns +CMR 2 +25 - 12.4 V -CMR 2 +25 -15 - V NOTES: 2. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. 3. F ≈ 100Hz, duty cycle ≈ 50%, inverting input driven, all unused inverting inputs tie to +5V. 4. Refer to enlarged area of test waveform A. Offset voltage is measured when VOUT = 1.4V. Sensitivity is measured on the transition edge at 0.4V and 3.5V. Sensitivity is the change in differential input voltage required to change the output state. Sensitivity includes the effects of offset voltage, offset current, common mode rejection and voltage gain. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-In) Final Electrical Test Parameters SUBGROUPS (SEE TABLE 1 ) 1 1 (Note 5), 2, 3 Group A Test Requirements 1, 2, 3 Groups C and D Endpoints 1 NOTE: 5. PDA applies to Subgroup 1 only. 3 FN3929.1 May 3, 2012 HA-4902/883 Test Circuit (Applies to Tables 1 and 2) I SWITCH POSITION 1 FOR D.C. PARAMETERS SWITCH POSITION 2 FOR A.C. PARAMETERS 1 OF 4 TEST LOOPS FOR THE HA-4902/883 DUT ENLARGED VIEW Test Waveform A (Applies to Table 1) ENLARGED VIEW DUT OUTPUT: CHANNEL B Test Waveform B (Applies to Table 3) RESPONSE TIME NOTE: Response time testing is done after VIO testing to acquire the actual device offset voltage. 10mV overdrive is then added (or subtracted depending on state) to this measured VIO value. 4 FN3929.1 May 3, 2012 HA-4902/883 Burn-in Circuit HA1-4902/883 CERAMIC DIP fo NOTES: R1 = 5kΩ, ±5% C1, C2, C3 = 0.01µF/Socket (Min) or 0.1µF/Row (Min) C4, C5, C6 = 0.01µF/Socket (Min) or 0.1µF/Row (Min) D1, D2, D3 = 1N4002 or Equivalent/Board |(V+) - (V-)| = 30V VL- = 0V, VL+ = 0.5V fO = 5V (Static Burn-In) 5 FN3929.1 May 3, 2012 HA-4902/883 Schematic Diagram (1/4 of HA-4902/883) R1 500Ω R9 4kΩ PR1 200kΩ R10 4kΩ Q1 Q11 Q2 R2 13kΩ R3 1kΩ R4 1kΩ Q12 Q13 Q14 D11A R6 2.5kΩ R7 2.5kΩ V+ R5 360Ω Q15 R18 664Ω Q16 Q26 Q23 Q3 Q4C D4B D4A Q24 Q19 Q38 Q37 Q20 Q9D Q9C Q9B Q18 +IN -IN Q22 Q33 Q30 Q34 D9A R20C 1kΩ R20B 1kΩ OUT MN6 R24 14kΩ R23 MN5 100Ω Q31 R15 8kΩ Q9A MN2 Q10 R20D 1kΩ R22 100Ω D29B D35 Q21 Q17 BIAS 1 BIAS 4 Q32 Q29 D39 R16 540Ω BIAS 3 R12 Q29A 8kΩ Q28 Q36 Q5 BIAS 2 VLOGIC+ D45 Q7 Q4 R11 8kΩ Q25 R20A 1kΩ R21 1kΩ R17 19kΩ MN1 R14 5kΩ VLOGICMN4 MN3 V- 6 FN3929.1 May 3, 2012 HA-4902/883 Die Characteristics DIE DIMENSIONS: 90mils x 102mils x 20mils ± 1mil 2280µm x 2600µm x 508µm ± 25.4µm METALLIZATION: GLASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ± 2kÅ Nitride Thickness: 3.5kÅ ± 1.5kÅ WORST CASE CURRENT DENSITY: 0.4 x 105A/cm2 Type: Al, 1% Cu Thickness: 16kÅ ± 2kÅ SUBSTRATE POTENTIAL (POWERED UP): VTRANSISTOR COUNT: 137 PROCESS: Bipolar and MOS Dielectric Isolation Metallization Mask Layout HA-4902/883 7 FN3929.1 May 3, 2012 HA-4902/883 Design Information The information contained in this section has been developed through characterization and is for use as application and design aid only. These characteristics are not 100% tested and no product guarantee is implied. Typical Performance Curves TA = +25°C, VS = ±15V, VLOGIC+ = 5V, VLOGIC- = 0V, Unless Otherwise Specified INPUT OFFSET CURRENT (nA) 80 60 40 20 0 -55 -25 0 25 50 75 100 15 10 5 0 125 -55 -25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 1. INPUT BIAS CURRENT vs TEMPERATURE FIGURE 2. INPUT OFFSET CURRENT vs TEMPERATURE 80 INPUT BIAS CURRENT (nA) INPUT BIAS CURRENT (nA) 100 60 40 20 0 -15 -12 -9 -6 -3 0 +3 +6 +9 +12 +15 COMMON MODE INPUT VOLTAGE FIGURE 3. INPUT BIAS CURRENT vs COMMON MODE INPUT VOLTAGE (VDIFF = 0V) 8 FN3929.1 May 3, 2012 HA-4902/883 Design Information (Continued) The information contained in this section has been developed through characterization and is for use as application and design aid only. These characteristics are not 100% tested and no product guarantee is implied. Typical Performance Curves SUPPLY CURRENT (mA) 10 7 V+ = 5V VLOGIC+ = 5V VLOGIC- = GND IPSL, VOUT = H IPS+, VOUT = L 8 SUPPLY CURRENT (mA) 12 TA = +25°C, VS = ±15V, VLOGIC+ = 5V, VLOGIC- = 0V, Unless Otherwise Specified (Continued) IPS+, VOUT = H 6 IPS-, VOUT = L 4 IPS-, VOUT = H IPSL, VOUT = L 2 0 -25 0 5 IPS+, VOUT = H 4 IPS+, VOUT = L 3 IPSL, VOUT = L 2 V+ = 5V VLOGIC+ = 5V VLOGIC- = GND 1 IPSL, VOUT = H -50 6 25 50 75 100 125 0 -50 TEMPERATURE (°C) FIGURE 4. SUPPLY CURRENT vs TEMPERATURE (FOR ±15V SUPPLIES AND +5V LOGIC SUPPLY) 0 25 50 TEMPERATURE (°C) 75 100 125 FIGURE 5. SUPPLY CURRENT vs TEMPERATURE (FOR SINGLE +5V OPERATION) 5 5 OVERDRIVE = 20mV 3 OVERDRIVE = 5mV 4 VOUT (V) 4 OVERDRIVE = 2mV 2 3 OVERDRIVE = 20mV OVERDRIVE = 5mV 2 1 1 0 0 0 -100mV OVERDRIVE = 2mV VIN VIN VOUT (V) -25 -100mV 0 0 100 200 TIME (ns) 300 400 0 100 200 TIME (ns) 300 400 FIGURE 6. RESPONSE TIME FOR VARIOUS INPUT OVERDRIVES 9 FN3929.1 May 3, 2012 HA-4902/883 Design Information (Continued) The information contained in this section has been developed through characterization and is for use as application and design aid only. These characteristics are not 100% tested and no product guarantee is implied. Typical Performance Curves TA = +25°C, VS = ±15V, VLOGIC+ = 5V, VLOGIC- = 0V, Unless Otherwise Specified (Continued) 2.0 250 CERDIP POWER DISSIPATION (mW) PACKAGE DISSIPATION (W) 1.75 1.50 1.25 1.0 0.75 0.50 200 150 V+ 100 V- 50 0.25 0 VLOGIC+ 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 7. MAXIMUM PACKAGE DISSIPATION vs AMBIENT TEMPERATURE 0 0 2 4 6 8 10 SUPPLY VOLTAGE (V) 12 14 FIGURE 8. POWER DISSIPATION vs SUPPLY VOLTAGE (NO LOAD CONDITION) NOTE: Total Power Dissipation (TPD) is the sum of individual dissipation contributions of V+, V-, and VLOGIC shown in curves of Power Dissipation vs Supply Voltages. The calculated TPD is then located on the graph of maximum Allowable Package Dissipation vs Ambient Temperature to determine ambient temperature operating limits imposed by the calculated TPD (see Performance Curves). For instance, the combination of ±15V, 5V, 0V (±V, VLOGIC+, VLOGIC-) gives a TPD of 350mW, the combination ±15V, 0V gives a TPD of 450mW. 10 FN3929.1 May 3, 2012 HA-4902/883 Design Information The information contained in this section has been developed through characterization and is for use as application and design aid only. These characteristics are not 100% tested and no product guarantee is implied. Typical Performance Characteristics specified. PARAMETERS Offset Voltage CONDITIONS Note 4 Input Bias Current Input Offset Current Device Characterized at: Supply Voltage = ±15V, VL+ = 5V, VL- = 0V, unless otherwise TEMP TYPICAL DESIGN LIMIT UNITS Full 0.5 Table 1 mV +25°C 50 Table 1 nA Full 90 Table 1 nA +25°C 10 Table 1 nA Full 20 Table 1 nA Input Sensitivity Note 4 Full 50 Table 1 µV Output Level VOL; ISINK = 3mA Full 0.15 Table 1 V VOH; ISOURCE = 3mA Full 4.3 Table 1 V +ICC; VOUT = VOH Full 10 Table 1 mA +ICC; VOUT = VOL Full 15 Table 1 mA -ICC; VOUT = VOH Full -6 Table 1 mA -ICC; VOUT = VOL Full -8 Table 1 mA IL; VOUT = VOH Full 2 Table 1 mA IL; VOUT = VOL Full 4 Table 1 mA tpd0 Full 150 Table 3 ns tpd1 Full 150 Table 3 ns Supply Current Logic Current Response Time Applying the HA-4902 Comparator Unused Inputs Supply Connections Inputs of unused comparator sections should be tied to a differential voltage source to prevent output “chatter” (VDIFF ≥ VIO). All unused inverting inputs may be tied to +5V and non-inverting inputs tied to ground. This device is exceptionally versatile in working with most available power supplies. The voltage applied to the V+ and V- terminals determines the allowable input signal range; while the voltage applied to the VL+ and VL- determines the output swing. In systems where dual analog supplies are available, these would be connected to V+ and V-, while the logic supply and return would be connected to VLOGIC+ and VLOGIC -. The analog and logic supply commons can be connected together at one point in the system, since the comparator is immune to noise on the logic supply ground. A negative output swing may be obtained by connecting VL+ to ground and VL- to a negative supply. Bipolar output swings (15VP-P, Max) may be obtained using dual supplies. In systems where only a single logic supply is available (+5V to +15V), V+ and VLOGIC+ may be connected together to the positive supply while V- and VLOGIC- are grounded. If an input signal could swing negative with respect to the V- terminal, a resistor should be connected in series with the input to limit input current to <5mA since the C-B junction of the input transistor would be forward biased. 11 Crosstalk Simultaneous high frequency operation of all other channels in the package will not affect the output logic state of a given channel, provided that its differential input voltage is sufficient to define a given logic state (ΔVIN ≥ ±VIO). Low level or high impedance input lines should be shielded from other signal sources to reduce crosstalk and interference. Power Supply Decoupling Decouple all power supply lines with 0.01µF ceramic capacitors to a ground line located near the package to reduce coupling between channels or from external sources. Response Time Fast rise time (<200ns) input pulses of several volts amplitude may result in delay times somewhat longer than those illustrated for 100mV steps. Operating speed is optimized by limiting the maximum differential input voltage applied, with resistor-diode clamping networks. FN3929.1 May 3, 2012 HA-4902/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 -D- -A- BASE METAL SYMBOL E M -Bbbb S C A-B S -C- 2 0.36 0.58 3 1.14 1.65 - 0.045 0.58 1.14 4 0.018 0.20 0.46 2 0.008 0.015 0.20 - 0.840 0.36 b1 0.014 0.023 b2 0.045 0.065 b3 0.023 c 0.008 c1 D E 0.220 α eA eA/2 aaa M C A - B S D S - 0.66 0.026 A A ccc M C A - B S 5.08 0.200 A e - 0.014 b2 b MAX b L S1 MIN A Q SEATING PLANE MAX M (b) D BASE PLANE MILLIMETERS MIN b1 SECTION A-A D S INCHES (c) c e D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 0.310 5.59 0.100 BSC NOTES 0.38 3 21.34 5 7.87 5 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 α 90o 105o 90o - 7 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 16 5. This dimension allows for off-center lid, meniscus, and glass overrun. 16 8 Rev. 0 4/94 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN3929.1 May 3, 2012