Cypress Roadmap: Synchronous SRAMs Q2 2016 001-94959 Rev *F Owner: ADMU BUM: OHP Synchronous SRAM Roadmap Synchronous SRAM Portfolio High Random Transaction Rate (RTR)1 | Low Latency | High Bandwidth Standard Sync and NoBL™ Standard Sync and NoBL™ with ECC2 QDR® -II/ DDR-II QDR-II+/ DDR-II+ QDR-II+X/ DDR-II+X QDR-IV Max RTR1: 250 MT/s Max BW: 18 Gbps Latency: 1 Cycle Pipeline and Flow-through Modes Max RTR1: 250 MT/s Max BW: 18 Gbps Latency: 1 Cycle Pipeline and Flow-through Modes Max RTR1: 666 MT/s Max BW: 47.9 Gbps Latency: 1.5 Cycles CIO3 and SIO4 Max RTR1: 666 MT/s Max BW: 79.2 Gbps Latency: 2 or 2.5 Cycles CIO3and SIO4, ODT5 Max RTR1: 900 MT/s Max BW: 91.1 Gbps Latency: 2.5 Cycles SIO4, ODT5 Max RTR1: 2.1 GT/s Max BW: 153.5 Gbps Latency: 5 or 8 Cycles Dual-Port Bidirectional ODT5 CY7C161/2xKV18 144Mb; 250-333 MHz 1.8 V; x9, x18, x36 Burst 2, 4 CY7Cx4/5/6/7xKV18 144Mb; 300-550 MHz 1.8 V; x18, x36 Burst 2, 4 CY7C151/2xKV18 72Mb; 250-333 MHz 1.8 V; x9, x18, x36 Burst 2, 4 CY7Cx54/5/6/7KV18 72Mb; 250-550 MHz 1.8 V; x18, x36 RH6; Burst 2, 4 CY7C156/7xXV18 72Mb; 366-633 MHz 1.8 V; x18, x36 Burst 2, 4 CY7C141/2xKV18 36Mb; 250-333 MHz 1.8 V; x8, x9, x18, x36 Burst 2, 4 CY7Cx24/5/6/7xKV18 36Mb; 400-550 MHz 1.8 V; x18, x36 Burst 2, 4 CY7C126/7x 36Mb; 366-633 MHz 1.8 V; x18, x36 Burst 2, 4 CY7C131/2/9xKV18 18Mb; 250-333 MHz 1.8 V; x8, x18, x36 Burst 2, 4 CY7Cx14/5/6/7xKV18 18Mb; 400-550 MHz 1.8 V; x18, x36 Burst 2, 4 CY7C147/8xB 72Mb; 133-250 MHz 2.5, 3.3 V; x18, x36 Density NEW CY7C144/6xK 36Mb; 133-250 MHz 2.5, 3.3 V; x36, x72 CY7C144/6xK 36Mb; 133-250 MHz 2.5, 3.3 V; x18, x36 NEW CY7C137/8xD/K 18Mb; 100-250 MHz 3.3 V; x18, x32, x36 CY7C137/8xK 18Mb; 100-250 MHz 2.5, 3.3 V; x18, x36 CY7C135/6xC 9Mb; 100-250 MHz 3.3 V; x18, x32, x36 Auto E7 NEW CY7C41xKV13 144Mb; 667-1066 MHz 1.3 V; x18, x36 Burst 2 NEW CY7C40xKV13 72Mb; 667-1066 MHz 1.3 V; x18, x36 Burst 2 CY7C1911xKV18 18Mb; 250-333 MHz 1.8 V; x9 Burst 2, 4 CY7C134/2xG 2,4Mb; 100-250 MHz 3.3 V; x18, x32, x36 Random Transaction Rate 1 Rate of truly random accesses to memory, expressed in transactions per second (MT/s, GT/s) 001-94959 Rev *F 2 Error-correcting 3 Common I/O 4 Separate I/O Owner: ADMU BUM: OHP code 5 On-die termination; parts are CY7C2x hardened, military grade 7 AEC-Q100 -40ºC to +125ºC 6 Radiation Synchronous SRAM Roadmap Production Sampling Development Concept Status Availability QQYY QQYY 2 QDR-IV Product Overview Family Table Switches and routers High-performance computing Military and aerospace systems Test and measurement Density MPN Max Freq RTR QDR-IV HP 72Mb 144Mb CY7C40x1KV13 CY7C41x1KV13 667 MHz 1,334 MT/s QDR-IV XP 72Mb 144Mb CY7C40x2KV13 CY7C41x2KV13 1,066 MHz 2,132 MT/s Block Diagram Available in two options: QDR-IV HP (RTR 1,334 MT/s) and QDR-IV XP (RTR 2,132 MT/s) Two independent, bidirectional DDR1 data ports Error-correcting code (ECC) to reduce soft error rate to less than 0.01 Failure-in-Time (FIT) per megabit Bus inversion to reduce simultaneous switching I/O noise On-die termination (ODT) to reduce board complexity De-skew training to improve signal-capture timing I/O levels: 1.2-1.25 V (HSTL/SSTL), 1.1-1.2 V (POD2) Package: 361-pin FCBGA3 Bus widths: x18, x36 Address/ Control Clock QDR-IV Data Valid x2 x18, x36 Data Port A Address Interface x2 x2 SRAM Array Impedance Matching 1 Double x21,x22 x2 ODT Datasheet: Address Parity Parity Error ECC Data Clocks x2 Bus Inversion Collateral Bus Address Inversion Port x2 Data Port A (HSTL/SSTL or POD) Features Option Data Port B (HSTL/SSTL or POD) Applications Control Logic Control x4 x2 Data Clocks Data Valid x18, x36 Data Port B x2 Bus Inversion Test Engine JTAG Interface Availability QDR-IV datasheets Data Rate: two data transfers per clock cycle 001-94959 Owner: ADMU Rev *F BUM: OHP Sampling: Production: 2 Pseudo Now Now open drain: Signaling interface that uses strong pull-down and weak pull-up drive strength Synchronous SRAM Roadmap 3 Flip-chip ball grid array 3