96696

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Changes in accordance with NOR 5962-R269-97.
97-04-09
R. MONNIN
B
Update boilerplate to reflect current requirements. –rrp
01-06-14
R. MONNIN
C
Add 3.1.1 and APPENDIX A. - ro
04-07-28
R. MONNIN
D
Make correction to die Appendix A figure A-1. - ro
05-03-18
R. MONNIN
REV
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PMIC N/A
PREPARED BY
Sandra Rooney
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
Sandra Rooney
APPROVED BY
Michael A. Frye
DRAWING APPROVAL DATE
96-01-10
REVISION LEVEL
D
MICROCIRCUIT, LINEAR, RADIATION
HARDENED. CMOS FLASH 8-BIT A/D
CONVERTER, MONOLITHIC SILICON
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
1 OF
5962-96696
21
5962-E233-05
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)
and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
96696
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
V
Y
C
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
01
Circuit function
HS9008RH
Radiation hardened CMOS flash 8-bit
A/D converter
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Y
Descriptive designator
CDIP2-T28
CDFP3-F28
Terminals
Package style
28
28
Dual-in-line
Flat pack
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
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REVISION LEVEL
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2
1.3 Absolute maximum ratings. 1/
DC supply voltage range, VDDD = VDDA (Referenced to VSSD = VSSA = GND) ...... -0.3 V dc to +7.0 V dc
Input voltage range: CE1 , CE2, CLK, VREF-, VREF+, VIN, 1/2R ................................ VSS – 0.3 V dc to VDD + 0.3 V dc
Output voltage range: B1 – B8, OF (Outputs off) ....................................................... VSS – 0.3 V dc to VDD + 0.3 V dc
DC input current CE1 , CE2, CLK, VIN, B1 – B8, OF ................................................
Storage temperature range ........................................................................................
Maximum package power dissipation at TA = +125°C (PD): 2/
Case outline X ........................................................................................................
Case outline Y ........................................................................................................
Thermal resistance, junction-to-case (θJC):
Case outline X ........................................................................................................
Case outline Y ........................................................................................................
Thermal resistance, junction-to-ambient (θJA):
Case outline X ........................................................................................................
Case outline Y ........................................................................................................
Lead temperature (soldering, 10 seconds) ................................................................
Junction temperature (TJ) ..........................................................................................
10 mA
-65°C to +150°C
1.02 W
0.77 W
9°C/W
10°C/W
49°C/W
65°C/W
+300°C
+175°C
1.4 Recommended operating conditions.
Operating voltage range (VDDD = VDDA) .................................................................. +4.5 V dc to +5.5 V dc
Digital input low voltage (VIL) ..................................................................................... 0 V to 0.2 VDD
Input high voltage (VIH) ............................................................................................. 0.8 VDD to VDD
Ambient operating temperature range (TA) ............................................................... -55°C to +125°C
1.5 Radiation features
Maximum total dose available (dose rate = 50 – 300 rad/s) ....................................... 300 Krad (Si)
8
Dose rate upset (20 ns pulse) 3/ ............................................................................... >5 x 10 Rad (Si)/s
2
SEP effective let no upset 3/ .................................................................................... >100 MeV/(cm /mg)
14
Neutron irradiation 3/ ................................................................................................ >1 x 10
11
Dose rate survivability 3/ .......................................................................................... >5 x 10
neutrons/cm2
Rad (Si)/s
______
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ If device power exceeds package dissipation capability, provide heat sinking or derate linearly (the derating is based
on θJA) at the following rates:
Case outline X ...................... 20.4 mW/°C
Case outline Y ...................... 15.4 mW/°C
3/ Guaranteed by process or design, not tested.
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A
REVISION LEVEL
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3
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from
the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.2.4 Timing diagrams. The timing diagrams shall be as specified on figure 3.
3.2.5 Radiation exposure circuit. The radiation exposure circuit information shall be as specified in table III.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
ambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
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REVISION LEVEL
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4
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 81 (see MIL-PRF-38535, appendix A).
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REVISION LEVEL
D
SHEET
5
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
1,2,3
01
Limits
Min
Integral linearity error
ILE
Differential linearity error
DLE
VDDD = VDDA = 5.0 V,
CLK = 500 kHz,
Unit
Max
±1
LSB
±0.5
VSSD = VSSA = 0 V,
VREF = 4.000 V (Adj.),
Offset error
VOS
1/
VDDD = VDDA = 5 V,
1,2,3
01
±2.0
LSB
1,2,3
01
±3.0
LSB
1,3
01
300
600
Ω
400
900
VSSD = VSSA = 0 V,
VREF = 4.000 V (Adj.),
VIN = (VREF-) + 0.5 LSB,
CLK = 500 kHz
Gain error
GE
1/
VDDD = VDDA = 5 V,
VSSD = VSSA = 0 V,
VREF = 4.000 V (Adj.),
VIN = (VREF+) - 1.5 LSB,
CLK = 500 kHz
Ladder impedance
REF
1/
VDDD = VDDA = 5 V,
2
VSSD = VSSA = 0 V,
Full scale range
2/
(VIN and (VREF+) – (VREF-))
Supply current
(IDDD + IDDA): Dynamic
FSR
VREF = 4.000 V (Adj.)
1,2,3
01
5
V
IDDD
VDDD = VDDA = 5.5 V,
1,2,3
01
135
mA
1,2,3
01
80
mA
1,2,3
01
±1.0
µA
1,2,3
01
±1.0
µA
VSSD = VSSA = 0 V,
VREF = 4.000 V (Adj.),
CLK = 10 MHz
Supply current
(IDDD + IDDA): Static
IDDS
VDDD = VDDA = 5.5 V,
VSSD = VSSA = 0 V,
VREF = 4.000 V (Adj.),
VIN = VDD or GND
Low level current
IIL
VDDD = VDDA = 5.5 V,
VIN = 0 V
High level current
IIH
VDDD = VDDA = 5.5 V,
VIN = 5.5 V
See footnotes at end of table.
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REVISION LEVEL
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
1,2,3
01
1,2,3
01
1,2,3
01
9,10,11
01
20
MSPS
9,10,11
01
10
MHz
1/ 4/
9,10,11
01
±3.5
%
1/ 4/
9,10,11
01
±3.0
Deg.
9,10,11
01
-48
dB
Min
Low level
voltage
VOL
VDDD = VDDA = 4.5 V,
Unit
Max
0.4
V
IOL = 2 mA
High level
voltage
VOH
VDDD = VDDA = 4.5 V,
2.4
V
IOH = -2 mA
Three-state low
current
Conversion
speed
IOZL
VDDD = VDDA = 5.5 V,
IOZH
VOUT = 0 V, 5.5 V
CS
VDDD = VDDA = 5 V,
2/
±10.0
µA
CLK = 10 MHz,
VSSD = VSSA = 0 V,
VREF = 4.000 V (Adj.),
CLK = 50% duty cycle, square wave
Analog
bandwidth
BW
VDDD = VDDA = 5 V,
3/
CLK = 10 MHz,
VSSD = VSSA = 0 V,
VREF = 4.000 V (Adj.),
VIN = Full scale sine wave
Differential gain
error
DGE
VDDD = VDDA = 5 V,
CLK = 10 MHz,
VSSD = VSSA = 0 V,
VREF = 4.000 V (Adj.)
DPE
Differential
phase error
VDDD = VDDA = 5 V,
CLK = 10 MHz,
VSSD = VSSA = 0 V,
VREF = 4.000 V (Adj.)
Total harmonic
distortion 5/
THD
VDDD = VDDA = 5 V,
CLK = 10 MHz
-48
VREF = 4.000 V (Adj)
CLK = 20 MHz
-42
VDDD = VDDA = 5 V,
CLK = 1 MHz
VSSD = VSSA = 0 V,
Signal-to-noise
ratio (plus
distortion) 5/
SNRD
VSSD = VSSA = 0 V,
VREF = 4.000 V (Adj)
Integral linearity
error
ILE
CLK = 1 MHz
9,10,11
47
01
CLK = 10 MHz
46
CLK = 20 MHz
42
CLK = 10 MHz
9,10,11
dB
±1.0
01
LSB
See footnotes at end of table.
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TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Conditions
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Differential
linearity error
DLE
CLK = 10 MHz
9,10,11
01
Max
±0.75
LSB
Data output
delay
TOD
VDDD = VDDA = 5 V,
9,10,11
01
32
ns
9,10,11
01
25
ns
9,10,11
01
25
ns
4
01
15
pF
4
01
10
pF
4
01
8
Bits
9,10,11
01
20
ns
9,10,11
01
20
ns
VSSD = VSSA = 0 V, CLK = 1 MHz,
VREF = 4.000 V (Adj.)
Output enable
time
TEN
VDDD = VDDA = 5 V,
VSSD = VSSA = 0 V, CLK = 1 MHz,
VREF = 4.000 V (Adj.)
Output disable
time
TDIS
VDDD = VDDA = 5 V,
VSSD = VSSA = 0 V, CLK = 1 MHz,
VREF = 4.000 V (Adj.)
Digital input
capacitance 6/
CI
VDDD = VDDA = OPEN, f = 1 MHz,
VSSD = VSSA = 0 V, TA = +25°C
Ouput
capacitance
6/
CO
VDDD = VDDA = OPEN, f = 1 MHz,
VSSD = VSSA = 0 V, TA = 25°C
Resolution
6/
RES
VDDD = VDDA = 5 V, CLK = 1 MHz,
VSSD = VSSA = 0 V, VREF = 4.000 V
Track time (Auto
balance time)
6/
TTRACK
VDDD = VDDA = 5 V, CLK = 25 MHz,
VSSD = VSSA = 0 V, CLK = High,
VREF = 4.000 V (Adj.)
Hold time
6/
THOLD
VDDD = VDDA = 5 V, CLK = 25 MHz,
VSSD = VSSA = 0 V, CLK = Low,
VREF = 4.000 V (Adj.)
1/
Devices supplied to this drawing have been characterized through all levels M, D, P, L, R, F of irradiation. However, this
device is only tested at the “F” level. Pre and Post irradiation values are identical unless otherwise specified in Table I.
2/
When performing post irradiation electrical measurements for any RHA level, TA = +25°C.
Conversion speed and full scale range are verified during functional test. Functional test is defined as:
3/
TA = +25°C, -55°C; DLE ≤ ±0.75 LSB, ILE ≤ ±2.25 LSB. TA = +125°C; DLE ≤ ±1.00 LSB, ILE ≤ ±3.25 LSB.
Defined at –0.7 dB. The –3 dB bandwidth for frequency response purposes is greater than 30 MHz.
4/
VIN = 3.58 MHz burst, CLK = 14 MHz, 6 DC levels (1.5, 1.7, 1.9, 2.1, 2.3, and 2.5).
5/
Analog input (VIN): For CLK = 1 MHz, VIN = 98.6 KHz sinewave. For CLK = 10 MHz, VIN = 87.9 KHz sinewave.
6/
For CLK = 20 MHz, VIN = 97.7 KHz sinewave.
These parameters are controlled via design or process parameters and not directly tested. These parameters are
characterized upon initial design or process changes which would affect these characteristics.
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Case outline
Device type
Terminal number
1
2
3
4
X and Y
01
Terminal symbol
1/2R
VDDD
CLK
VDDD
5
VSSA
6
VREF-
7
8
9
10
11
12
13
14
VDDA
B1 (LSB)
B2
B3
B4
CE1
CE2
15
VDDD
16
VSSD
17
18
19
20
21
22
23
VSSA
B5
B6
B7
B8 (MSB)
OF
24
VREF+
25
VSSA
26
VSSD
27
VIN
28
VSSD
VDDA
VDDA
FIGURE 1. Terminal connections.
CE1
0
1
X
CE2
B1 – B8
OF
1
1
0
Valid
Three-state
Three-state
Valid
Valid
Three-state
FIGURE 2. Truth table.
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Input Timing
Output Enable Timing
FIGURE 3. Timing diagrams.
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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015.
(2) TA = +125°C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
Subgroups 5, 6, 7, and 8 in table I, method 5005 of MIL-STD-883 shall be omitted.
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TABLE IIA. Electrical test requirements.
Test requirements
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
1/
2/
3/
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
1, 9
Device
class Q
1, 9
Device
class V
1, 9
1, 2, 3,
1/
9, 10, 11
1, 2, 3, 4,
9, 10, 11
1, 2, 3,
9, 10, 11
1, 9
1, 2, 3,
1/
9, 10, 11
1, 2, 3, 4,
9, 10, 11
1, 2, 3,
9, 10, 11
1, 9
1, 2, 3, 2/ 3/
9, 10, 11
1, 2, 3, 4,
9, 10, 11
1, 2, 3, 3/
9, 10, 11
1, 9
1, 9
1, 9
1, 9
PDA applies to subgroup 1.
PDA applies to subgroups 1 and ∆.
Delta limits as specified in table IIB herein shall be required where specified, and the delta
values shall be completed with reference to the zero hour electrical parameters (see table I).
TABLE IIB. Burn-in delta parameters and group C delta parameters (+25°C).
PARAMETER
Signal-to-noise ratio (+distortion)
CLK = 1 MHz
Low level input current
High level input current
SYMBOL
SNRD
DELTA LIMITS
±0.75 dB
±150 nA
IIL
±150 nA
IIH
Three-state low output current
IOZL
Three-state high output current
IOZH
Low level voltage
VOL
High level voltage
VOH
±1.0 µA
±1.0 µA
±60 mV
±160 mV
TABLE III. Irradiation test connections. (TA = +25°C ± 5°C, VDD = 5.5 V ±10%)
Test
Radiation exposure
Open
Ground
VDD
1, 8, 9, 10, 11, 18,
19, 20, 21, 22
5, 6, 12, 16, 17, 25,
26, 27, 28 1/
2, 3, 4, 7, 13, 14,
15, 23, 24 2/
1/ Pins 12 and 27 have a series resistor of 10 kΩ ± 10% to GND.
2/ Pins 3 and 13 have a series resistor of 10 kΩ ± 10% to VDD.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96696
A
REVISION LEVEL
D
SHEET
12
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein). RHA levels for device classes M, Q and V shall be as specified in MIL-PRF-38535. End-point electrical
parameters shall be as specified in table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019, condition A and as specified herein.
4.4.4.1.1 Accelerated aging testing. Accelerated aging testing shall be performed on all devices requiring a RHA level greater
than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table I herein and shall be the
pre-irradiation end-point electrical parameter limits at 25°C ±5°C. Testing shall be performed at initial qualification and after any
design or process changes which may affect the RHA response of the device.
4.4.4.2 Dose rate induced latchup testing. When required by the customer, dose rate induced latchup testing shall be
performed in accordance with method 1020 of MIL-STD-883 and as specified herein (see 1.5 herein). Tests shall be performed
on devices, SEC, or approved test structures at technology qualification and after any design or process changes which may
effect the RHA capability of the process.
4.4.4.3 Dose rate upset testing. When required by the customer, dose rate upset testing shall be performed in accordance
with method 1023 of MIL-STD-883 and herein (see 1.5 herein).
a.
Transient dose rate upset testing shall be performed at initial qualification and after any design or process changes
which may affect the RHA performance of the devices. Test 10 devices with 0 defects unless otherwise specified.
b.
Transient dose rate upset testing for class Q and V devices shall be performed as specified by a TRB approved
radiation hardness assurance plan and MIL-PRF-38535.
4.4.4.4 Dose rate burnout. When required by the customer, test shall be performed on devices, SEC, or approved test
structures at technology qualifications and after any design or process changes which may effect the RHA capability of the
process. Dose rate burnout shall be performed in accordance with method 1023 of MIL-STD-883 and as specified herein.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96696
A
REVISION LEVEL
D
SHEET
13
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone (614)
692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96696
A
REVISION LEVEL
D
SHEET
14
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96696
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multi-chip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device class V) are reflected in the Part or Identification Number
(PIN). When available, a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN.
A.1.2 PIN. The PIN is as shown in the following example:
5962
F
Federal
stock class
designator
\
RHA
designator
(see A.1.2.1)
96696
01
V
9
X
Device
type
(see A.1.2.2)
Device
class
designator
(see A.1.2.3)
Die
code
Die
details
(see A.1.2.4)
/
\/
Drawing number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die meet the MIL-PRF-38535 specified RHA levels. A dash
(-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
Generic number
HS-9008RH
Circuit function
Radiation hardened CMOS flash 8-bit A/D converter
A.1.2.3 Device class designator.
Device class
Q or V
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
Device requirements documentation
Certification and qualification to the die requirements of MIL-PRF-38535
SIZE
5962-96696
A
REVISION LEVEL
D
SHEET
15
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96696
A.1.2.4 Die details. The die details designation is a unique letter which designates the die's physical dimensions, bonding
pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each product
and variant supplied to this appendix.
A.1.2.4.1 Die physical dimensions.
Die type
Figure number
01
A-1
A.1.2.4.2 Die bonding pad locations and electrical functions.
Die type
Figure number
01
A-1
A.1.2.4.3 Interface materials.
Die type
Figure number
01
A-1
A.1.2.4.4 Assembly related information.
Die type
Figure number
01
A-1
A.1.3 Absolute maximum ratings. See paragraph 1.3 herein for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 herein for details.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96696
A
REVISION LEVEL
D
SHEET
16
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96696
A.2 APPLICABLE DOCUMENTS.
A.2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARD
MIL-STD-883 - Test Method Standard Microcircuits.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or
from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
A.3 REQUIREMENTS
A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein and the manufacturer’s QM plan for device classes Q and V.
A.3.2.1 Die physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figure A-1.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as
specified in A.1.2.4.2 and on figure A-1.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figure A-1.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and on figure A-1.
A.3.2.5 Truth table. The truth table shall be as defined in paragraph 3.2.3 herein.
A.3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as defined in paragraph 3.2.5 herein.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96696
A
REVISION LEVEL
D
SHEET
17
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96696
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table I of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table I.
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed
in A.1.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of
compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the
manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
A.4 VERIFICATION
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not affect the form, fit, or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum, it shall consist of:
a.
Wafer lot acceptance for class V product using the criteria defined in MIL-STD-883, method 5007.
b.
100% wafer probe (see paragraph A.3.4 herein).
c.
100% internal visual inspection to the applicable class Q or V criteria defined in MIL-STD-883, method 2010 or the
alternate procedures allowed in MIL-STD-883, method 5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table II herein. Group E tests and conditions are as specified in paragraphs 4.4.4, 4.4.4.1,
4.4.4.1.1, 4.4.4.2, 4.4.4.3, and 4.4.4.4 herein.
A.5 DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or
as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96696
A
REVISION LEVEL
D
SHEET
18
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96696
A.6 NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications, and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43218-3990 or telephone
(614)-692-0547.
A.6.3 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DSCC-VA and have
agreed to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96696
A
REVISION LEVEL
D
SHEET
19
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96696
FIGURE A-1. Die bonding pad locations and electrical functions.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96696
A
REVISION LEVEL
D
SHEET
20
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96696
Die physical dimensions.
Die size: 4850 microns x 4400 microns
Die thickness: 19 ±1 mils
Interface materials.
Top metallization: Si Al Cu 10.0 kÅ ±1 kÅ
Backside metallization: None: Chemical etch
Glassivation.
Type: PSG
Thickness: 8kÅ ±1 kÅ
Substrate: Single crystal silicon
Assembly related information.
Substrate potential: substrate internally tied to VDD
Special assembly instructions: Intersil double bonds the VDD*, VREF*, and VSS* pins for current sharing
purposes.
FIGURE A-1. Die bonding pad locations and electrical functions – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96696
A
REVISION LEVEL
D
SHEET
21
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 05-03-18
Approved sources of supply for SMD 5962-96696 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962F9669601QXC
3/
HS1-9008RH-8
5962F9669601QYC
3/
HS9-9008RH-8
5962F9669601VXC
3/
HS1-9008RH-Q
5962F9669601V9A
34371
HS0-9008RH-Q
5962F9669601VYC
3/
HS9-9008RH-Q
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ No longer available from an approved source of supply.
Vendor CAGE
number
34371
Vendor name
and address
Intersil Corporation
P.O. Box 883
Melbourne, FL 32902-0883
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.