92316

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
A
Add case outline T. Update boilerplate. Editorial changes throughout.
96-06-05
M. A. Frye
APPROVED
B
Changes in accordance with NOR 5962-R139-98.
98-07-20
Raymond Monnin
C
Dimensional corrections to case outlines Z and U. Updated
boilerplate. - glg
99-10-25
Raymond Monnin
D
Boilerplate update and part of five year review. tcr
06-05-31
Raymond Monnin
E
Update drawing to reflect current MIL-PRF-38535 requirements.
15-03-20
Charles Saffle
REV
SHEET
REV
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E
E
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E
E
E
E
E
E
SHEET
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REV STATUS
REV
E
E
E
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E
OF SHEETS
SHEET
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9
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PMIC N/A
PREPARED BY
Jeff Bowling
STANDARD
MICROCIRCUIT
DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
CHECKED BY
Jeff Bowling
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
Michael A. Frye
DRAWING APPROVAL DATE
95-02-17
REVISION LEVEL
E
MICROCIRCUIT, MEMORY, DIGITAL, CMOS,
1MEG X 1 STATIC RANDOM ACCESS MEMORY
(SRAM) WITH SEPARATE I/O,
MONOLITHIC SILICON
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
5962-92316
1 OF 26
5962-E135-15
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q and M)
and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
92316
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
Q
X
A
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number 1/
01
02
03
04
05
06
07
08
Circuit function
1 MEG X 1 CMOS SRAM
1 MEG X 1 CMOS SRAM
1 MEG X 1 CMOS SRAM
1 MEG X 1 CMOS SRAM
1 MEG X 1 CMOS SRAM
1 MEG X 1 CMOS SRAM
1 MEG X 1 CMOS SRAM
1 MEG X 1 CMOS SRAM
Data retention
Access time
No
No
No
No
Yes
Yes
Yes
Yes
45 ns
35 ns
25 ns
20 ns
45 ns
35 ns
25 ns
20 ns
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Y
Z
U
T
Descriptive designator
See figure 1
See figure 1
See figure 1
See figure 1
See figure 1
Terminals
32
32
32
32
28
Package style
dual-in-line
rectangular leadless chip carrier
flat pack
SOJ package
dual-in-line
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
_____
1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and
will also be listed in MIL-HDBK-103 (see 6.6.2 herein).
STANDARD
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APR 97
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A
REVISION LEVEL
E
SHEET
2
1.3 Absolute maximum ratings. 2/
Voltage on any input relative to VSS -------------------------Voltage applied to Q ---------------------------------------------Storage temperature range -------------------------------------Maximum power dissipation (PD) -----------------------------Lead temperature (soldering, 10 seconds) ----------------Thermal resistance, junction-to-case (ΘJC):
Cases X and T ---------------------------------------------------Case Y ------------------------------------------------------------Cases U and Z ---------------------------------------------------Junction temperature (TJ) ----------------------------------------
-0.5 V dc to +7.0 V dc
-0.5 V dc to +6.0 V dc
-65°C to +150C
1.0 W
+260°C
5°C/W
4°C/W
6°C/W
+150°C 3/
1.4 Recommended operating conditions.
Supply voltage range (VCC) ------------------------------------Supply voltage (VSS) ---------------------------------------------Input high voltage range (VIH) ---------------------------------Input low voltage range (VIL) -----------------------------------Case operating temperature range (TC) ----------------------
4.5 V dc to 5.5 V dc
0V
2.2 V dc to +6.0 V dc
-0.5 V dc to +0.8 V dc 4/
-55°C to +125°C
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
________
2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
4/ VIL minimum = -3.0 V dc for pulse width less than 20 ns.
STANDARD
MICROCIRCUIT DRAWING
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COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
E
SHEET
3
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM Standard F1192
-
Standard Guide for the Measurement of Single Event Phenomena from
Heavy Ion Irradiation of Semiconductor Devices.
(Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor
Drive, West Conshohocken, PA 19428-2959; http://www.astm.org.)
JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JESD 78
-
IC Latch-Up Test.
(Copies of these documents are available online at http://www.jedec.org or from JEDEC – Solid State Technology
Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107.)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute the
documents. These documents also may be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 as specified herein, or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth table. The truth table(s) shall be as specified on figure 3.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
STANDARD
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APR 97
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REVISION LEVEL
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3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of
supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MILPRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of
product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritime’s agent,
and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore
documentation shall be made available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 041 (see MIL-PRF-38535, appendix A).
STANDARD
MICROCIRCUIT DRAWING
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APR 97
SIZE
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A
REVISION LEVEL
E
SHEET
5
TABLE I. Electrical performance characteristics.
Test
Operating supply current
Symbol
ICC1
1/
Standby power supply
ICC2
tAVAV = tAVAV (minimum),
Group A
subgroups
Device
types
Limits
Unit
Min
1, 2, 3
Max
01, 05
115
VCC = 5.5 V, CE = VIL,
02, 06
125
all other inputs at VIL
03, 07
140
04, 08
155
1, 2, 3
All
25
mA
1, 2, 3
All
5
mA
1, 2, 3
05-08
VCC = 2.0 V
1, 2, 3
05-08
1.0
mA
VCC = 3.0 V
1, 2, 3
05-08
1.5
mA
1, 2, 3
All
±10
A
1, 2, 3
All
±10
A
1, 2, 3
All
1, 2, 3
All
0.4
V
4
All
10.0
pF
4
All
12.0
pF
7, 8A, 8B
All
CE > VIH, all other inputs < VIL
mA
or > VIH, VCC = 5.5 V, f = 0
MHz
current TTL 1/
Standby power supply
current CMOS 1/
Conditions
-55C  TC +125C
VCC 4.5 V to 5.5 V
VSS = 0 V
unless otherwise specified
ICC3
CE > (VCC -0.2 V), f = 0 MHz,
VCC = 5.5 V, all other inputs
< 0.2 V or > (VCC - 0.2 V)
Data retention voltage
VDR
CE  VCC - 0.2 V,
2
V
VIN  VCC - 0.2 V or  0.2 V`
Data retention current
Input leakage current,
ICC4
IILK
any input
VCC = 5.5 V,
VIN = 0 V to 5.5 V
Off-state output leakage
IOLK
current
VCC = 5.5 V,
VIN = 0 V to 5.5 V
Output high voltage
VOH
IOUT = -4.0 mA, VCC = 4.5 V,
2.4
V
VIL = 0.8 V, VIH = 2.2 V
Output low voltage
VOL
IOUT = 8.0 mA, VCC = 4.5 V,
VIL = 0.8 V, VIH = 2.2 V
Input capacitance
CIN
VIN = 0 V,
f = 1.0 MHz, TA = +25C,
see 4.4.1e
Output capacitance
COUT
VOUT = 0 V,
f = 1.0 MHz, TA = +25C,
see 4.4.1e
Functional testing
See 4.4.1c
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
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APR 97
SIZE
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A
REVISION LEVEL
E
SHEET
6
TABLE I. Electrical performance characteristics – Continued.
Test
Symbol
Chip enable access time
Read cycle time
Address access time
tELQV
3/
Conditions
-55C  TC +125C
VCC 4.5 V to 5.5 V
VSS = 0 V
unless otherwise specified
See figure 5 2/
Output hold after address
change
Chip enable to output active
5/ 6/
Chip disable to output
inactive 5/ 6/
9,10,11
tAVQV
Device
types
Limits
Min
9,10,11
tAVAV
4/
Group A
subgroups
9,10,11
Unit
Max
01, 05
45
02, 06
35
03, 07
25
04, 08
20
01, 05
45
02, 06
35
03, 07
25
04, 08
20
ns
ns
01, 05
45
02, 06
35
03, 07
25
04, 08
20
ns
tAVQX
9,10,11
All
3.0
ns
tELQX
9,10,11
All
3.0
ns
tEHQZ
9,10,11
01, 05
0
18
02, 06
0
15
03, 07
0
10
04, 08
0
8
0
Chip enable to power up 5/
tELPU
9,10,11
All
Chip enable to power down
5/
tEHPD
9,10,11
01, 05
45
02, 06
35
03, 07
25
04, 08
20
ns
ns
ns
See footnotes at end of table.
STANDARD
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REVISION LEVEL
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SHEET
7
TABLE I. Electrical performance characteristics – Continued.
Test
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Symbol
tAVAV
Conditions
-55C  TC +125C
VCC 4.5 V to 5.5 V
VSS = 0 V
unless otherwise specified
See figure 5 2/
Group A
subgroups
9,10,11
tELEH
9,10,11
tDVWH
Limits
Min
9,10,11
tWLWH
Device
types
9,10,11
01, 05
45
02, 06
35
03, 07
25
04, 08
20
01, 05
25
02, 06
20
03, 07
16
04, 08
15
01, 05
25
02, 06
20
03, 07
16
04, 08
15
01, 02,
05, 06
13
03, 07
10
04, 08
8
Unit
Max
ns
ns
ns
ns
Data hold after end of write
tWHDX
9,10,11
All
0
ns
Address setup to end of
write
tAVWH
9,10,11
01, 05
25
ns
02, 06
20
03, 07
16
04, 08
15
Address setup to beginning
of write
tAVWL
tAVEL
9,10,11
All
0
ns
Address hold after end of
write
tWHAV
9,10,11
All
5.0
ns
See footnotes at end of table.
STANDARD
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REVISION LEVEL
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TABLE I. Electrical performance characteristics – Continued.
Test
Write enable to output
disable 5/ 6/
Output active after end of
write 5/ 6/ 7/
Chip select to data retention
time
5/
Operation recovery time 5/
Symbol
tWLQZ
Conditions
-55C  TC +125C
VCC 4.5 V to 5.5 V
VSS = 0 V
unless otherwise specified
See figure 5 2/
Group A
subgroups
9,10,11
Device
types
Limits
Unit
Min
Max
01, 05
0
15
02, 06
0
13
03, 07
0
11
04, 08
0
10
ns
tWHQX
9,10,11
All
0
ns
tCDR
9,10,11
05-08
0
ns
tR
9,10,11
05-08
tAVAV
ns
1/ ICC is dependent upon output loading and cycle rate. The specified values apply with output(s) unloaded.
2/ AC measurements assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of
0 V to 3.0 V and output loading of 30 pF load capacitance, unless otherwise specified. Output timing reference is 1.5 V.
See igure 4.
3/ For read cycles 1 and 2, WE is high for entire cycle.
4/ Device is continuously selected, CE low.
5/ Parameter if not tested, shall be guaranteed to the limits specified in table I.
6/ Measured ±500 mV from steady-state output voltage. Load capacitance is 5.0 pF.
7/ If WE is low when CE goes low, the output remains in the high impedance state.
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REVISION LEVEL
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Case X (see notes)
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
2.26
2.82
.089
.111
b
0.41
0.51
.016
.020
b1
1.14
1.40
.045
.055
c
0.20
0.30
.008
.012
D
40.26
41.02
1.585
1.615
E
9.78
10.29
.385
.405
E1
9.91
10.41
.390
.410
e
2.54 BSC
.100 BSC
L
3.18
4.45
.125
.175
Q
1.02
1.52
.040
.060
α
0°
15°
-------
-------
N
32
-------
NOTES: 1. Either configuration in detail A is allowed.
2. The U.S. Government preferred system of measurement is the metric SI system. However, since this item was
originally designed using inch-pound units of measurement, in the event of conflict between the metric and
inch-pound units, the inch-pound units shall take precedence.
FIGURE 1. Case outlines - continued.
STANDARD
MICROCIRCUIT DRAWING
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REVISION LEVEL
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SHEET
10
Case Y (see note)
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
2.03
2.54
.080
.100
b
0.56
0.71
.022
.028
b1
0.10 R
0.36 R
.004 R
.014 R
b2
1.37
1.68
.054
.066
D
20.70
21.21
.815
.835
D1
18.80
19.30
.740
.760
E
9.96
10.36
.392
.408
e
1.27 BSC
.050 BSC
L
1.78
2.03
.070
.080
L1
2.29
2.79
.090
.110
N
32
-----
NOTE: The U.S. Government preferred system of measurement is the metric SI system. However, since this item was
originally designed using inch-pound units of measurement, in the event of conflict between the metric and
inch-pound units, the inch-pound units shall take precedence.
FIGURE 1. Case outlines - continued.
STANDARD
MICROCIRCUIT DRAWING
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REVISION LEVEL
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Case Z (see note)
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
2.46
2.97
.097
.117
b
0.38
0.48
.015
.019
c
0.10
0.15
.004
.006
D
20.62
21.03
.812
.828
D1
18.92
19.18
.745
.755
E
8.23
8.53
.324
.336
E1
10.29
10.54
.405
.415
e
1.27 BSC
.050 BSC
L
7.37
9.4
.290
.370
Q
0.66
------
.026
-----
N
32
------
Note: The U.S. Government preferred system of measurement is the metric SI system. However, since this item was
originally designed using inch-pound units of measurement, in the event of conflict between the metric and
inch-pound units, the inch-pound units shall take precedence.
FIGURE 1. Case outlines - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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DSCC FORM 2234
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REVISION LEVEL
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Case U (see note)
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
3.43
3.89
.135
.153
A2
0.66
0.91
.026
.036
b
0.38
0.48
.015
.019
R
0.76
1.02
.030
.040
D
20.62
21.03
.812
.828
D1
18.80
19.18
.740
.755
E
10.29
10.54
.405
.415
E1
11.05
11.30
.435
.445
E2
9.14
9.85
.360
.380
e
1.27 BSC
.050 BSC
N
32
-------
NOTE: The U.S. Government preferred system of measurement is the metric SI system. However, since this item was
originally designed using inch-pound units of measurement, in the event of conflict between the metric and
inch-pound units, the inch-pound units shall take precedence.
FIGURE 1. Case outlines - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92316
A
REVISION LEVEL
E
SHEET
13
Case T (see notes)
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
2.26
2.82
.089
.111
b
0.41
0.51
.016
.020
b1
1.01
1.52
.040
.060
c
0.20
0.30
.008
.012
D
35.20
35.92
1.386
1.414
E
9.78
10.29
.385
.405
E1
9.91
10.41
.390
.410
e
2.54 BSC
L
3.18
4.45
.125
.175
Q
1.02
1.52
.040
.060
α
0°
15°
------
-------
N
NOTES:
.100 BSC
28
1. Either configuration in detail A is allowed.
2. The U.S. Government preferred system of measurement is the metric SI system. However, since this item was
originally designed using inch-pound units of measurement, in the event of conflict between the metric and
inch-pound units, the inch-pound units shall take precedence.
FIGURE 1. Case outlines - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92316
A
REVISION LEVEL
E
SHEET
14
Device types
Case outlines
Terminal Number
All
X, Y, Z, U
T
Terminal Symbol
1
A
A
2
A
A
3
A
A
4
NC
A
5
A
A
6
A
A
7
A
NC
8
NC
A
9
A
A
10
A
A
11
A
A
12
A
Q
13
NC
14
Q
WE
VSS
15
WE
VSS
CE
D
A
21
CE
D
A
A
NC
NC
22
A
A
23
NC
A
24
A
A
25
A
A
26
A
A
27
A
A
28
A
VCC
29
A
-----
30
A
-----
31
NC
-----
32
VCC
-----
16
17
18
19
20
A
A
A
NC = No Connection
Figure 2. Terminal Connections.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92316
A
REVISION LEVEL
E
SHEET
15
CE
WE
Mode
I/O
Power
H
X
Not selected
High Z
L
L
Write
DIN
Active
L
H
Read
DOUT
Active
Standby
H = Logic “1” state
L = Logic “0” state
X = Don’t care
FIGURE 3. Truth table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92316
A
REVISION LEVEL
E
SHEET
16
NOTES:
1.
2.
3.
Use these output load circuits or equivalent for testing.
Including scope and jig.
Minimum of 5 pF for tELQZ. tEHQZ, tWLQZ, and tWHQX.
AC test conditions
Input pulse levels
GND to 3.0 V
Input rise, fall times
5 ns
Input timing reference levels
1.5 V
Output reference levels
1.5 V
FIGURE 4. Output load circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92316
A
REVISION LEVEL
E
SHEET
17
NOTES:
1. WE is high for entire cycle.
2. CE and WE must transition between VIH (min) to VIL (max) or VIL (max) to VIH (min) in monotonic fashion.
3. Device is continuously selected, CE low.
FIGURE 5. Timing waveforms.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92316
A
REVISION LEVEL
E
SHEET
18
NOTES:
1. CE and WE must transition between VIH (min) to VIL (max) or VIL (max) to VIH (min) in monotonic fashion.
2. CE and WE must be > VIH during address transitions.
FIGURE 5. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92316
A
REVISION LEVEL
E
SHEET
19
FIGURE 5. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92316
A
REVISION LEVEL
E
SHEET
20
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Delete the sequence specified as initial (preborn-in) electrical parameters through interim (postburn-in)
electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.
b.
The test circuit shall be maintained by the manufacturer under document revision level control and shall be made
available to the preparing or acquiring activity upon request. For device class M, the test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015.
(1) Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein).
c.
Interim and final electrical parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections, and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92316
A
REVISION LEVEL
E
SHEET
21
TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7
Line
no.
Test
requirements
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
Subgroups
(per MIL-PRF-38535,
table III)
Device
class Q
Device
class V
1, 7, 9
Not Required
Not Required
Required
Required
1*, 7* 
Required
1
Interim electrical
parameters (see 4.2)
2
Static burn-in I and
II (method 1015)
3
4
Same as line 1
Dynamic burn-in
(method 1015)
5
Same as line 1
6
Final electrical
parameters
1*, 2, 3, 7*,
8A, 8B, 9, 10, 11
1*, 2, 3, 7*,
8A, 8B, 9, 10, 11
1*, 7* 
1*, 2, 3, 7*,
8A, 8B, 9, 10, 11
7
Group A test
requirements
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
8
Group C end-point
electrical parameters
2, 3, 7, 8A, 8B
1, 2, 3, 7, 8A, 8B
9
Group D end-point
electrical parameters
2, 3, 8A, 8B
2, 3, 8A, 8B
1, 2, 3, 7,
8A, 8B, 9,
10, 11 
2, 3, 8A, 8B
10
Group E end-point
electrical parameters
1, 7, 9
1, 7, 9
1, 7, 9
Required
1/
2/
3/
4/
5/
6/
Blank spaces indicate tests are not applicable.
Any or all subgroups may be combined when using high-speed testers.
Subgroups 7 and 8 functional tests shall verify the truth table.
* indicates PDA applies to subgroup 1 and 7.
** see 4.4.1e.
Δ indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be computed
with reference to the previous interim electrical parameters (see line 1).
7/ See 4.4.1d
TABLE IIB. Delta limits at +25°C.
Parameter 1/
Device types
All
ICC3 standby
± 10 %
IILK, IOLK
± 10 %
1/ The above parameter shall be recorded
before and after the required burn-in and
life tests to determine the delta.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92316
A
REVISION LEVEL
E
SHEET
22
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
c.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V,
subgroups 7 and 8 shall include verifying the functionality of the device. These tests shall have been fault graded in
accordance with MIL-STD-883, method 5012 (see 1.5 herein).
d.
O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may
affect the performance of the device. For device class M, procedures and circuits shall be maintained under document
revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity
upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device
manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or
acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be
considered destructive. Information contained in JESD 78 may be used for reference.
e.
Subgroup 4 (CIN and COUT measurements) shall be measured only for initial qualification and after any process or
design changes which may affect input or output capacitance. Capacitance shall be measured between the
designated terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all input and
output terminals tested.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
Delta limits shall apply only to subgroup 1 of group C inspection and shall consist of tests specified in table IIB herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and
shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MILSTD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MILSTD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C 5°C,
after exposure, to the subgroups specified in table IIA herein.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92316
A
REVISION LEVEL
E
SHEET
23
4.5 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded
before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical
parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option,
either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7, and
9.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and
this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0540.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in
MIL-HDBK-103 and QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein)
to DLA Land and Maritime-VA and have agreed to this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DLA Land and Maritime-VA.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92316
A
REVISION LEVEL
E
SHEET
24
APPENDIX A
Appendix A forms a part of SMD 5962-92316
FUNCTIONAL ALGORITHMS
A.1 SCOPE
A.1.1 Scope. Functional algorithms are test patterns which define the exact sequence of events used to verify proper
operation of a random access memory (RAM). Each algorithm serves a specific purpose for the testing of the device. It is
understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of each
manufacturer to guarantee that the test patterns described herein are followed as closely as possible, or equivalent patterns be
used that serve the same purpose. Each manufacturer should demonstrate that this condition will be met. Algorithms shall be
applied to the device in a topologically pure fashion. This appendix is a mandatory part of the specification. The information
contained herein is intended for compliance.
A.2 APPLICABLE DOCUMENTS. This section is not applicable to this appendix.
A.3 ALGORITHMS
A.3.1 Algorithm A (pattern 1).
A.3.1.1 Checkerboard, checkerboard-bar.
Step 1.
Step 2.
Step 3.
Step 4.
Load memory with a checkerboard data pattern by incrementing from location 0 to maximum.
Read memory, verifying the output checkerboard pattern by incrementing from location 0 to maximum.
Load memory with a checkerboard-bar pattern by incrementing from location 0 to maximum.
Read memory, verifying the output checkerboard-bar pattern by incrementing from location 0 to maximum.
A.3.2 Algorithm B (pattern 2).
A.3.2.1 March.
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.
Step 7.
Step 8.
Step 9.
Step 10.
Step 11.
Step 12.
Step 13.
Step 14.
Step 15.
Step 16.
Step 17.
Step 18.
Load memory with background data, incrementing from minimum to maximum address locations (all "0's").
Read data in location 0.
Write complement data to location 0.
Read complement data in location 0.
Repeat steps 2 through 4 incrementing X-fast sequentially for each location in the array.
Read complement data in maximum address location.
Write data to maximum address location.
Read data in maximum address location.
Repeat steps 6 through 8 decrementing X-fast sequentially for each location in the array.
Read data in location 0.
Write complement data to location 0.
Read complement data in location 0.
Repeat steps 10 through 12 decrementing X-fast sequentially for each location in the array.
Read complement data in maximum address location.
Write data to maximum address location.
Read data in maximum address location.
Repeat steps 14 through 16 incrementing X-fast sequentially for each location in the array.
Read background data from memory, decrementing X-fast from maximum to minimum address locations.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92316
A
REVISION LEVEL
E
SHEET
25
APPENDIX A – Continued.
Appendix A forms a part of SMD 5962-92316
FUNCTIONAL ALGORITHMS
A.3.3 Algorithm C (pattern 3).
A.3.3.1 XY March.
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.
Step 7.
Step 8.
Step 9.
Step 10.
Step 11.
Step 12.
Step 13.
Step 14.
Step 15.
Step 16.
Step 17.
Step 18.
Load memory with background data, incrementing from minimum to maximum address locations (all "0's").
Read data in location 0.
Write complement data to location 0.
Read complement data in location 0.
Repeat steps 2 through 4 incrementing Y-fast sequentially for each location in the array.
Read complement data in maximum address location.
Write data to maximum address location.
Read data in maximum address location.
Repeat steps 6 through 8 decrementing X-fast sequentially for each location in the array.
Read data in location 0.
Write complement data to location 0.
Read complement data in location 0.
Repeat steps 10 through 12 decrementing Y-fast sequentially for each location in the array.
Read complement data in maximum address location.
Write data to maximum address location.
Read data in maximum address location.
Repeat steps 14 through 16 incrementing X-fast sequentially for each location in the array.
Read background data from memory, decrementing Y-fast from maximum to minimum address locations.
A.3.4 Algorithm D (pattern 4).
A.3.4.1 CEDES - CE deselect checkerboard, checkerboard-bar.
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.
Load memory with a checkerboard data pattern by incrementing from location 0 to maximum.
Deselect device, attempt to load memory with checkerboard-bar data pattern by incrementing from location 0 to
maximum.
Read memory, verifying the output checkerboard pattern by incrementing from location 0 to maximum.
Load memory with a checkerboard-bar pattern by incrementing from location 0 to maximum.
Deselect device, attempt to load memory with checkerboard data pattern by incrementing from location 0 to
maximum.
Read memory, verifying the output checkerboard-bar pattern by incrementing from location 0 to maximum.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-92316
A
REVISION LEVEL
E
SHEET
26
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 15-03-20
Approved sources of supply for SMD 5962-92316 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
5962-9231601MTA
3/
5962-9231601MUA
57300
5962-9231601MXA
3/
MT5C1001C-45/883C
5962-9231601MYA
3/
MT5C1001EC-45/883C
5962-9231601MZA
57300
MT5C1001F-45/883C
5962-9231602MTA
3/
MT5C1001C-35/883C
5962-9231602MUA
57300
5962-9231602MXA
3/
MT5C1001C-35/883C
5962-9231602MYA
3/
MT5C1001EC-35/883C
5962-9231602MZA
57300
MT5C1001F-35/883C
5962-9231603MTA
3/
MT5C1001C-25/883C
5962-9231603MUA
57300
5962-9231603MXA
3/
MT5C1001C-25/883C
5962-9231603MYA
3/
MT5C1001EC-25/883C
5962-9231603MZA
57300
MT5C1001F-25/883C
5962-9231604MTA
3/
MT5C1001C-20/883C
5962-9231604MUA
57300
5962-9231604MXA
3/
MT5C1001C-20/883C
5962-9231604MYA
3/
MT5C1001EC-20/883C
5962-9231604MZA
57300
5962-9231605MTA
3/
5962-9231605MUA
57300
5962-9231605MXA
3/
MT5C1001C-45L/883C
5962-9231605MYA
3/
MT5C1001EC-45L/883C
5962-9231605MZA
57300
1 of 2
Vendor
similar
PIN 2/
MT5C1001C-45/883C
MT5C1001DCJ-45/883C
MT5C1001DCJ-35/883C
MT5C1001DCJ-25/883C
MT5C1001DCJ-20/883C
MT5C1001F-20/883C
MT5C1001C-45L/883C
MT5C1001DCJ-45L/883C
MT5C1001F-45L/883C
STANDARD MICROCIRCUIT DRAWING BULLETIN – Continued.
DATE: 15-03-20
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9231606MTA
3/
5962-9231606MUA
57300
5962-9231606MXA
3/
MT5C1001C-35L/883C
5962-9231606MYA
3/
MT5C1001EC-35L/883C
5962-9231606MZA
57300
MT5C1001F-35L/883C
5962-9231607MTA
3/
MT5C1001C-25L/883C
5962-9231607MUA
57300
5962-9231607MXA
3/
MT5C1001C-25L/883C
5962-9231607MYA
3/
MT5C1001EC-25L/883C
5962-9231607MZA
57300
MT5C1001F-25L/883C
5962-9231608MTA
3/
MT5C1001C-20L/883C
5962-9231608MUA
57300
5962-9231608MXA
3/
MT5C1001C-20L/883C
5962-9231608MYA
3/
MT5C1001EC-20L/883C
5962-9231608MZA
57300
MT5C1001C-35L/883C
MT5C1001DCJ-35L/883C
MT5C1001DCJ-25L/883C
MT5C1001DCJ-20L/883C
MT5C1001F-20L/883C
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
The last known source is listed below.
Vendor CAGE
number
Vendor name
and address
57300
Micross Components
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
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