CD4094BMS CMOS 8-Stage Shift-and-Store Bus Register December 1992 Features Pinout • High Voltage Type (20V Rating) CD4094BMS TOP VIEW • 3-State Parallel Outputs for Connection to Common Bus • Separate Serial Outputs Synchronous to Both Positive and Negative Clock Edges for Cascading 16 VDD STROBE 1 • Medium Speed Operation - 5MHz at 10V (typ) 15 OUTPUT ENABLE DATA 2 • Standardized Symmetrical Output Characteristics CLOCK 3 14 Q5 • 100% Tested for Quiescent Current at 20V Q1 4 13 Q6 • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC Q2 5 12 Q7 Q3 6 11 Q8 Q4 7 10 Q’S VSS 8 9 QS • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Functional Diagram Applications • Serial-to-Parallel Data Conversion • Remote Control Holding Register DATA 2 CLOCK 3 STROBE 1 OUTPUT ENABLE 15 • Dual-Rank Shift, Hold, and Bus Applications SERIAL OUTPUTS 10 Q’S 8-STAGE SHIFT REGISTER 9 QS Description CD4094BMS is a 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the STROBE input is high. Data in the storage register appears at the outputs whenever the OUTPUT-ENABLE signal is high. Two serial outputs are available for cascading a number of CD4094BMS devices. Data is available at the QS serial output terminal on positive clock edges to allow for high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information, available at the Q’S terminal on the next negative clock edge, provides a means for cascading CD4094BMS devices when the clock rise time is slow. 8-BIT STORAGE REGISTER 3-STATE OUTPUTS VDD = 16 VSS = 8 PARALLEL OUTPUTS Q1 - Q8 (TERMINALS 4, 5, 6, 7, 14, 13, 12, 11, RESPECTIVELY) The CD4094BMS is supplied in these 16 lead outline packages: Braze Seal DIP H4X Frit Seal DIP H1F Ceramic Flatpack H6W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1083 File Number 3194 Specifications CD4094BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Current Input Leakage Current SYMBOL IDD IIL IIH CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125 C - 1000 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA VIN = VDD or GND 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA - 50 mV VIN = VDD or GND VDD = 20 VDD = 18V o Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Functional F VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V Tri-State Output Leakage IOZL VIN = VDD or GND VOUT = 0V 1 +25oC -0.4 - µA Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V 2 +125oC -12 - µA VDD = 18V 3 -55oC -0.4 - µA VDD = 20V 1 +25oC - 0.4 µA 2 +125oC - 12 µA 3 -55oC - 0.4 µA VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1084 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4094BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Propagation Delay Clock to Serial Output QS TPHL1 TPLH1 GROUP A SUBGROUPS TEMPERATURE CONDITIONS VDD = 5V, VIN = VDD or GND (Note 1, 2) Propagation Delay Clock to Serial Output Q’S TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND (Note 1, 2) Propagation Delay Clock to Parallel Output TPHL3 TPLH3 VDD = 5V, VIN = VDD or GND (Note 1, 2) Propagation Delay Strobe to Parallel Output TPHL4 TPLH4 VDD = 5V, VIN = VDD or GND (Note 1, 2) Propagation Delay Output Enable to Parallel Output TPHZ TPZH VDD = 5V, VIN = VDD or GND (Note 2, 3) Propagation Delay Output Enable to Parallel Output TPLZ TPZL VDD = 5V, VIN = VDD or GND (Note 2, 3) Transition Time TTHL TTLH VDD = 5V, VIN = VDD or GND (Note 1, 2) Maximum Clock Input Frequency FCL VDD = 5V, VIN = VDD or GND (Note 1, 2) 9 10, 11 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 600 ns - 810 ns - 460 ns - 621 ns 9 +25oC - 840 ns 10, 11 +125oC, -55oC - 1134 ns 9 +25oC - 580 ns - 783 ns 10, 11 o o +125 C, -55 C o 9 +25 C - 280 ns 10, 11 +125oC, -55oC - 378 ns 9 +25oC - 200 ns - 270 ns - 200 ns 10, 11 9 10, 11 +125oC, -55oC +25oC +125oC, -55oC - 270 ns 9 +25oC 1.25 - MHz 10, 11 +125oC, -55oC .93 - MHz MIN MAX UNITS µA NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC - 5 +125oC - 150 µA -55oC, +25oC - 10 µA +125oC - 300 µA - 10 µA +125oC - 600 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 7-1085 1, 2 +125oC 0.9 - mA -55oC 1.6 - mA Specifications CD4094BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Sink) SYMBOL IOL15 CONDITIONS VDD = 15V, VOUT = 1.5V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC 2.4 - mA o Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 -55 C 4.2 - mA +125oC - -0.36 mA - -0.64 mA -55 Output Current (Source) Output Current (Source) IOH5B IOH10 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 oC +125oC - -1.1 mA -55oC - -2.0 mA +125oC - -0.9 mA - -2.6 mA - -2.4 mA -55o Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 C +125oC oC - - mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC 7 - V VDD = 10V 1, 2, 3 +25oC - 250 ns VDD = 15V 1, 2, 3 +25oC - 190 ns 1, 2, 3 +25oC - 220 ns oC - 150 ns - 390 ns 1, 2, 3 o +25 C - 270 ns VDD = 10V 1, 2, 3 +25 oC - 290 ns VDD = 15V 1, 2, 3 +25oC - 200 ns 1, 2, 4 +25 oC - 120 ns - 90 ns -55 Propagation Delay Clock to Serial Output Qs TPHL1 TPLH1 Propagation Delay Clock to Serial Output Q’s TPHL2 TPLH2 VDD = 10V VDD = 15V 1, 2, 3 +25 Propagation Delay Clock to Parallel Output TPHL3 TPLH3 VDD = 10V 1, 2, 3 +25oC Propagation Delay Strobe to Parallel Output TPHL4 TPLH4 VDD = 15V Propagation Delay Output Enable to Parallel Output TPHZ TPZH VDD = 10V VDD = 15V 1, 2, 4 +25oC Propagation Delay Output Enable to Parallel Output TPLZ TPZL VDD = 10V 1, 2, 4 +25oC - 100 ns VDD = 15V 1, 2, 4 +25oC - 80 ns Transition Time TTLH TTHL VDD = 10V 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25 oC - 80 ns VDD = 10V 1, 2, 3 +25oC 2.5 - MHz VDD = 15V 1, 2, 3 +25oC 3 - MHz 1, 2, 3 +25oC - 125 ns VDD = 10V 1, 2, 3 +25oC - 55 ns VDD = 15V 1, 2, 3 +25oC - 35 ns VDD = 5V 1, 2, 3, 5 +25oC - 15 µs VDD = 10V 1, 2, 3, 5 +25oC - 5 µs 1, 2, 3, 5 +25oC - 5 µs VDD = 5V 1, 2, 3 +25oC - 200 ns VDD = 10V 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 83 ns Maximum Clock Input Frequency Minimum Data Setup Time Maximum Clock Input Rise and Fall Time FCL TS TRCL TFCL VDD = 15V VDD = 5V VDD = 15V Minimum Clock Pulse Width TW VDD = 15V 7-1086 Specifications CD4094BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Minimum Strobe Pulse Width Input Capacitance SYMBOL TW CONDITIONS VDD = 5V CIN NOTES TEMPERATURE MIN MAX UNITS 1, 2, 3 +25oC - 200 ns o VDD = 10V 1, 2, 3 +25 C - 80 ns VDD = 15V 1, 2, 3 +25oC - 70 ns oC - 7.5 pF Any Input 1, 2 +25 NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. 5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) MIL-STD-883 METHOD GROUP A SUBGROUPS 100% 5004 1, 7, 9 7-1087 READ AND RECORD IDD, IOL5, IOH5A Specifications CD4094BMS TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B IDD, IOL5, IOH5A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 (Note 1) 4 - 7, 9 - 14 1 - 3, 8, 15 16 Static Burn-In 2 (Note 1) 4 - 7, 9 - 14 8 1 - 3, 15, 16 Dynamic BurnIn (Note 1) - 8 1, 15, 16 4 - 7, 9 - 14 8 1 - 3, 15, 16 Irradiation (Note 2) 9V ± -0.5V 50kHz 25kHz 4 - 7, 9 - 14 3 2 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-1088 CD4094BMS SERIAL IN CL p SERIAL OUT * D 2 CL CL Q D CL CL 1 Q D CL CL 2 Q 10 n Q’S 8 Q CL CL p p n CLOCK TR * CL 3 STAGES 3-7 CL SERIAL OUT p CL STROBE n TR TR 9 n * QS TR TR 1 TR OUTPUT ENABLE TR TR LATCH 2 TR LATCH 1 TR LATCH 8 * VDD * 15 3-STATE 1 3STATE 2 p 3STATE 8 n VDD VSS * ALL INPUTS PROTECTED BY CMOS PROTECTION NETWORK VSS 4 5 Q1 Q2 14 13 12 11 Q3 Q4 Q5 Q6 Q7 6 7 Q8 FIGURE 1. LOGIC DIAGRAM TRUTH TABLE CL∆ PARALLEL OUTPUTS SERIAL OUTPUTS OUTPUT ENABLE STROBE DATA Q1 QN QS* Q’S 0 X X OC OC Q7 NC 0 X X OC OC NC Q7 1 0 X NC NC Q7 NC 1 1 0 0 QN-1 Q7 NC 1 1 1 1 QN-1 Q7 NC 1 1 1 NC NC NC Q7 ∆ = Level Change Logic 1 = High X = Don’t Care Logic 0 = Low NC = No Change OC = Open Circuit * At the positive clock edge information in the 7th shift register stage is transferred to the 8th register stage and the QS output 7-1089 CD4094BMS AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT TRANSFER CHARACTERISTICS FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V -30 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC 0 -5 -10V PROPAGATION DELAY TIME (tPHL, tPLH) (ns) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) SUPPLY VOLTAGE (VDD) = 5V 300 10V 15V 20 -15 FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 400 0 -10 -15V AMBIENT TEMPERATURE (TA) = +25oC 100 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 200 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 300 AMBIENT TEMPERATURE (TA) = +25oC 250 SUPPLY VOLTAGE (VDD) = 5V 200 150 10V 100 15V 50 0 FIGURE 6. CLOCK-TO-SERIAL OUTPUT QS PROPAGATION DELAY vs CL 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. CLOCK-TO-SERIAL OUTPUT Q’S PROPAGATION DELAY vs CL 7-1090 CD4094BMS (Continued) 600 PROPAGATION DELAY TIME (tPHL, tPLH) (ns) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC 500 SUPPLY VOLTAGE (VDD) = 5V 400 300 10V 200 15V 100 0 20 SUPPLY VOLTAGE (VDD) = 5V 300 200 10V 100 15V 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 9. STROBE-TO-PARALLEL OUTPUT PROPAGATION DELAY vs CL 300 AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC tPHL 250 tPLH TRANSITION TIME (tTHL, tTLH) (ns) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) 400 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 8. CLOCK-TO-PARALLEL OUTPUT PROPAGATION DELAY vs CL SUPPLY VOLTAGE (VDD) = 5V 200 10V 5V 10V 15V 15V 150 100 50 0 20 150 SUPPLY VOLTAGE (VDD) = 5V 100 10V 5V 50 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) POWER DISSIPATION /PACKAGE (PD) (µW) FIGURE 11. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE +25oC AMBIENT TEMPERATURE (TA) = LOAD CAPACITANCE (CL) = 50PF 15 200 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 10. OUTPUT ENABLE-TO-PARALLEL OUTPUT PROPAGATION DELAY vs CL MAXIMUM CLOCK FREQUENCY (fCL MAX) (MHz) AMBIENT TEMPERATURE (TA) = +25oC 10 5 AMBIENT TEMPERATURE (TA) = +25oC ALTERNATING 0 AND 1 PATTERN OUTPUT ENABLE HIGH STROBE HIGH EVERY 8 CLOCK PULSES 106 105 SUPPLY VOLTAGE (VDD) = 15V 104 10V 103 10V 5V 102 CL = 50pF CL = 15pF 10 0 5 10 15 SUPPLY VOLTAGE (VDD) (V) 1 20 FIGURE 12. TYPICAL MAXIMUM-CLOCK-FREQUENCY vs SUPPLY VOLTAGE 10 102 103 104 105 INPUT FREQUENCY (fI) (kHz) FIGURE 13. DYNAMIC POWER DISSIPATION vs INPUT CLOCK FREQUENCY 7-1091 CD4094BMS CLOCK DATA IN STROBE OUTPUT ENABLE INTERNAL Q1 3 - STATE 3 STATE OUTPUT Q1 INTERNAL Q7 3 - STATE 3 STATE OUTPUT Q7 SERIAL QS OUTPUT SERIAL Q’S OUTPUT FIGURE 14. TIMING DIAGRAM DIGITALLY CONTROLLED EQUIPMENT (REQUIRES CONTINUOUS DIGITAL CONTROL) D CD4094BMS STROBE CLOCK DIGITALLY CONTROLLED EQUIPMENT Q’S D CD4094BMS STROBE DIGITALLY CONTROLLED EQUIPMENT QS CLOCK CONTROL AND SYNC CIRCUITRY DATA CLOCK FROM REMOTE CONTROL PANEL FIGURE 15. REMOTE CONTROL HOLDING REGISTER 7-1092 D CD4094BMS STROBE CLOCK CD4094BMS Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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