HM-65642 ® 8K x 8 Asynchronous CMOS Static RAM May 2002 Features Description • Full CMOS Design The HM-65642 is a CMOS 8192 x 8-bit Static Random Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide standard, which allows easy memory board layouts which accommodate a variety of industry standard ROM, PROM, EPROM, EEPROM and RAMs. The HM-65642 is ideally suited for use in microprocessor based systems. In particular, interfacing with the Intersil 80C86 and 80C88 microprocessors is simplified by the convenient output enable (G) input. • Six Transistor Memory Cell • Low Standby Supply Current . . . . . . . . . . . . . . . . 100µA • Low Operating Supply Current. . . . . . . . . . . . . . . 20mA • Fast Address Access Time . . . . . . . . . . . . . . . . . . 150ns • Low Data Retention Supply Voltage . . . . . . . . . . . 2.0V • CMOS/TTL Compatible Inputs/Outputs • JEDEC Approved Pinout The HM-65642 is a full CMOS RAM which utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temperature range. • Equal Cycle and Access Times • No Clocks or Strobes Required • Gated Inputs • No Pull-Up or Pull-Down Resistors Required • Easy Microprocessor Interfacing • Dual Chip Enable Control Ordering Information TEMPERATURE RANGE (NOTE 1) 150ns/75µA CERDIP -40oC to +85oC - JAN# -55oC to +125oC PACKAGE (NOTE 1) 150ns/150µA (NOTE 1) 200ns/250µA HM1-65642-9 29205BXA - PKG. NO. - F28.6 - F28.6 NOTE: 1. Access Time/Data Retention Supply Current. Pinout HM-65642 (CERDIP) TOP VIEW NC 1 28 VCC A12 2 27 W A7 3 26 E2 A6 4 25 A8 A5 5 24 A9 A4 6 A3 7 A2 8 A1 9 20 E1 A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 GND 14 15 DQ3 PIN A DESCRIPTION Address Input DQ Data Input/Output E1 Chip Enable 23 A11 E2 Chip Enable 22 G W Write Enable 21 A10 G Output Enable NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 No Connections GND Ground VCC Power FN3005.2 HM-65642 Functional Diagram A9 A12 A7 A6 A5 A4 A 8 A ROW DECODER ROW ADDRESS BUFFERS A8 256 256 x 256 MEMORY ARRAY 8 A3 256 COLUMN ADDRESS BUFFERS A2 A1 A0 A10 A11 A 5 COLUMN SELECT (8 OF 256) A 5 8 W G E1 8 E2 DQ 1 OF 8 TRUTH TABLE MODE E1 E2 W G Standby (CMOS) X GND X X VIH X X X X VIL X X Enable (High Z) VIL VIH VIH VIH Write VIL VIH VIL X Read VIL VIH VIH VIL Standby (TTL) 2 HM-65642 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage Applied for All Grades . . . . . . GND -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . . . 5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 θJC Thermal Resistance (Typical) θJA CERDIP Package . . . . . . . . . . . . . . . . 45oC/W 8oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101,000 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-65642-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC DC Electrical Specifications Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . +2.2V to VCC +0.3V VCC = 5V ±10%; TA = -40oC to +85oC (HM-65642-9) LIMITS SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS ICCSB1 Standby Supply Current (CMOS) - 250 µA E2 = GND, VCC = 5.5V ICCSB2 Standby Supply Current (TTL) - 5 mA E2 = 0.8V or E1 = 2.2V, VCC = 5.5V ICCDR Data Retention Supply Current - 150 µA E2 = GND, VCC = 2.0V ICCEN Enabled Supply Current - 5 mA E2 = 2.2V, E1 = 0.8V, VCC = 5.5V, IIO = 0mA ICCOP Operating Supply Current (Note 1) - 20 mA f = 1MHz, E1 = 0.8V, E2 = 2.2V, VCC = 5.5V, IIO = 0mA Input Leakage Current -1.0 +1.0 µA VI = VCC or GND, VCC = 5.5V IIOZ Input/Output Leakage Current -1.0 +1.0 µA E2 = GND, VIO = VCC or GND, VCC = 5.5V VCCDR Data Retention Supply Voltage 2.0 - V VOH1 Output High Voltage 2.4 - V IOH = -1.0mA, VCC = 4.5V VOH2 Output High Voltage (Note 2) VCC -0.4 - V IOH = -100µA, VCC = 4.5V - 0.4 V IOL = 4.0mA, VCC = 4.5V II VOL Output Low Voltage Capacitance SYMBOL CI CIO TA = +25oC PARAMETER MAX UNITS Input Capacitance (Note 2) 12 pF Input/Output Capacitance (Note 2) 14 pF NOTES: 1. Typical derating 5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes. 3 TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND HM-65642 AC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-65642-9) LIMITS SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS 150 - ns (Notes 1, 3) - 150 ns (Notes 1, 3) READ CYCLE (1) TAVAX Read Cycle Time (2) TAVQV Address Access Time (3) TE1LQV Chip Enable Access Time E1 - 150 ns (Notes 2, 3) (4) TE2HQV Chip Enable Access Time E2 - 150 ns (Notes 1, 3) (5) TGLQV Output Enable Access Time - 70 ns (Notes 1, 3) (6) TE1LQX Chip Enable Valid to Output On E1 10 - ns (Notes 2, 3) (7) TE2HQX Chip Enable Valid to Output On E2 10 - ns (Notes 2, 3) (8) TGLQX Output Enable Valid to Output On 5 - ns (Notes 2, 3) (9) TE1HQZ Chip Enable Not Valid to Output Off E1 - 50 ns (Notes 2, 3) (10) TE2LQZ Chip Enable Not Valid to Output Off E2 - 60 ns (Notes 2, 3) (11) TGHQZ Output Enable Not Valid to Output Off - 50 ns (Notes 2, 3) (12) TAXQX Output Hold From Address Change 10 - ns (Notes 2, 3) (13) TAVAX Write Cycle Time 150 - ns (Notes 1, 3) (14) TWLWH Write Pulse Width 90 - ns (Notes 1, 3) (15) TE1LE1H Chip Enable to End of Write E1 90 - ns (Notes 1, 3) (16) TE2HE2L Chip Enable to End of Write E2 90 - ns (Notes 1, 3) (17) TAVWL Address Setup Time Late Write 0 - ns (Notes 1, 3) (18) TAVE1L Address Setup Time Early Write E1 0 - ns (Notes 1, 3) (19) TAVE2H Address Setup Time Early Write E2 0 - ns (Notes 1, 3) (20) TWHAX Write Recovery Time Late Write 10 - ns (Notes 1, 3) (21) TE1HAX Write Recovery Time Early Write E1 10 - ns (Notes 1, 3) (22) TE2LAX Write Recovery Time Early Write E2 10 - ns (Notes 1, 3) (23) TDVWH Data Setup Time Late Write 60 - ns (Notes 1, 3) (24) TDVE1H Data Setup Time Early Write E1 60 - - (Notes 1, 3) (25) TDVE2L Data Setup Time Early Write E2 60 - ns (Notes 1, 3) (26) TWHDX Data Hold Time Late Write 5 - ns (Notes 1, 3) (27) TE1HDX Data Hold Time Early Write E1 10 - ns (Notes 1, 3) (28) TE2LDX Data Hold Time Early Write E2 10 - ns (Notes 1, 3) (29) TWLQZ Write Enable Low to Output Off - 50 ns (Notes 2, 3) (30) TWHQX Write Enable High to Output On 5 - ns (Notes 2, 3) WRITE CYCLE NOTES: 1. Input pulse levels: 0V to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. VCC = 4.5V and 5.5V. 4 HM-65642 Low Voltage Data Retention Intersil CMOS RAMs are designed with battery backup in mind. Data Retention voltage and supply current are guaranteed over the operating temperature range. The following rules ensure data retention: 1. The RAM must be kept disabled during data retention. This is accomplished by holding the E2 pin between -0.3V and GND. 2. During power-up and power-down transitions, E2 must be held between -0.3V and 10% of VCC. 3. The RAM can begin operating one TAVAX after VCC reaches the minimum operating voltage of 4.5V. DATA RETENTION MODE VCC 4.5V VIH TAVAX E2 VCCOR GND FIGURE 1. DATA RETENTION Read Cycles TAVAX (1) A ADDRESS 1 TAVQV (2) Q ADDRESS 2 TAXQX (12) DATA 2 DATA 1 FIGURE 2. READ CYCLE I: W, E2 HIGH; G, E1 LOW 5 HM-65642 Read Cycles TAVAX (1) A TAVQV (2) E1 TE1LQV (3) TE1HQZ (9) TE1LQX (6) E2 TE2HQV (4) TE2LQZ (10) TE2HQX (7) G TGLQV (5) TGHQZ (11) TGLQX (8) Q FIGURE 3. READ CYCLE II: W HIGH Write Cycles TAVAX (13) A TAVWL (17) TWLWH (14) TWHAX (20) W E1 E2 TWHQX (30) TDVWH (23) D TWLQZ (29) Q FIGURE 4. WRITE CYCLE I: LATE WRITE 6 TWHDX (26) HM-65642 Write Cycles TAVAX (13) A TAVE1L (18) TE1LE1H (15) TE1HAX (21) W E1 E2 TDVE1H (24) TE1HDX (27) D FIGURE 5. WRITE CYCLE II: EARLY WRITE - CONTROLLED BY E1 TAVAX (13) A TE2HE2L (16) W TAVE2H (19) TE2LAX (22) E1 E2 TDVE2L (25) TE2LDX (28) D FIGURE 6. WRITE CYCLE III: EARLY WRITE - CONTROLLED BY E2 Typical Performance Curve VCC = 2.0V -3 -4 LOG (ICC/(1A)) -5 -6 -7 -8 -9 -10 -11 -12 -55 -35 -15 5 25 TA 45 65 85 105 125 (oC) FIGURE 7. TYPICAL ICCDR vs TA All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8