HS-65647RH TM Data Sheet Radiation Hardened 8K x 8 SOS CMOS Static RAM The Intersil HS-65647RH is a fully asynchronous 8K x 8 radiation hardened static RAM. This RAM is fabricated using the Intersil 1.2 micron silicon-on-sapphire CMOS technology. This technology gives exceptional hardness to all types of radiation, including neutron fluence, total ionizing dose, high intensity ionizing dose rates, and cosmic rays. Low power operation is provided by a fully static design. Low standby power can be achieved without pull-up resistors, due to the gated input buffer design. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95823. A “hot-link” is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp August 2000 File Number 2928.3 Features • Electrically Screened to SMD # 5962-95823 • QML Qualified per MIL-PRF-38535 Requirements • 1.2 Micron Radiation Hardened SOS CMOS - Total Dose. . . . . . . . . . . . . . . . . . . . . 300 krad(Si) (Max) - Transient Upset . . . . . . . . . . . . . . . . . >1 x 1011 rad(Si)/s - Single Event Upset . . . . . . . . < 1 x 10-12 Errors/Bit-Day • Latch-up Free • LET Threshold . . . . . . . . . . . . . . . . . . >250 MEV/mg/cm2 • Low Standby Supply Current . . . . . . . . . . . . . 10mA (Max) • Low Operating Supply Current . . . . . . . . . .100mA (2MHz) • Fast Access Time . . . . . . . . . . . . . 50ns (Max), 35ns (Typ) • High Output Drive Capability • Gated Input Buffers (Gated by E2) • Six Transistor Memory Cell • Fully Static Design Ordering Information • Asynchronous Operation INTERNAL MKT. NUMBER ORDERING NUMBER TEMP. RANGE (oC) • CMOS Inputs 5962F9582301QXC HS1-65647RH-8 -55 to 125 • 5V Single Power Supply 5962F9582301QYC HS-965647RH-8 -55 to 125 • Military Temperature Range . . . . . . . . . . . -55oC to 125oC 5962F9582301VXC HS1-65647RH-Q -55 to 125 • Industry Standard JEDEC Pinout 5962F9582301VYC HS9-65647RH-Q -55 to 125 Functional Diagram HS1-65647RH/PROTO HS1-65647RH/PROTO -55 to 125 HS9-65647RH/PROTO HS9-65647RH/PROTO -55 to 125 AI ROW ROW DECODER 128 X 512 MEMORY ARRAY TRUTH TABLE E1 E2 G W MODE X 0 X X Low Power Standby 1 1 X X Disabled 0 1 1 1 Enabled 0 1 0 1 Read 0 1 X 0 Write I/O0 INPUT DATA CIRCUIT COLUMN I/O COLUMN DECODER I/O7 AI COL E2 E1 G CONTROL CIRCUIT W 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 HS-65647RH Pinout HS1-65647RH 28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T28 TOP VIEW NC 1 28 VDD A12 2 27 W A7 3 26 E2 A6 4 25 A8 A5 5 24 A9 HS9-65647RH 28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP3-F28 TOP VIEW 1 28 VDD A12 A7 2 27 3 26 W E2 A6 4 25 A8 A5 5 24 A4 6 23 A9 A11 A3 A2 7 22 8 21 9 20 E1 10 DQ7 NC A4 6 23 A11 A3 7 22 G A2 8 21 A10 A1 9 20 E1 G A10 A0 10 19 DQ7 A1 A0 DQ0 11 19 18 DQ0 11 18 DQ6 DQ1 12 17 DQ6 DQ5 DQ1 12 17 DQ5 DQ2 13 16 DQ4 GND 14 15 DQ3 DQ2 13 16 DQ4 GND 14 15 DQ3 HS9A-65647RH 36 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) INTERSIL OUTLINE K36.A TOP VIEW 36 VDD A12 A7 2 35 3 34 W E2 A6 4 33 A8 A5 5 32 A9 A4 6 31 A11 NC 7 30 8 9 29 G A10 28 E1 10 11 12 13 27 26 DQ7 GND DQ0 14 15 DQ1 DQ2 GND A3 A2 A1 A0 DQ0 DQ1 DQ2 2 1 25 DQ6 DQ5 24 DQ4 23 22 DQ3 DQ0 16 21 DQ1 17 20 DQ2 18 19 GND HS-65647RH Timing Waveforms TAVAX ADDRESS 2 ADDRESS 1 A TAVQV TAXQX DATA 1 Q DATA 2 FIGURE 1. READ CYCLE I: W, E2 HIGH; G, E1 LOW TAVAX A TAVQV E1 TE1LQV TE1HQZ TE1LQX E2 TE2HQV TE2LQZ TE2HQX G TGHQZ TGLQV TGLQX Q FIGURE 2. READ CYCLE II: W HIGH TAVAX A TAVWL TWLWH TWHAX W E1 E2 TWHQX TDVWH D TWLQZ Q FIGURE 3. WRITE CYCLE I: LATE WRITE 3 TWHDX HS-65647RH Timing Waveforms (Continued) TAVAX A TAVE1L TE1LE1H TE1HAX TAVE2H W E1 E2 TDVE1H TE1HDX D FIGURE 4. WRITE CYCLE II: EARLY WRITE - CONTROLLED BY E1 TAVAX A TAVE2H TE2HE2L TE2LAX TAVE2L W E1 E2 TDVE2L TE2LDX D FIGURE 5. WRITE CYCLE III: EARLY WRITE - CONTROLLED BY E2 4 HS-65647RH Typical Performance Curves TA = 25oC, Unless Otherwise Specified 7 13 12 6 11 10 5 IDDSB (mA) IDDSB (mA) 9 8 7 6 5 4 4 3 2 3 2 1 1 0 0 200 400 600 800 1000 1200 0 1400 0.1 0.1 TOTAL DOSE (KRAD) 100 9 90 8 80 7 70 IDDEN (mA) IDDSB (mA) FIGURE 7. 10 6 5 4 50 40 30 2 20 1 10 -40 -20 0 20 40 60 80 100 0 -60 120 -40 -20 0 20 40 60 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 8. FIGURE 9. 120 106 110 102 100 98 80 100 120 94 IDDOP (mA) 90 IDDOP (mA) 60 3 -60 100 ANNEAL TIME (HOURS) FIGURE 6. 0 10 80 70 60 90 86 82 78 74 50 70 40 66 30 20 -60 62 -40 -20 0 20 40 60 TEMPERATURE (oC) FIGURE 10. 5 80 100 120 58 0 1 2 3 4 5 6 FREQUENCY (MHz) FIGURE 11. 7 8 9 10 HS-65647RH Burn-In Circuits HS-65647RH 28 LEAD FLATPACK AND CERAMIC DIP 1 NC F13 3 F8 4 F7 5 F6 6 F5 7 F4 8 F3 9 F2 F1 F14 F14 F14 2 10 R2 11 R2 12 R2 13 14 NC VDD A12 W A7 E2 A6 A8 A5 A9 A4 A11 A3 G A2 A10 A1 E1 A0 DQ7 DQ0 DQ6 DQ1 DQ5 DQ2 DQ4 VSS DQ3 HS-65647RH 28 LEAD FLATPACK AND CERAMIC DIP VDD VDD 28 NC 27 1 2 F0 26 3 25 24 23 F9 4 F10 5 F12 6 F0 7 8 22 21 F11 20 19 R2 18 R2 R2 17 R2 16 R2 15 9 F14 10 F14 11 NC F14 NC F14 NC F14 12 13 14 VDD A12 W A7 E2 A6 A8 A5 A9 A4 A11 28 27 26 25 24 23 A3 G 22 A2 A1 A10 21 E1 20 A0 DQ7 DQ0 DQ6 DQ1 DQ5 DQ2 DQ4 VSS DQ3 19 NC 18 NC 17 NC 16 NC 15 NC STATIC CONFIGURATION DYNAMIC CONFIGURATION NOTES: NOTES: 1. 2. 3. 4. 5. 6. NC 7. VDD = 5.5V Min. 8. R = 10kΩ ±10%. VDD = 5.5V Min. R = 10kΩ ±10%, except R2 = 47kΩ ±10%. VIH: VDD ±0.5V, VIL: 0.4V ±0.4V. F0 = 100kHz ±10%, 50% Duty Cycle. F1 = F0/2; F2 = F1/2; F3 = F2/2; . . . F14 = F13/2. F0 = inverted F0. HS-65647RH 36 LEAD FLATPACK HS-65647RH 36 LEAD FLATPACK VDD 1 2 NC F13 3 4 5 F8 6 F7 7 F6 F5 8 9 F4 10 F3 11 F2 12 F1 F14 R2 F14 R2 F14 R2 NC 13 VDD 1 VSS 36 VDD 35 VSS VDD NC 34 W 33 NC A12 2 F0 E2 32 A8 31 A7 A6 A4 A2 E1 26 DQ7 25 A1 A0 DQ6 24 DQ5 23 DQ4 22 DQ0 14 DQ1 15 DQ2 16 NC 17 VDD 18 VSS DQ3 21 VDD 20 4 5 F9 7 F10 8 F12 F0 G 28 A10 27 A3 3 6 A9 30 A11 29 A5 NC NC 9 10 F11 R2 R2 11 12 F14 NC F14 R2 F14 R2 F14 R2 F14 NC NC NC VSS 19 DYNAMIC CONFIGURATION 13 VSS VDD NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 14 DQ1 15 DQ2 16 NC 17 VDD 18 VSS NOTES: 9. 10. 11. 12. 13. 14. 15. VDD = 5.5V Min. 16. R = 10kΩ ±10%. 6 NC 34 W 33 NC E2 32 A8 31 A9 30 A11 29 G 28 A10 27 E1 26 DQ7 25 DQ6 24 DQ5 23 DQ4 22 DQ3 21 VDD 20 VSS 19 STATIC CONFIGURATION NOTES: VDD = 5.5V Min. R = 10kΩ ±10%, except R2 = 4.7kΩ ±10%. VIH: VDD ±0.5V, VIL: 0.4V ±0.4V. F0 = 100kHz ±10%, 50% Duty Cycle. F1 = F0/2; F2 = F1/2; F3 = F2/2; . . . F14 = F13/2. F0 = Inverted F0. VSS 36 VDD 35 NC NC NC NC NC HS-65647RH Irradiation Circuit HS-65647RH (8K x 8 TSOS4 SRAM) 28 LEAD CERAMIC DIP VDD NC 1 NC VDD 28 2 A12 W 27 3 A7 E2 26 4 A6 A8 25 5 A5 A9 24 6 A4 A11 23 7 A3 G 22 8 A2 A10 21 9 A1 E1 20 10 A0 DQ7 19 11 DQ0 DQ6 18 12 DQ1 DQ5 17 13 DQ2 DQ4 16 14 VSS DQ3 15 NOTES: 17. VDD = 5.5V ±0.5V R = 10kΩ ±10%. 18. Group E sample size is two die/wafer. Test Patterns MARCH (II) PATTERN This is pattern then repeated but using complemented data. After a background of zeros is written, each cell (from beginning to end in sequence) is read, written to a one and reread. When the array is full of ones each cell (from the end to the beginning) is read, restored to a zero and reread. GALCOL PATTERN (Column Galloping Pattern) After this the pattern is repeated but with complemented data. MASEST PATTERN (Multiple Address Select Pattern) A checkerboard pattern is written into the memory. Then the first cell is read, then its binary address complement is read. The second cell is read and then its binary address complement is read. This pattern of incrementing the address and then reading its binary address complement is repeated until the entire memory is read. This is then repeated but using a checkerboard bar pattern. GALROW PATTERN (Row Galloping Pattern) After a background of zeros is written into the memory a one is written into the first cell. It is then read alternately with each other cell in the row. The test cell is then rewritten back to a zero. The test cell is then incremented and the sequence is repeated until all cells in the memory have been used as a test cell. 7 After a background of zeros is written into the memory a one is written into the first cell. It is then read alternately with each other cell in the column. The test cell is then rewritten back to a zero. The test cell is then incremented and the sequence is repeated until all cells in the memory have been used as a test cell. This is pattern then repeated but using complemented data. CHECKERBOARD PATTERN and CHECKERBOARD BAR A checkerboard is written (101010) into the memory and then the pattern is read back. This is then repeated but using complemented data. HS-65647RH Metallization Topology DIE DIMENSIONS: GLASSIVATION: 313 mils x 291 mils x 21 mils ±1mil Type: SiO2 Thickness: 8kÅ ±1kÅ METALLIZATION: WORST CASE CURRENT DENSITY: Type: Al/Si/Cu Metal 1 Thickness: 7500Å ±2kÅ Metal 2 Thickness: 10kÅ ±2kÅ 1.5 x 105 A/cm2 Metallization Mask Layout NC (22) G (23) A11 (24) A9 (25) A8 (26) E2 (27) W (28) VDD (2) A12 (3) A7 (4) A6 (5) A5 (6) A4 NC (7) A3 HS-65647RH NC A10 (21) E (20) DQ7 (19) DQ6 (18) D15 (17) DQ4 (16) DQ3 (15) VDD VSS (14) DQ2 (13) DQ1 (12) DQ0 (11) A0 (10) VDD A1 (9) VDD A2 (8) VSS NC VSS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 8