INTERSIL HM4

HM-65642/883
8K x 8 Asynchronous
CMOS Static RAM
March 1997
Features
Description
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Full CMOS Design
• Six Transistor Memory Cell
• Low Standby Supply Current . . . . . . . . . . . . . . . .100µA
• Low Operating Supply Current . . . . . . . . . . . . . . . 20mA
• Fast Address Access Time . . . . . . . . . . . . . . . . . . 150ns
• Low Data Retention Supply Voltage. . . . . . . . . . . . 2.0V
• CMOS/TTL Compatible Inputs/Outputs
• JEDEC Approved Pinout
• Equal Cycle and Access Times
• No Clocks or Strobes Required
• Gated Inputs
- No Pull-Up or Pull-Down Resistors Required
• Temperature Range -55oC to +125oC
• Easy Microprocessor Interfacing
• Dual Chip Enable Control
The HM-65642/883 is a CMOS 8192 x 8-bit Static Random
Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide
standard, which allows easy memory board layouts which
accommodate a variety of industry standard ROM, PROM,
EPROM, EEPROM and RAMs. The HM-65642/883 is ideally
suited for use in microprocessor based systems. In particular, interfacing with the Intersil 80C86 and 80C88 microprocessors is simplified by the convenient output enable (G)
input.
The HM-65642/883 is a full CMOS RAM which utilizes an
array of six transistor (6T) memory cells for the most stable
and lowest possible standby supply current over the full military temperature range. In addition to this, the high stability
of the 6T RAM cell provides excellent protection against soft
errors due to noise and alpha particles. This stability also
improves the radiation tolerance of the RAM over that of four
transistor or MIX-MOS (4T) devices
Ordering Information
PACKAGE
TEMPERATURE RANGE
150ns/75µA
150ns/150µA
CERDIP
-55oC to +125oC
HM1-65642B/883
HM1-65642/883
CLCC
-55oC to +125oC
HM4-65642B/883
HM4-65642/883
200ns/250µA
PKG. NO.
HM1-65642C/883
-
F28.6
J32.A
Pinouts
A6 4
25 A8
E2
26 E2
W
A7 3
VCC
27 W
NC
A12 2
NC
28 VCC
A12
NC 1
HM4-65642/883 (CLCC)
TOP VIEW
A7
HM-65642/883 (CERDIP)
TOP VIEW
4
3
2
1
32
31
30
PIN
A6
5
29 A8
A5
6
28 A9
A4
7
27 A11
A
DESCRIPTION
Address Input
DQ
Data Input/Output
E1
Chip Enable
E2
Chip Enable
W
Write Enable
G
Output Enable
A5 5
24 A9
A4 6
23 A11
A3
8
26 NC
A3 7
22 G
A2
9
25 G
A2 8
21 A10
A1 10
24 A10
A1 9
20 E1
A0 11
23 E1
A0 10
19 DQ7
NC 12
22 DQ7
NC
DQ0 11
18 DQ6
21 DQ6
GND
Ground
VCC
Power
20
DQ5
15 DQ3
19
DQ4
GND 14
18
DQ3
16 DQ4
17
NC
17 DQ5
DQ2 13
15 16
GND
DQ1 12
14
DQ2
13
DQ1
DQ0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-220
No Connections
File Number
3004.1
HM-65642/883
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input or Output Voltage Applied for all Grades . . . . . . .GND -0.3V to
VCC +0.3V
Typical Derating Factor . . . . . . . . . . . . 5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical)
θJA
θJC
CERDIP Package . . . . . . . . . . . . . . . . 45oC/W
8oC/W
CLCC Package . . . . . . . . . . . . . . . . . . 55oC/W
10oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101,000 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . +2.2V to VCC +0.3V
Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max.
TABLE 1. HM-65642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
LIMITS
(NOTE 1)
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
PARAMETER
SYMBOL
High Level Output
Voltage
VOH 1
VCC = 4.5V, IO = -1.0mA
1, 2, 3
-55oC ≤ TA ≤ +125oC
2.4
-
V
Low Level Output
Voltage
VOL
VCC = 4.5V, IO = 4.0mA
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
0.4
V
High Impedance
Output Leakage
Current
IIOZ
HM-65642B/883, HM-65642/883
VCC = 5.5V, G = 2.2V,
VI/O = GND or VCC
1, 2, 3
-55oC ≤ TA ≤ +125oC
-1.0
+1.0
µA
HM-65642C/883
VCC = 5.5V, G = 2.2V,
VI/O = GND or VCC
1, 2, 3
-55oC ≤ TA ≤ +125oC
-2.0
+2.0
µA
HM-65642B/883, HM-65642/883
VCC = 5.5V, VI = GND or VCC
1, 2, 3
-55oC ≤ TA ≤ +125oC
-1.0
+1.0
µA
HM-65642C/883
VCC = 5.5V, VI = GND or VCC
1, 2, 3
-55oC ≤ TA ≤ +125oC
-2.0
+2.0
µA
HM-65642B/883
VCC = 5.5V, E1 = VCC -0.3V or
E2 = GND +0.3V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
100
µA
HM-65642/883
VCC = 5.5V, E1 = VCC -0.3V or
E2 = GND +0.3V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
250
µA
HM-65642C/883
VCC = 5.5V, E1 = VCC -0.3V or
E2 = GND +0.3V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
400
µA
Input Leakage
Current
Standby Supply
Current
II
ICCSB1
Standby Supply
Current
ICCSB
VCC = 5.5V, IO = 0mA, E1 = 2.2V or
E2 = 0.8V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
5
mA
Enable Supply
Current
ICCEN
VCC = 5.5V, IO = 0mA, E1 =0.8V,
E2 = 2.2V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
5
mA
Operating Supply
Current
ICCOP
VCC = 5.5V, G = 5.5V, (Note 2),
f = 1MHz, E1 = 0.8V, E2 = 2.2V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
20
mA
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HM-65642/883
TABLE 1. HM-65642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested
LIMITS
PARAMETER
Data Retention
Supply Current
Functional Test
(NOTE 1)
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
HM-65642B/883
VCC = 2.0V, E1 = VCC -0.3V or
E2 = GND +0.3V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
75
µA
HM-65642/883
VCC = 2.0V, E1 = VCC -0.3V or
E2 = GND +0.3V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
150
µA
HM-65642C/883
VCC = 2.0V, E1 = VCC -0.3V or
E2 = GND +0.3V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
250
µA
7, 8A, 8B
-55oC ≤ TA ≤ +125oC
-
-
-
SYMBOL
ICCDR
FT
VCC = 4.5V (Note 3)
NOTES:
1. All voltages referenced to device GND.
2. Typical derating 5mA/MHz increase in ICCOP.
3. Tested as follows: f = 2MHz, VIH = 2.4V, VIL = 0.4V, IOH = -4.0mA, IOL = 4.0mA, VOH ≥ 1.5V, and VOL ≤ 1.5V.
TABLE 2. HM-65642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
LIMITS
PARAMETERS
SYMBOL
(NOTES 1, 2)
CONDITIONS
HM65642B/883
HM65642/883
HM65642C/883
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
150
-
150
-
200
-
ns
Read/Write/
Cycle Time
TAVAX
VCC = 4.5V and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
Address Access
Time
TAVQV
VCC = 4.5V and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
-
150
-
150
-
200
-
Output Enable
Access Time
TGLQV
VCC = 4.5V and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
-
70
-
70
-
70
ns
Chip Enable
Access Time
TE1LQV
TE2HQV
VCC = 4.5V and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
-
150
-
150
-
200
ns
Write Recovery
Time
TWHAX
TE1HAX
TE2LAX
VCC = 4.5V and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
10
-
10
-
10
-
ns
Chip Enable to
End-of-Write
TE1LE1H
TE2HE2L
VCC = 4.5V and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
90
-
90
-
120
-
ns
Address Setup
Time
TAVWL
TAVE1L
TAVE2H
VCC = 4.5V and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
0
-
0
-
0
-
ns
Write Enable
Pulse Width
TWLWH
VCC = 4.5V and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
90
-
90
-
120
-
ns
Data Setup Time
TDVWH
TDVE1H
TDVE2L
VCC = 4.5V and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
60
-
60
-
80
-
ns
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HM-65642/883
TABLE 2. HM-65642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
LIMITS
PARAMETERS
Data Hold Time
(NOTES 1, 2)
CONDITIONS
SYMBOL
HM65642B/883
HM65642/883
HM65642C/883
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
TWHDX
VCC = 4.5V and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
5
-
5
-
5
-
ns
TE1HDX
VCC = 4.5V and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
10
-
10
-
10
-
ns
TE2LDX
VCC = 4.5V and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
10
-
10
-
10
-
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume transition time ≤ 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1TTL equivalent
load and CL ≥ 50pF, for CL > 50pF, access times are derated 0.15ns/pF.
TABLE 3. HM-65642/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
LIMITS
PARAMETER
Output High Voltage
Input Capacitance
I/O Capacitance
Write Enable to Output in High Z
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
VOH2
VCC = 4.5V, IO = -100µA
1
-55oC ≤ TA ≤ +125oC
VCC -0.4
-
V
VCC = Open, f = 1MHz, All
Measurements Referenced to Device Ground
1, 2
TA = +25oC
-
12
pF
VCC = Open, f = 1MHz, All
Measurements Referenced to Device Ground
1, 3
TA = +25oC
-
10
pF
VCC = Open, f = 1MHz, All
Measurements Referenced to Device Ground
1, 2
TA = +25oC
-
14
pF
VCC = 4.5V, VI/O = GND
or VCC, All Measurements
Referenced to Device
Ground
1, 3
TA = +25oC
-
12
pF
1
-55oC ≤ TA ≤ +125oC
-
50
ns
5
-
ns
CIN
CI/O
TWLQZ
VCC = 4.5V and 5.5V
Write Enable High to Output ON
TWHQX
VCC = 4.5V and 5.5V
1
-55oC ≤ TA ≤ +125oC
Chip Enable to Output ON
TE1LQX
TE2HQX
VCC = 4.5V and 5.5V
1
-55oC ≤ TA ≤ +125oC
10
-
ns
Output Enable to Output ON
TGLQX
VCC = 4.5V and 5.5V
1
-55oC ≤ TA ≤ +125oC
5
-
ns
Chip Enable to Output in High Z
TE1HQZ
VCC = 4.5V and 5.5V
1
-55oC ≤ TA ≤ +125oC
-
50
ns
1
-55oC ≤ TA ≤ +125oC
-
60
ns
TE2LQZ
Output Disable to Output in High Z
TGHQZ
VCC = 4.5V and 5.5V
1
-55oC ≤ TA ≤ +125oC
-
50
ns
Output Hold from Address
Change
TAXQX
VCC = 4.5V and 5.5V
1
-55oC ≤ TA ≤ +125oC
10
-
ns
NOTES:
1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics.
2. Applies to DIP device types only. For design purposes CIN = 6pF typical and CI/O = 7pF typical.
3. Applies to LCC device types only. For design purposes CIN = 4pF typical and CI/O = 5pF typical.
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HM-65642/883
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
GROUPS METHOD
SUBGROUPS
Interim Test 1
100%/5004
-
Interim Test
100%/5004
1, 7, 9
PDA
100%/5004
1
Final Test 1
100%/5004
2, 3, 8A, 8B, 10, 11
Group A
Samples/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C and D
Samples/5005
1, 7, 9
6-224
HM-65642/883
Low Voltage Data Retention
1. The RAM must be kept disabled during data retention. This is accomplished by holding the E2 pin between -0.3V and GND.
Intersil CMOS RAMs are designed with battery backup in
mind. Data Retention voltage and supply current are guaranteed over the operating temperature range. The following
rules ensure data retention:
2. During power-up and power-down transitions, E2 must be held
between -0.3V and 10% of VCC.
3. The RAM can begin operating one TAVAX after VCC reaches the
minimum operating voltage of 4.5V.
DATA RETENTION MODE
VCC
4.5V
VIH
TAVAX
E2
VCCOR
GND
FIGURE 1. DATA RETENTION
Read Cycles
TAVAX
A
ADDRESS 1
TAVQV
ADDRESS 2
TAXQX
DATA 2
DATA 1
Q
FIGURE 2. READ CYCLE I: W, E2 HIGH; G, E1 LOW
TAVAX
A
TAVQV
E1
TE1LQV
TE1HQZ
TE1LQX
E2
TE2HQV
TE2LQZ
TE2HQX
G
TGLQV
TGHQZ
TGLQX
Q
FIGURE 3. READ CYCLE II: W HIGH
6-225
HM-65642/883
Write Cycles
TAVAX
A
TAVWL
TWLWH
TWHAX
W
E1
E2
TWHQX
TDVWH
TWHDX
D
TWLQZ
Q
FIGURE 4. WRITE CYCLE I: LATE WRITE
TAVAX
A
TAVE1L
TE1LE1H
TE1HAX
W
E1
E2
TDVE1H
TE1HDX
D
FIGURE 5. WRITE CYCLE II: EARLY WRITE - CONTROLLED BY E1
TAVAX
A
TAVE2H
TE2HE2L
TE2LAX
W
E1
E2
TDVE2L
TE2LDX
D
FIGURE 6. WRITE CYCLE III: EARLY WRITE - CONTROLLED BY E2
6-226
HM-65642/883
Test Circuit
DUT
(NOTE 1) CL
+
-
IOH
1.5V
IOL
EQUIVALENT CIRCUIT
NOTE:
1. Test head capacitance.
Burn-In Circuits
HM-65642/883
CERDIP
TOP VIEW
HM-65642/883
CLCC
TOP VIEW
F16
F1
C
F15
F10
VCC
C
GND
F2
F2
F2
A0
DQ0
DQ1
DQ2
5
24
6
23
7
22
8
21
9
20
10
11
19
18
12
17
13
16
14
15
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
F11
F9
F8
F12
F14
F7
F6
A6
A5
E2
VCC
NC
W
NC
1
32 31 30
29
6
28
27
8
26 NC
G
25
A10
24
E1
23
DQ7
22
DQ6
21
A2
F0
F3
9
A1 10
A0 11
F2
NC 12
DQ0 13
14 15 16 17 18 19 20
F2
NOTES:
NOTES:
F0 = 100kHz ±10%.
All resistors 47kΩ ±5%.
C = 0.01µF Min.
VCC = 5.5V ±0.5V.
VIH = 4.5V ±10%.
VIL = -0.2V to +0.4V.
F0 = 100kHz ±10%.
C = 0.01µF Min.
VCC = 5.5V ±0.5V.
VIH = 4.5V ±10%.
VIL = -0.2V to +0.4V.
6-227
A11
7
F4
F2
A9
A3
F13
F2
A8
A4
F5
F2
2
3
5
F0
F2
A12
A7
4
F16
F2
GND
25
A8
F1
F2
F3
A1
4
E2
DQ5
F4
A2
26
F2
F5
A3
3
W
DQ4
F6
A4
27
F2
F7
A5
2
NC
DQ3
F8
A6
28
GND
F9
A7
1
F2
F10
A12
DQ2
F15
VCC
DQ1
NC
F11
F12
F14
F0
F13
F0
F2
F2
HM-65642/883
Die Characteristics
DIE DIMENSIONS:
274.0 x 302.8 x 19 ±1mils
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
METALLIZATION:
Type: Si - Al
Thickness: 11kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
0.9 x 105 A/cm2
Metallization Mask Layout
HM-65642/883
A8
A7 A12
VCC
W
E2
A8
A5
A4
A3
A9
A11
A2
A1
A0
A10
E1
DQ7
G
DQ0
DQ1 DQ2 GND DQ3
DQ4
DQ5 DQ6
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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