A/D, D/C Converters for Image Signal Processing MN65702H Low Power 8-Bit, 3-Channel CMOS D/A Converter for Image Processing Features Maximum conversion rate: 20 MSPS (min.) Linearity error: ±0.2 LSB (typ.) Differential linearity error: ±0.2 LSB (typ.) Power supply voltage: VDD= 3.3 ±0.3 V, VCC= 4.8 ±0.3 V Full scale current: 2.33 mA (typ.) Power consumption: 100 mW (typ.) (fCLK=15 MHz) Built-in LPF and synchronization function. Applications DC4 DC5 DC6 DC7 DC8 DVSS DVDD N.C. AVSS VREFC N.C. COMPC 36 35 34 33 32 31 30 29 28 27 26 25 N.C. DC3 DC2 DC1 UVSEL DVDD DVSS CLK DY8 DY7 DY6 DY5 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 The MN65702H is a high-speed 8-bit, 3-channel CMOS digital-to-analog converter. (Two channels use serial input.) It uses both a matrix cell and weighted current technology to achieve both low power consumption and high speed. It features built-in output resistor, reference resistor, and low pass filter, and provides independent output amplitude adjustment for the Y (luminance) and C (chroma) synchronization signals. The Y (luminance signal) can be superimposed with an external SYNC signal. Pin Assignment N.C. VOUT VCC UOUT AVSS VCC YOUT AVSS VREFY N.C. COMPY VREFS DY4 DY3 DY2 DY1 SYNC VCC DVSS N.C. N.C. AVDD COMPS N.C. Overview (TOP VIEW) QFH048-P-0707 Digital television Digital video equipment Digital image processing equipment 1 2 AVSS AVSS AVSS 28 20 17 22 + – VCC Current cell Low pass filter Current cell Low pass filter 21 Current cell Low pass filter Current cell – 19 10 Latch Decoder Decoder Latch 32 Latch 33 18 Latch Decoder + VCC AVCC 25 27 43 Current Source COMPC VREFC DVSS Latch Latch Latch – 31 40 DC1 DC2 39 DC3 38 Latch DY7 46 45 DY8 Latch + DVSS 7 41 DVSS UVSEL DVDD DC8 42 DC7 Latch DC4 36 DC5 35 DC6 34 Latch 4 DY1 DY2 3 2 DY3 DY4 1 DY5 48 DY6 47 30 6 SYNC 5 DVDD VCC 12 37 29 26 24 15 9 8 14 16 11 N.C. COMPY VREFY COMPS 13 V REFS MN65702H A/D, D/C Converters for Image Signal Processing Block Diagram Current Source CLK 44 23 Current Source YOUT UOUT VOUT A/D, D/C Converters for Image Signal Processing MN65702H Pin Descriptions Pin No. 1 Symbol DY4 Function Description Y (luminance) digital input 2 DY3 Y (luminance) digital input 3 DY2 Y (luminance) digital input 4 DY1 Y (luminance) digital input (MSB) 5 SYNC SYNC signal judgment signal 6 VCC Filter power supply for analog circuits 7 DVSS Ground for digital circuits 8 N.C. No connection 9 N.C. No connection 10 AVDD 11 COMPS Power supply for analog circuits Phase compensation 12 N.C. No connection 13 VREFS SYNC reference voltage input 14 COMPY 15 N.C. 16 VREFY Luminance reference voltage input 17 AVSS Ground for analog circuits 18 YOUT Y signal analog current output 19 VCC Filter power supply for analog circuits 20 AVSS Ground for analog circuits 21 UOUT U signal analog current output 22 VCC Filter power supply for analog circuits 23 VOUT V signal analog current output 24 N.C. 25 COMPC Phase compensation No connection No connection Phase compensation 26 N.C. No connection 27 VREFC Chroma reference voltage input 28 AVSS Ground for analog circuits 29 N.C. No connection 30 DVDD Power supply voltage for digital circuits 31 DVSS Ground for digital circuits 32 DC8 C (chroma) digital input (LSB) 33 DC7 C (chroma) digital input 34 DC6 C (chroma) digital input 35 DC5 C (chroma) digital input 36 DC4 C (chroma) digital input 37 N.C. No connection 38 DC3 C (chroma) digital input 39 DC2 C (chroma) digital input 40 DC1 41 UVSEL 42 DVDD C (chroma) digital input (MSB) U/V signal discrimination for C (chroma) signal Power supply voltage for digital circuits 3 MN65702H A/D, D/C Converters for Image Signal Processing Pin Descriptions (continued) Pin No. 43 Symbol DVSS Function Description Power supply for digital circuits 44 CLK Sampling clock 45 DY8 Y (luminance) digital input (LSB) 46 DY7 Y (luminance) digital input 47 DY6 Y (luminance) digital input 48 DY5 Y (luminance) digital input Absolute Maximum Ratings Parameter Power supply voltage Ta=25˚C Symbol DVDD/AVDD Rating – 0.3 to +7.0 Unit V VCC – 0.3 to +7.0 V VI – 0.3 to DVDD +0.3 V Output voltage VO – 0.3 to AVDD +0.3 V Operating ambient temperature Topr –20 to +70 ˚C Storage temperature Tstg –55 to +125 ˚C Power supply voltage for analog circuits Input voltage Recommended Operating Conditions VDD=AVDD=DVDD=3.3V, VCC=4.8V, VSS=AVSS=DVSS=0V, Ta=25˚C Parameter Power supply voltage Symbol VCC min 4.5 VDD Reference voltage VREFS/Y/C External compensation capacitor Digital input "H" level typ 4.8 max 5.1 Unit V 3.0 3.3 3.6 V — 2.15/1.96/1.93 — V CCOMPS, Y, C 0.33 1.0 3.3 µF VIH 2.4 — VDD V voltage "L" level VIL VSS — 0.8 V Clock "H" level pulse width tWH 20 — — ns "L" level pulse width tWL 20 — — ns Electrical Characteristics Parameter Power supply voltage DVDD=AVDD=3.0V, VCC=4.8V, DVSS=AVSS=0V, Ta=25˚C Symbol Conditions IDD/ICC fCLK=15MHz, Output amplitude = 0.7 V, Resolution 4 RES min typ max Unit — 12/12 21/21 mA — 8 — bit Linearity error EL VDD=3.3V, VCC=4.8V — ±0.2 ±0.5 LSB Differential linearity error ED Y (luminance) output amplitude =0.7Vp-p — ±0.2 ±0.5 LSB Full scale current IFS C (chroma) output amplitude =0.7Vp-p — 2.33 — mA Setup time tS 15 — — ns Hold time tH Settling time tST VDD=3.3V, VCC=4.8V 5 — — ns — 30 50 ns Maximum conversion speed FC(max.) Y·C output amplitude =0.7VP–P 20 — — MSPS Analog output delay time tdY/tdc f=100kHz — 90/140 — ns A/D, D/C Converters for Image Signal Processing Filter Characteristics MN65702H DVDD=AVDD=3.0V, VCC=4.8V, DVSS=AVSS=0V, Ta=25˚C Parameter Y filter I/O gain Symbol GYF Conditions f=100kHz min –1.2 typ – 0.2 Y filter f characteristic (fck/2) Y filter f characteristic (3MHz) max 0.8 Unit dB FYFCK f=100kHz → 6.35MHz –10 FYFCL f=100kHz → 3.0MHz –3 –7 –4 dB –1 1.0 dB Y filter group delay DYF f=100kHz 60 80 100 dB UV filter I/O gain GCF f=100kHz –1.2 – 0.2 0.8 dB UV filter f characteristic (fck/4) FCFCK f=100kHz → 3.18MHz –15 –10 –6 dB UV filter f characteristic (1MHz) FCFCL f=100kHz → 1.0MHz –3 –1 1.0 dB f=100kHz 100 130 160 ns UV filter group delay DCF Timing Chart M SELECT = "H," Y and U(C), 3-channel output SYNC CLK DY1 to DY8 Y-1 Y0 Y1 Y2 Y3 Y4 Y5 DC1 to DC8 Y-2 U0 V0 U2 V2 U4 V4 UVSEL Two clock cycles Y-2 YOUT Y-1 Y0 Y1 Y3 tds tds UOUT U-4 U-2 U0 U2 VOUT V-4 V-2 V0 V2 Two clock cycles td tst tds: SYNC delay time td: Analog output delay time tst: Settling time 5 MN65702H A/D, D/C Converters for Image Signal Processing Package Dimensions (Unit:mm) QFH048-P-0707 9.0±0.2 7.0±0.2 36 25 24 9.0±0.2 7.0±0.2 (0.75) 37 13 48 1 0.5 (0.75) 12 0.2±0.1 0.1 SEATING PLANE 6 0.1±0.1 0.15 +0.10 -0.05 2.9 max. 2.5±0.2 (1.0) 0.5±0.2 0 to 10°