RENESAS M62383FP

M62383FP
5 V Composite Type D-A Converter
REJ03F0076-0100Z
Rev.1.0
Sep.19.2003
Description
The M62383FP is a 5 V composite D-A converter incorporating two modules, with two 8-bit buffer amp output D-A
converters and an 8-bit D-A converter for reference voltage adjustment as one module.
The D-A outputs can be set simultaneously for each module without address setting. The data configurations comprise
16-bit serial data for the two main D-A circuits and 8-bit serial data for the reference voltage setting D-A. The D-A
output buffer amps have full-swing output capability, from power supply voltage to GND.
Features
•
•
•
•
Simultaneous dual-output data setting by means of 16-bit serial data (TTL level)
Data transfer clock frequency: 10 MHz (max.)
D-A converter output settling time: 5 µs (typ.)
Power-on reset and external reset (L reset) functions
(D-A output = 0 V, MON output = VREF × 255/256)
Application
Automatic adjustment of electronic devices
Recommended Operating Conditions
Power supply voltage: 5 V ±10%
Pin Connection Diagram (Top View)
1
24
SCKREFx
MONx
2
23
SDIREFx
D/AXx
3
22
SLDREFx
D/AYx
4
21
SCKx
VREFx
5
20
SDIx
VCC
6
19
SLDx
VREFy
7
18
SCKREFy
D/AXy
8
17
SDIREFy
M62383FP
GND
D/AYy
9
16
SLDREFy
MONy
10
15
SCKy
GND
11
14
SDIy
12
13
SLDy
RESET
Package: 24P2Q-A
Rev.1.0, Sep.19.2003, page 1 of 9
M62383FP
Block Diagram
VREFx
5
SDIREFx
23
8-bit shift
register
8-bit
latch
8-bit
D-A
2
MONx
SCKREFx 24
SLDREFx 22
SDIx 20
16-bit shift
register
8-bit
latch
8-bit
D-A
3
D-AXx
8-bit
latch
8-bit
D-A
4
D-AYx
SCKx 21
SLDx 19
Module 1
VCC
6
Reset
VREFy
12 RESET
11 GND
GND 1
7
SDIREFy 17
10 MONy
SCKREFy 18
SLDREFy 16
SDIy 14
8
D-AXy
9
D-AYy
SCKy 15
SLDy 13
Module 2
Rev.1.0, Sep.19.2003, page 2 of 9
M62383FP
Pin Description
Pin No.
Symbol
Function
1, 11
GND
Ground (GND) pin
2
MONx
Module 1: Reference voltage D-A output pin
10
3
MONy
D/Axx
Module 2: Reference voltage D-A output pin
Module 1: 8-bit D-A output pin (x side)
4
8
D/Axy
D/Ayx
Module 1: 8-bit D-A output pin (y side)
Module 2: 8-bit D-A output pin (x side)
9
5
D/Ayy
VREFx
Module 2: 8-bit D-A output pin (y side)
Module 1: Reference voltage input pin
7
6
VREFy
Vcc
Module 2: Reference voltage input pin
Power supply (VCC) pin
12
RESET
Reset pin
19
SLDx
13
SLDy
22
SLDREFx
16
SLDREFy
20
14
When input level is changed from “H” to “L”, D-A output becomes 0 V (DA data: 00h), and MON output becomes VREF × 255/256 (MON data:
FFh). Even if input level is restored from “L” to “H”, output is maintained
until next data setting. TTL-based.
At rising edge of input signal from “L” to
Module 1: Load signal input pin
“H”, data in 16-bit shift register is loaded
Module 2: Load signal input pin
into D/A data register. TTL-based.
Module 1: Reference voltage load signal
input pin
Module 2: Reference voltage load signal
input pin
At rising edge of input signal from “L” to
“H”, data in 8-bit shift register is loaded into
D/A data register. TTL-based.
SDIx
SDIy
Module 1: Serial data input pin
Module 2: Serial data input pin
TTL-based 16-bit-length serial data
23
SDIREFx
TTL-based 8-bit-length serial data
17
SDIREFy
Module 1: Reference voltage serial data
input pin
Module 2: Reference voltage serial data
input pin
21
15
SCKx
SCKy
Module 1: Shift clock signal input pin
Module 2: Shift clock signal input pin
18
SCKREFx
Module 1: Reference voltage shift clock
signal input pin
24
SCKREFy
Module 2: Reference voltage shift clock
signal input pin
TLL Schmitt trigger based serial clock input
SDI serial data is sent to 16-bit shift
register one bit at a time at each rise.
TLL Schmitt trigger based serial clock input
SDIREF serial data is sent to 8-bit shift
register one bit at a time at each rise.
Absolute Maximum Ratings
(Unless specified otherwise, Ta = 25ºC)
Item
Symbol
Rated Value
Unit
Conditions
Power supply voltage
Digital input voltage
VCC
VDIN
-0.3 to 7.0
-0.3 to Vcc+0.3 (≤ 7.0)
V
V
DC voltage (“H” level voltage)
Reference voltage input voltage
Output voltage
VREF
VDAout
-0.3 to Vcc+0.3 (≤ 7.0)
-0.3 to Vcc+0.3 (≤ 7.0)
V
V
Internal permissible loss
Operating ambient temperature
Pd
Topr
500
-20 to +85
mW
°C
Storage temperature
Tstg
-55 to +150
°C
Rev.1.0, Sep.19.2003, page 3 of 9
M62383FP
Recommended Operating Conditions
(Unless specified otherwise, VCC = 5 V ±10%, VREF = VCC, fSCK = 5 MHz, VIH = VCC, VIL = GND, Ta = 25ºC)
Specification Values
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Power supply voltage
Reference power supply voltage
Vcc
VREF
4.5
GND
5.0
5.5
Vcc
V
V
VCC voltage or below
Clock frequency
“H” level input voltage
fSCK
VIH
2
10
Vcc
MHz
V
TTL “H” input level
“L” level input voltage
Clock input hysteresis voltage
VIL
V∆
GND
0.4
0.8
1.0
V
V
TTL “L” input level
TTL Schmitt trigger
Clock “L” pulse width
Clock “H” pulse width
tSCKL
tSCKH
30
30
450
450
ns
ns
See timing chart
See timing chart
Clock rise time
Clock fall time
tSCKR
tSCKF
10
10
100
100
ns
ns
See timing chart
See timing chart
Data setup time
Data hold time
tDCH
tCHD
10
20
100
200
ns
ns
See timing chart
See timing chart
Load setup time
Load hold time
tCHL
tLDC
40
20
800
400
ns
ns
See timing chart
See timing chart
Load “H” pulse time
Reset “H” pulse time
tLDH
tRSTL
20
50
400
ns
ns
See timing chart
See timing chart
0.6
Timing Chart
t SCKH
t SCKR
t SCKF
SCK
t SCKL
SDI
t DCH
t CHD
t LDH
t LDC
t CHL
SLD
t LDD
±0.5LSB
V OA = 0.5V, V OR = 0.5V
V OA = 4.5V, V OR = 4.5V
±0.5LSB
RESET
Rev.1.0, Sep.19.2003, page 4 of 9
t RSTL
t LDD
0.5V
M62383FP
Electrical Characteristics
(Unless specified otherwise, VCC = 5 V ±10%, VREF = VCC, fSCK = 5 MHz, VIH = VCC, VIL = GND, Ta = -20ºC
to 85ºC)
(a) Common to analog and digital blocks
Specification Values
Item
Symbol
Circuit current
Icc
Min.
Typ.
Max.
Unit
6.0
10
mA
Test Conditions
(b) Digital block
Specification Values
Item
Symbol
Min.
Input leakage current
IILK
−10
Rev.1.0, Sep.19.2003, page 5 of 9
Typ.
Max.
Unit
Test Conditions
10
µA
VIN = 0V to 5V
M62383FP
(c) Analog block
Specification Values
Item
Symbol
Min.
Reference voltage input voltage
VREF
GND
Reference voltage input current
IREF
−1
Upper reference voltage output
voltage (*1)
Lower reference voltage output
voltage (*1)
VORU
4.88
VORL
Reference voltage output offset
voltage (*1)
Typ.
Max.
Unit
Test Conditions
Vcc
V
When SDIREF is set to (FF)h,
VREF = MON
+1
µA
GND≤VREF≤Vcc
Vcc
V
GND
0.10
V
SDIREF = (FF)h, SDI =
(FFFF)h, MON output value
SDIREF = (00)h, SDI = (FFFF)h,
MON output value
∆VOR
−100
100
mV
Upper buffer amp D-A output
voltage
VOAU
4.5
Lower buffer amp D-A output
voltage
Accuracy: Differential
nonlinearity error
VOAL
SDL
Accuracy: Nonlinearity error
Accuracy: Zero scale error
4.98
V
0.05
V
−1.0
+1.0
LSB
SNL
SZERO
−1.0
−2.0
+1.0
+2.0
LSB
LSB
Accuracy: Full-scale error
SFULL
−2.0
+2.0
LSB
Reference voltage input pin
capacitance
CREF
10
pF
D-A converter output settling
time
tLDDA
5
10
µS
Reference voltage output
settling time
tLDDR
10
20
µS
Power-on reset voltage (*3)
VRESET
1.5
3
V
0.8
VREF = 2 to 5V, SDI = (FFFF)h,
255/256VREF-VOR (MON
output value)
IOA = ±0.5mA, SDIREF = (FF)h,
SDI = (FFFF)h
IOA = ±0.5mA, SDIREF = (FF)h,
SDI = (0000)h
(Monotone increasing capability)
VREF = 2 to 5 V: Buffer output
offset (*2)
VREF = 2 to 5 V: Buffer output
offset (*2)
VOA = 0.5↔4.5V, IOA = 0.1mA,
Co = 50pF, SDIREF = (FF)h,
Time for output to be absorbed
within ±0.5 LSB
VOA = 0.5↔4.5V, no external
load
Time for output to be absorbed
within ±0.5 LSB
Vcc = 0→5V, VOA = 0V, VOR =
VREF×255/256 set
Notes: 1. MON output specification. Equivalent to ±5 LSB.
2. D-A output (D-Axx, D-Axy, D-Ayx, D-Ayy) specification. MON output is stipulated by 3 items in *1 above
(VORU, VORL, ∆VOR).
3. Reference values
Rev.1.0, Sep.19.2003, page 6 of 9
M62383FP
Digital Data Format
SCK
MSBn
SDI
LSB
* D-A converter serial data is MSB-first data.
SLD
D-A
SDIx, SDIy
MSB
LSB
D15
D14
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
D7X
D6X
D5X
D4X
D3X
D2X
D1X
D0X
D7Y
D6Y
D5Y
D4Y
D3Y
D2Y
D1Y
D0Y
2 ×D7 *+2 ×D6 *+2 ×D5 *+2 ×D4 *+2 ×D3 *+2 ×D2 *+2 ×D1 *+2 ×D0 *
256
7
VOA = VOR ×
6
5
4
3
2
1
0
VOA: D-A output voltage
VOR: MON output voltage
Dn*: D-A data
n = 0 to 7, * = x, y
SDIREFx, SDIREF
MSB
D7
LSB
D6
D5
D4
D2
D1
D0
2 ×D7+2 ×D6+2 ×D5+2 ×D4+2 ×D3+2 ×D2+2 ×D1+2 ×D0
256
7
VOA = VREF ×
D3
6
5
4
3
2
1
0
VOR: MON output voltage
VREF: Reference voltage
Usage Notes
1. This IC has three pins to which a constant voltage is applied during use (constant-voltage input pins: VCC, VREFx,
VREFy). If ripples or spikes are imposed on these pins, D-A conversion accuracy may fall. When using this IC, a
capacitor (1 µF or higher recommended) must be inserted between the constant-voltage input pins and ground
(GND) in order to ensure stable D-A conversion.
2. With regard to the reset function (power-on reset), when the power supply voltage passes the vicinity of 1.5 V at
power-on, the D-A output voltage (VOA) becomes 0 V (D-A data: 00h), and the MON output voltage (VOR)
becomes VREF × 255/256 (MON data: FFh), and output is maintained until the next data is set. In the event of
repeated power supply on/off operations at short intervals, a reset may not be effected because of the simplicity of
the circuit.
Rev.1.0, Sep.19.2003, page 7 of 9
M62383FP
Sample Standard Application Circuit
1
24
2
23
xx
3
22
xy
4
21
5
20
D-Ax* Reference voltage
monitoring
D-A output
6
7
D-A output
M62383FP
5V
19
18
17
yx
8
yy
9
16
10
15
11
14
12
13
D-Ay* Reference voltage
monitoring
H: Fixed
Rev.1.0, Sep.19.2003, page 8 of 9
Module 1 D-A data
Module 2 D-A data
HE
G
Z1
e
1
24
z
Detail G
D
y
JEDEC Code

MMP
b
12
13
Weight(g)
0.2
Detail F
A2
A
Lead Material
Cu Alloy
L1
EIAJ Package Code
SSOP24-P-300-0.80
E
Rev.1.0, Sep.19.2003, page 9 of 9
A1
F
c
L
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
y
Symbol
e1
b2
e1
I2
b2
Dimension in Millimeters
Min
Nom
Max
2.1


0.2
0.1
0

1.8

0.45
0.35
0.3
0.25
0.2
0.18
10.2
10.1
10.0
5.4
5.3
5.2

0.8

8.1
7.8
7.5
0.8
0.6
0.4

1.25



0.65

0.8

0.1


0°

8°

0.5


7.62


1.27

Recommended Mount Pad
e
Plastic 24pin 300mil SSOP
I2
24P2Q-A
M62383FP
Package Dimensions
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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