CD4007UBMS CMOS Dual Complementary Pair Plus Inverter November 1994 Features Pinout • High-Voltage Type (20V Rating) CD4007UBMS TOP VIEW • Standardized Symmetrical Output Characteristics • Medium Speed Operation - tPHL, tPLH = 30 ns (typ) at 10V Q2 (P) DRAIN 1 14 VDD, Q1, Q2, Q3 (P) SUBSTRATES, Q1(P) DRAIN Q2 (P) SOURCE 2 • 100% Tested for Maximum Quiescent Current at 20V 13 Q1 (P) SOURCE Q2 GATES 3 • Meets All Requirements of JEDEC Tentative Standards No. 13B, “Standard Specifications for Description of “B” Series CMOS Devices” 12 Q3 (N) DRAIN, Q3 (P) SOURCE Q2 (N) SOURCE 4 11 Q3 (P) DRAIN Q2 (N) DRAIN 5 10 Q3 GATES Q1 GATES 6 • Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; 100nA at 18V and +25oC VSS, Q1, Q2, Q3 (N) SUBSTRATES Q1 (N) SOURCE 9 Q3 (N) SOURCE 8 Q1 (N) DRAIN 7 Applications • Extremely High-Input Impedance Amplifiers Functional Diagram • Shapers 14 • Inverters • Threshold Detector p 2 11 p p • Linear Amplifiers • Crystal Oscillators 6 13 Description 1 3 8 n CD4007BMS types are comprised of three n-channel and three p-channel enhancement-type MOS transistors. The transistor elements are accessible through the package terminals to provide a convenient means for constructing the various typical circuits as shown in Figure 2. More complex functions are possible using multiple packages. Numbers shown in parentheses indicate terminals that are connected together to form the various configurations listed. 12 5 n 7 10 n 4 9 TERMINAL NO. 14 - VDD TERMINAL NO. 7 - VSS The CD4007BMS is supplied in these 14 lead outline packages: Braze Seal DIP H4Q Frit Seal DIP H1B Ceramic Flatpack H3W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-666 File Number 3291 Specifications CD4007UBMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 GROUP A SUBGROUPS LIMITS TEMPERATURE MIN MAX 1 +25 - 0.5 µA +125oC - 50 µA 3 -55oC - 0.5 µA 1 +25o C -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA - 100 nA - 50 mV - V 3 -55oC Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 VDD = 18V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V UNITS 2 oC 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA 1 +25oC - -1.8 mA Output Current (Source) Output Current (Source) IOH5A IOH5B VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V 1 +25oC 0.7 2.8 V N Threshold Voltage P Threshold Voltage Functional VNTH VPTH F VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.0 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 4.0 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 2.5 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 12.5 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs 7-667 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4007UBMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Transition Time SYMBOL TPHL TPLH CONDITIONS (NOTE 1, 2) GROUP A SUBGROUPS TEMPERATURE VDD = 5V, VIN = VDD or GND 9 10, 11 TTHL TTLH VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 110 ns - 149 ns - 200 ns - 270 ns NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. 55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND 1, 2 TEMPERATURE o o -55 C, +25 C VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 1, 2 MAX UNITS - 0.25 µA +125 C - 7.5 µA -55oC, +25oC - 0.5 µA +125oC - 15 µA o VDD = 10V, VIN = VDD or GND MIN - 0.5 µA +125oC - 30 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) Input Voltage Low IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VIL VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 VDD =15V, VOUT = 13.5V VDD = 10V, VOH > 9V, VOL < 1V 1, 2 1, 2 o +125 C 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA +25oC, +125oC, - 2 V -55oC Input Voltage High VIH Propagation Delay TPHL TPLH VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V 7-668 1, 2 +25oC, +125oC, -55oC 8 - V 1, 2, 3 +25oC - 60 ns 1, 2, 3 +25oC - 50 ns Specifications CD4007UBMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Transition Time TTHL TTLH Input Capacitance CONDITIONS VDD = 10V VDD = 15V CIN Any Input NOTES TEMPERATURE MIN MAX UNITS 1, 2, 3 +25oC - 100 ns o 1, 2, 3 +25 C - 80 ns 1, 2 +25oC - 15.0 pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL Supply Current IDD N Threshold Voltage VNTH N Threshold Voltage Delta ∆VNTH P Threshold Voltage VPTH P Threshold Voltage Delta ∆VPTH Functional F CONDITIONS NOTES TEMPERATURE UNITS 1, 4 +25 C - 2.5 µA 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND TPHL TPLH MAX VDD = 10V, ISS = -10µA VDD = 3V, VIN = VDD or GND Propagation Delay Time MIN VDD = 20V, VIN = VDD or GND o VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - SSI IDD ±0.1µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Final Test Group A Group B 7-669 READ AND RECORD IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Specifications CD4007UBMS TABLE 6. APPLICABLE SUBGROUPS (Continued) CONFORMANCE GROUP Group D MIL-STD-883 METHOD GROUP A SUBGROUPS Sample 5005 1, 2, 3, 8A, 8B, 9 READ AND RECORD Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 1, 5, 8, 12, 13 3, 4, 6, 7, 9, 10 2, 11, 14 Static Burn-In 2 Note 1 1, 5, 8, 12, 13 4, 7, 9 2, 3, 6, 10, 11, 14 Dynamic BurnIn Note 1 - 4, 7, 9 2, 11, 14 1, 5, 8, 12, 13 4, 7, 9 2, 3, 6, 10, 11, 14 Irradiation Note 2 9V ± -0.5V 50kHz 25kHz 1, 5, 8, 12, 13 3, 6, 10 - NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ±5%, VDD = 18V ±0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ±0.5V Schematic Diagram 2 14 D2 * D2 R1 D2 6 ** 13 8 D1 D1 *CMOS INPUT PROTECTION NETWORK D2 Q1 3 R1 D2 ** * 1 Q2 10 5 D1 D1 D1 D1 D1 D2 D2 R1 D1 D2 VDD 4 R2 D2 OUTPUT TERMINAL D1 ** D1 12 Q3 D1 D1 ** D1 D1 7 ** D2 D2 **CMOS OUTPUT PROTECTION NETWORK BETWEEN TERMINAL NOS. 1, 2, 4, 5, 8, 9, 11, 12, 13 AND THE CORRESPONDING DRAINS AND/OR SOURCES 11 D2 D2 * ** PARASITIC AND NETWORK COMPONENTS D1 = N+ TO P WELL D2 = P+ TO SUBSTRATE R1 = 1 - 5 KΩ R2 = 15 - 30Ω 9 ** D1 VSS FIGURE 1. DETAILED SCHEMATIC DIAGRAM OF CD4007UBMS SHOWING INPUT, OUTPUT, AND PARASITIC DIODES 7-670 CD4007UBMS Logic Circuits 6 8 (14, 2, 11); (8, 13); (1, 5); (7, 4, 9) 3 10 5 6 3 10 6 3 12 10 (13, 2); (1, 11); (12, 5, 8); (7, 4, 9) 12 a) TRIPLE INVERTERS 12 (1, 12, 13); (2, 14, 11); (4, 8); (5, 9) b) 3 - INPUT NOR GATE c) 3 - INPUT NAND GATE VDD VDD # B A A 10 OUT C B 12 3 OUT A C B OUT (VDD) = C + AB OUT (VSS) = CA + CB C 6 VSS #ALL P- UNIT SUBSTRATES ARE CONNECTED TO VDD ALL N- UNIT SUBSTRATES ARE CONNECTED TO VSS (13, 12, 5); (4, 9, 8); (14, 2); (1, 11) VSS d) TREE (RELAY) LOGIC VDD (OPTIONAL VDD PULL-UP) VDD (6, 3, 10); (13, 1, 12); (14, 2, 11); (7, 9) 12 6 6 12 (6, 3, 10); (8, 5, 12); (11, 14); (7, 4, 9) (OPTIONAL VSS PULL-DOWN) VSS VSS e) HIGH SINK-CURRENT DRIVER f) HIGH SOURCE-CURRENT DRIVER VDD 6 2 OUT1 (IN1) 4 OUT2 (IN2) TG1 CLOCK IN (OUT) 12 12 6 TG2 (6, 3, 10); (14, 2, 11); (7, 4, 9); (13, 8, 1, 5, 12) (1, 5, 12); (2, 9); (11, 4); (8, 13, 10); (6, 3) VSS g) HIGH SINK - AND SOURCE-CURRENT DRIVER h) DUAL BI-DIRECTIONAL TRANSMISSION GATING FIGURE 2. SAMPLE CMOS LOGIC CIRCUIT ARRANGEMENTS USING TYPE CD4007UBMS 7-671 CD4007UBMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC A - SINGLE INPUT ONLY B - TWO INPUTS ONLY C - THREE INPUTS * OTHER INPUT SWITCHES TO VDD VI SUPPLY VOLTAGE (VDD) = 15V 16 14 12 A B C 10V VO 10 8 5V 6 4 VI * OUTPUT VOLTAGE (VO) (V) OUTPUT VOLTAGE (VO) (V) AMBIENT TEMPERATURE (TA) = +25oC A B C VDD 0 10 8 6 2 2.5 5.0 7.5 10 12.5 INPUT VOLTAGE (VI) (V) 15 0 A - SINGLE INPUT ONLY B - TWO INPUTS ONLY C - THREE INPUTS * OTHER INPUT 2.5 5.0 7.5 10.0 12.5 INPUT VOLTAGE (VI) (V) * 15.0 FIGURE 4. TYPICAL VOLTAGE-TRANSFER CHARACTERISTICS FOR NOR GATE AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC 30 OUTPUT VOLTAGE (VO) (V) GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 12.5 10V 10.0 7.5 5V 5.0 2.5 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 0 FIGURE 5. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 14 11 VDD 12.5 12.5 VI 10 VO 10 10.0 15 7.5 12 7 5 9 ID 5.0 10.0 VO ID 7.5 5.0 10 TERM 3 & 6 TO GND 2.5 SUPPLY MILLIAMPERES (ID) SUPPLY VOLTAGE (VDD) = 15V 2.5 5 0 2.5 2.5 5.0 7.5 10.0 12.5 INPUT VOLTAGE (VI) (V) 15.0 FIGURE 6. MINIMUM AND MAXIMUM VOLTAGE-TRANSFER CHARACTERISTICS FOR INVERTER AMBIENT TEMPERATURE (TA) = +25oC 15.0 VO 15.0 5V 0 VI SUPPLY VOLTAGE (VDD) = 15V 5.0 7.5 10.0 12.5 15.0 INPUT VOLTAGE (VI) (V) OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) A B C 10V A B C 5V A B C 12 4 FIGURE 3. TYPICAL VOLTAGE-TRANSFER CHARACTERISTICS FOR NAND GATE OUTPUT VOLTAGE (VO) (V) 14 C B A 2 VO SUPPLY VOLTAGE (VDD) = 15V 16 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 FIGURE 7. TYPICAL CURRENT AND VOLTAGE-TRANSFER CHARACTERISTICS FOR INVERTER 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 8. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 7-672 CD4007UBMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 -30 OUTPUT VOLTAGE (VO) (V) -5 -10V TA -55oC 10V -55oC 125oC 5V 5 -55oC 125oC 0 5 10 15 INPUT VOLTAGE (VI) (V) DISSIPATION PER GATE (PD) (µW) TRANSITION TIME (fTHL, fTLH) (ns) SUPPLY VOLTAGE (VDD) = 5V 100 10V 0 0 5V 20 SUPPLY VOLTAGE (VDD) = 5V 80 60 10V 40 15V 20 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) AMBIENT TEMPERATURE (TA) = +25oC 200 50 100 FIGURE 12. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE AMBIENT TEMPERATURE (TA) = +25oC 150 AMBIENT TEMPERATURE (TA) = +25oC 0 FIGURE 11. TYPICAL VOLTAGE-TRANSFER CHARACTERISTICS AS A FUNCTION OF TEMPERATURE -15 FIGURE 10. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS =125oC 10 -10 -15V SUPPLY VOLTAGE (VDD) = 15V 15 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V PROPAGATION DELAY TIME (tPLH, tPHL) (ns) FIGURE 9. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 (Continued) SUPPLY VOLTAGE (VDD) = 15V 104 10V 103 10V 5V 102 10 LOAD CAPACITANCE (CL) = 15pF (CL) = 50pF 1 2 4 68 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 13. TYPICAL TRANSISTION TIME vs LOAD CAPACITANCE 105 102 103 2 4 68 2 4 68 2 4 68 2 4 68 104 105 106 INPUT FREQUENCY (fi) (Hz) 107 FIGURE 14. TYPICAL DISSIPATION vs FREQUENCY CHARACTERISTICS 7-673 2 4 68 CD4007UBMS Chip Dimension and Pad Layout Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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