ISL24020 ¬ Data Sheet October 2, 2008 Low Cost, 60MHz Rail-to-Rail Input-Output Op-Amp FN6735.0 Features • Pb-free (RoHS compliant) The ISL24020 is a low power, high voltage rail-to-rail inputoutput amplifier. Operating on supplies ranging from 5V to 15V, while consuming only 2.5mA per amplifier, the ISL24020 has a bandwidth of 60MHz (-3dB). It also provides common mode input ability beyond the supply rails, as well as rail-to-rail output capability. This enables the amplifier to offer maximum dynamic range at any supply voltage. • 60MHz (-3dB) bandwidth • Supply voltage = 4.5V to 16.5V • Low supply current (per amplifier) = 2.5mA • High slew rate = 75V/µs • Unity-gain stable The ISL24020 also features fast slewing and settling times, as well as a high output drive capability of 65mA (sink and source). These features make the ISL24020 ideal for high speed filtering and signal conditioning application. Other applications include battery power, portable devices, and anywhere low power consumption is important. • Beyond the rails input capability The ISL24020 is available in 5 Ld TSOT package. It features a standard operational amplifier pinout and operats over a temperature range of -40°C to +85°C. • TFT-LCD panels Ordering Information • Data acquisition PART NUMBER ISL24020IHTZ-T7* (Note) PART MARKING BCBA PKG. DWG. # PACKAGE 5 Ld TSOT (Pb-free) • Rail-to-rail output swing • ±180mA output short current Applications • VCOM amplifiers • Drivers for A/D converters • Video processing • Audio processing MDP0049 • Active filters *Please refer to TB347 for details on reel specifications. • Test equipment NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • Battery-powered applications • Portable equipment Pinout ISL24020 (5 LD TSOT) TOP VIEW VOUT 1 VS- 2 VIN+ 3 1 5 VS+ + 4 VIN- CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL24020 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 65mA Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Thermal Resistance (Typical, Note 1) θJA (°C/W) 5 Lead TSOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 1kΩ to 0V, TA = +25°C, Unless Otherwise Specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 3 15 mV INPUT CHARACTERISTICS VOS Input Offset Voltage TCVOS Average Offset Voltage Drift (Note 2) IB Input Bias Current RIN Input Impedance 1 GΩ CIN Input Capacitance 2 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio for VIN from -5.5V to 5.5V 50 70 dB AVOL Open-Loop Gain -4.5V ≤ VOUT ≤ 4.5V 62 70 dB VCM = 0V 7 VCM = 0V 2 -5.5 µV/°C 60 nA +5.5 V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = 5mA ISC IOUT -4.92 4.85 -4.85 V 4.92 V Short-Circuit Current ±180 mA Output Current ±65 mA 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from ±2.25V to ±7.75V IS Supply Current No load 2.5 60 4.5 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 3) -4.0V ≤ VOUT ≤ 4.0V, 20% to 80% 75 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 80 ns BW -3dB Bandwidth 60 MHz GBWP Gain-Bandwidth Product 32 MHz PM Phase Margin 50 ° dG Differential Gain (Note 4) RF = RG = 1kΩ and VOUT = 1.4V 0.17 % dP Differential Phase (Note 4) RF = RG = 1kΩ and VOUT = 1.4V 0.24 ° NOTES: 2. Measured over operating temperature range. 3. Slew rate is measured on rising and falling edges. 4. NTSC signal generator used. 2 FN6735.0 October 2, 2008 ISL24020 Typical Performance Curves 25 VS = ±5V TA = +25°C TYPICAL PRODUCTION DISTRIBUTION 400 300 200 100 VS = ±5V QUANTITY (AMPLIFIERS) 15 10 5 21 19 17 15 11 13 9 INPUT OFFSET VOLTAGE DRIFT, TCVOS (µV/°C) FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE 2. INPUT OFFSET VOLTAGE DRIFT 2.0 0.008 VS = ±5V INPUT BIAS CURRENT (µA) INPUT OFFSET VOLTAGE (mV) 7 1 12 8 10 6 4 2 -0 -2 -4 -6 -8 -10 -12 INPUT OFFSET VOLTAGE (mV) 5 0 0 1.5 1.0 0.5 0.0 -0.5 -50 -10 30 70 110 0.004 0.000 -0.004 -0.008 -0.012 -50 150 -10 TEMPERATURE (°C) 70 110 150 FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE 4.96 4.94 4.92 4.90 4.88 -10 30 70 110 150 TEMPERATURE (°C) FIGURE 5. OUTPUT HIGH VOLTAGE vs TEMPERATURE 3 OUTPUT LOW VOLTAGE (V) -4.85 VS = ±5V IOUT = 5mA 4.86 -50 30 TEMPERATURE (°C) FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE OUTPUT HIGH VOLTAGE (V) TYPICAL PRODUCTION DISTRIBUTION 20 3 QUANTITY (AMPLIFIERS) 500 VS = ±5V IOUT = 5mA -4.87 -4.89 -4.91 -4.93 -4.95 -50 -10 30 70 110 150 TEMPERATURE (°C) FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE FN6735.0 October 2, 2008 ISL24020 Typical Performance Curves (Continued) 78 75 VS = ±5V 77 SLEW RATE (V/µs) OPEN-LOOP GAIN (dB) VS = ±5V RL = 1kΩ 70 65 76 75 74 73 60 -50 -10 30 70 110 72 -50 150 -10 110 150 FIGURE 8. SLEW RATE vs TEMPERATURE 2.9 2.70 TA = +25°C VS = ±5V 2.7 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 70 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 7. OPEN-LOOP GAIN vs TEMPERATURE 2.5 2.3 2.1 1.9 1.7 1.5 4 8 12 16 2.65 2.60 2.55 2.50 2.45 2.40 -50 20 -10 30 70 110 150 TEMPERATURE (°C) SUPPLY VOLTAGE (V) FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs TEMPERATURE 0.00 0.30 DIFFERENTIAL PHASE (°) -0.02 DIFFERENTIAL GAIN (%) 30 -0.04 -0.06 -0.08 -0.10 -0.12 VS = ±5V AV = 2 RL = 1kΩ -0.14 -0.16 -0.18 0.25 0.20 0.15 0.10 0.05 0.00 0 100 IRE FIGURE 11. DIFFERENTIAL GAIN 4 200 0 100 200 IRE FIGURE 12. DIFFERENTIAL PHASE FN6735.0 October 2, 2008 ISL24020 Typical Performance Curves (Continued) -30 GAIN -60 2nd HD -70 -80 40 4 6 8 10 -20 1k 10 10k 100k VOP-P (V) VS = ±5V AV = 1 CLOAD = 0pF 1kΩ 1 560Ω -3 150Ω -5 100k 1M 10M 1000pF 15 47pF 10pF -5 -15 VS = ±5V AV = 1 RL = 1kΩ 1M 100M FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS CL MAXIMUM OUTPUT SWING (VP-P) OUTPUT IMPEDANCE (Ω) 350 300 250 200 150 100 50 10M 100M FREQUENCY (Hz) FIGURE 17. CLOSED LOOP OUTPUT IMPEDANCE 5 10M FREQUENCY (Hz) 400 1M 100pF 5 FREQUENCY (Hz) 100k -50 100M 25 -25 100k 100M FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS RL 0 10k 10M FIGURE 14. OPEN LOOP GAIN AND PHASE MAGNITUDE (NORMALIZED) (dB) MAGNITUDE (NORMALIZED) (dB) 5 -1 1M FREQUENCY (Hz) FIGURE 13. HARMONIC DISTORTION vs VOP-P 3 70 0 -90 2 PHASE 20 3rd HD 0 130 PHASE (°) -50 190 60 GAIN (dB) -40 DISTORTION (dB) 250 80 VS = ±5V AV = 2 RL = 1kΩ FREQ = 1MHz 12 10 8 6 4 2 VS = ±5V AV = 1 RL = 1kΩ DISTORTION <1% 0 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 18. MAXIMUM OUTPUT SWING vs FREQUENCY FN6735.0 October 2, 2008 ISL24020 Typical Performance Curves (Continued) -15 -80 PSRR+ -25 PSRR- PSRR (dB) CMRR (dB) -60 -35 -45 -40 -20 -55 VS = ±5V TA = +25°C -65 1k 10k 100k 1M 10M 0 100 100M 1k 10k FREQUENCY (Hz) 1M 10M FREQUENCY (Hz) FIGURE 19. CMRR FIGURE 20. PSRR 1K 100 80 OVERSHOOT (%) VOLTAGE NOISE (nV/√Hz) 100k 100 10 VS = ±5V AV = 1 RL = 1kΩ VIN = ±50mV TA = +25°C 60 40 20 1 100 1k 10k 100k 1M 10M 0 10 100M 100 FREQUENCY (Hz) 1k LOAD CAPACITANCE (pF) FIGURE 21. INPUT VOLTAGE NOISE SPECTRAL DENSITY FIGURE 22. SEPARATIONSMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE 5 4 STEP SIZE (V) 3 VS = ±5V AV = 1 RL = 1kΩ 0.1% 2 1 0 -1 -2 0.1% -3 -4 -5 55 65 75 85 95 105 SETTLING TIME (ns) FIGURE 23. SETTLING TIME vs STEP SIZE 6 FN6735.0 October 2, 2008 ISL24020 Typical Performance Curves (Continued) VS = ±5V TA = +25°C AV = 1 RL = 1kΩ VS = ±5V TA = +25°C AV = 1 RL = 1kΩ 100mV STEP 1V STEP 50ns/DIV 50ns/DIV FIGURE 24. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 25. SMALL SIGNAL TRANSIENT RESPONSE Pin Descriptions ISL24020 (TSOT-5) NAME 1 VOUT FUNCTION EQUIVALENT CIRCUIT Amplifier A output VS+ GND VS- CIRCUIT 1 2 VS- Negative power supply 3 VIN+ Amplifier A non-inverting input 4 VIN- Amplifier A inverting input (Reference Circuit 2) VS+ VS- CIRCUIT 2 5 VS+ Positive power supply 7 FN6735.0 October 2, 2008 ISL24020 Applications Information Output Phase Reversal Product Description The ISL24020 voltage feedback amplifier is fabricated using a high voltage CMOS process. It exhibits rail-to-rail input and output capability, is unity gain stable and has low power consumption (2.5mA). These features make the ISL24020 ideal for a wide range of general-purpose applications. Connected in voltage follower mode and driving a load of 1kΩ, the ISL24020 has a -3dB bandwidth of 60MHz while maintaining a 75V/µs slew rate. The ISL24020 is immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 27 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. VS = ±2.5V, TA = +25°C, AV = 1, VIN = 6VP-P Operating Voltage, Input, and Output 1V The ISL24020 is specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most ISL24020 specifications are stable over both the full supply range and operating temperatures of -40°C to +85°C. Parameter variations with operating voltage and/or temperature are shown in the “Typical Performance Curves” on page 3. The input common-mode voltage range of the ISL24020 extends 500mV beyond the supply rails. The output swings of the ISL24020 typically extend to within 100mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 26 shows the input and output waveforms for the device in the unity-gain configuration. Operation is from ±5V supply with a 1kΩ load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.8VP-P. VS = ±5V, TA = +25°C, AV = 1, VIN = 10VP-P OUTPUT 5V 1V FIGURE 27. OPERATION WITH BEYOND-THE-RAILS INPUT Power Dissipation With the high-output drive capability of the ISL24020 amplifier, it is possible to exceed the +125°C 'absolute-maximum junction temperature' under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: 10µs INPUT 5V 10µs T JMAX – T AMAX P DMAX = --------------------------------------------θ JA (EQ. 1) where: • TJMAX = Maximum junction temperature • TAMAX = Maximum ambient temperature • ΘJA = Thermal resistance of the package FIGURE 26. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT Short Circuit Current Limit The ISL24020 will limit the short circuit current to ±180mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds ±65mA. This limit is set by the design of the internal metal interconnects. • PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: P DMAX = Σi [ V S × I SMAX + ( V S + – V OUT i ) × I LOAD i ] (EQ. 2) when sourcing, and: P DMAX = Σi [ V S × I SMAX + ( V OUT i – V S - ) × I LOAD i ] (EQ. 3) when sinking. 8 FN6735.0 October 2, 2008 ISL24020 Where: • i = 1 to 2 for dual and 1 to 4 for quad • VS = Total supply voltage • ISMAX = Maximum supply current per amplifier • VOUTi = Maximum output voltage of the application • ILOADi = Load current If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. Unused Amplifiers It is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground plane. 9 Power Supply Bypassing and Printed Circuit Board Layout The ISL24020 can provide gain at high frequency. As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1µF ceramic capacitor should be placed from VS+ to pin to VS- pin. A 4.7µF tantalum capacitor should then be connected in parallel, placed in the region of the amplifier. One 4.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. FN6735.0 October 2, 2008 ISL24020 TSOT Package Family MDP0049 e1 D TSOT PACKAGE FAMILY A MILLIMETERS 6 N SYMBOL 4 E1 2 E 3 0.15 C D 2X 1 5 2 (N/2) 0.25 C 2X N/2 TIPS e ddd M B C A-B D b NX 0.15 C A-B 1 3 D 2X TSOT5 TSOT6 TSOT8 TOLERANCE A 1.00 1.00 1.00 Max A1 0.05 0.05 0.05 ±0.05 A2 0.87 0.87 0.87 ±0.03 b 0.38 0.38 0.29 ±0.07 c 0.127 0.127 0.127 +0.07/-0.007 D 2.90 2.90 2.90 Basic E 2.80 2.80 2.80 Basic E1 1.60 1.60 1.60 Basic e 0.95 0.95 0.65 Basic e1 1.90 1.90 1.95 Basic L 0.40 0.40 0.40 ±0.10 L1 0.60 0.60 0.60 Reference ddd 0.20 0.20 0.13 - N 5 6 8 Reference Rev. B 2/07 C A2 SEATING PLANE 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.15mm maximum per side are not included. A1 0.10 C NOTES: NX 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. (L1) 5. Index area - Pin #1 I.D. will be located within the indicated zone (TSOT6 AND TSOT8 only). H A GAUGE PLANE c L 6. TSOT5 version has no center lead (shown as a dashed line). 0.25 4¬¨Ðó All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN6735.0 October 2, 2008