MICROCHIP PIC16LF1902

PIC16LF1902/3
Data Sheet
28-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
LCD Driver and nanoWatt XLP Technology
 2011 Microchip Technology Inc.
Preliminary
DS41455A
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•
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•
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
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FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-822-1
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41455A-page 2
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
28-Pin Flash-Based, 8-Bit CMOS MCUs with LCD Driver and
nanoWatt XLP Technology
High-Performance RISC CPU:
PIC16LF1902/3 Low-Power Features:
• C Compiler Optimized Architecture
• Only 49 Instructions
• Up to 7 Kbytes Self-Write/Read Flash Program
Memory Addressing
• Up to 256 Bytes Data Memory Addressing
• Operating Speed:
- DC – 20 MHz clock input @ 3.6V
- DC – 16 MHz clock input @ 1.8V
- DC – 200 ns instruction cycle
• Interrupt Capability with Automatic Context
Saving
• 16-Level Deep Hardware Stack with Optional
Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes:
- Two full 16-bit File Select Registers (FSRs)
- FSRs can read program and data memory
• Standby Current:
- 60 nA @ 1.8V, typical
• Operating Current:
- 7.0 A @ 32 kHz,1.8V, typical
- 150 A @ 1 MHz, 1.8V, typical
• Timer1 Oscillator Current:
- 600 nA @ 32 kHz, 1.8V, typical
• Low-Power Watchdog Timer Current:
- 500 nA @ 1.8V, typical
Flexible Oscillator Structure:
• 16 MHz Internal Oscillator:
- Accurate to ±10%, typical
- Software selectable frequency range from
16 MHz to 31.25 kHz
• 31 kHz Low-Power Internal Oscillator
• Three External Clock modes up to 20 MHz
• Two-Speed Oscillator Start-up
Special Microcontroller Features:
• Operating Voltage Range:
- 1.8V-3.6V
• Self-Programmable under Software Control
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Ultra Low-Power Brown-Out Reset (ULPBOR)
• Extended Watchdog Timer (WDT)
• In-Circuit Serial Programming™ (ICSP™) via
Two Pins
• In-Circuit Debug (ICD) via Two Pins
• Enhanced Low-Voltage Programming (LVP)
• Programmable Code Protection
• Power-Saving Sleep mode
 2011 Microchip Technology Inc.
Analog Features:
• Analog-to-Digital Converter (ADC):
- 10-bit resolution, up to 11 channels
- Conversion available during Sleep
- Dedicated ADC RC oscillator
- Fixed Voltage Reference (FVR) as channel
• Integrated Temperature Indicator
• Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V
and 2.048V output levels
Peripheral Highlights:
• Up to 25 I/O Pins and 1 Input-only Pin:
- High current 25 mA sink/source
- Individually programmable weak pull-ups
- Individually programmable interrupt-onchange (IOC) pins
• Integrated LCD Controller:
- 19 segment pins and 72 total segments
- Variable clock input
- Contrast control
- Internal voltage reference selections
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Dedicated low-power 32 kHz oscillator driver
Preliminary
DS41455A-page 3
PIC16LF1902/3
Device
Program Memory Flash
(words)
SRAM (bytes)
I/Os
10-bit A/D (ch)
Timers
8/16-bit
PIC16LF1902/3 Family Types
PIC16LF1902
2048
128
25
11
1/1
Common Pins
Segment Pins
Total Segments
LCD
4
19
72(1)
PIC16LF1903
4096
256
25
11
1/1
4
19
Note 1: COM3 and SEG15 share a pin, so the total segments are limited to 72 for 28-pin devices.
72(1)
FIGURE 1:
28-PIN PDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16LF1902/3
28-Pin PDIP, SOIC, SSOP
1
28
RB7(1)/SEG13/ICSPDAT
SEG12/AN0/RA0
2
27
RB6(1)/SEG14/ICSPCLK
SEG7/AN1/RA1
3
26
RB5(1)/AN13/COM1
COM2/AN2/RA2
4
25
RB4(1)/AN11/COM0
SEG15/COM3/VREF+/AN3/RA3
5
RB3(1)/AN9/SEG26/VLCD3
SEG4/T0CKI/RA4
6
24
23
SEG5/AN4/RA5
VSS
7
22
RB1(1)/AN10/SEG24/VLCD1
RB0(1)/AN12/INT/SEG0
SEG2/CLKIN/RA7
9
21
RB2(1)/AN8/SEG25/VLCD2
20
VDD
19
VSS
SEG1/CLKOUT/RA6
10
T1CKI/T1OSO/RC0
11
18
RC7/SEG8
T1OSI/RC1
Note 1:
DS41455A-page 4
8
PIC16LF1902/3
VPP/MCLR/RE3
12
17
RC6/SEG9
SEG3/RC2
13
16
RC5/SEG10
SEG6/RC3
14
15
RC4/T1G/SEG11
These pins have interrupt-on-change functionality.
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
FIGURE 2:
28-PIN UQFN PACKAGE DIAGRAM FOR PIC16LF1902/3
RE3/MCLR/VPP
RB7(1)/ICSPDAT/SEG13
RB6(1)/ICSPCLK/SEG14
RB5(1)/AN13/COM1
RB4(1)/AN11/COM0
28
27
26
25
24
23
22
RA1/AN1/SEG7
RA0/AN0/SEG12
28-Pin UQFN
8
9
10
11
12
13
14
PIC16LF1902/3
Note 1:
 2011 Microchip Technology Inc.
21
20
19
18
17
16
15
RB3(1)/AN9/SEG26/VLCD3
RB2(1)/AN8/SEG25/VLCD2
RB1(1)/AN10/SEG24/VLCD1
RB0(1)/AN12/INT/SEG0
VDD
VSS
RC7/SEG8
T1OSI/RC1
SEG3/RC2
SEG6/RC3
SEG11/T1G/RC4
SEG10/RC5
SEG9/RC6
1
2
3
4
5
6
7
T1CKI/T1OSO/RC0
COM2/AN2/RA2
SEG15/COM3/VREF+/AN3/RA3
SEG4/T0CKI/RA4
SEG5/AN4/RA5
VSS
SEG2/CLKIN/RA7
SEG1/CLKOUT/RA6
These pins have interrupt-on-change functionality.
Preliminary
DS41455A-page 5
PIC16LF1902/3
28-Pin DIP/
SOIC/SSOP
28-Pin UQFN
A/D
Timers
LCD
Interrupt
Pull-up
Basic
28-PIN ALLOCATION TABLE (PIC16LF1902/3)
I/O
TABLE 1:
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
2
3
4
5
6
7
10
9
21
22
23
24
25
26
27
28
11
12
13
14
15
16
17
18
27
28
1
2
3
4
7
6
18
19
20
21
22
23
24
25
8
9
10
11
12
13
14
15
AN0
AN1
AN2
AN3/VREF+
—
AN4
—
—
AN12
AN10
AN8
AN9
AN11
AN13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T0CKI
—
—
—
—
—
—
—
—
—
—
—
T1OSO/T1CKI
T1OSI
—
—
T1G
—
—
—
SEG12
SEG7
COM2
SEG15/COM3
SEG4
SEG5
SEG1
SEG2
SEG0
VLCD1/SEG24
VLCD2/SEG25
VLCD3/SEG26
COM0
COM1
SEG14
SEG13
—
—
SEG3
SEG6
SEG11
SEG10
SEG9
SEG8
—
—
—
—
—
—
—
—
INT/IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
Y
Y
Y
Y
Y
Y
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLKOUT
CLKIN
—
—
—
—
—
—
ICSPCLK
ICSPDAT
—
—
—
—
—
—
—
—
RE3
VDD
Vss
1
20
8,19
26
17
5,16
—
—
—
—
—
—
—
—
—
—
—
—
Y(1)
—
—
MCLR/VPP
VDD
VSS
Note 1:
Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
DS41455A-page 6
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13
3.0 Memory Organization ................................................................................................................................................................. 15
4.0 Device Configuration .................................................................................................................................................................. 37
5.0 Resets ........................................................................................................................................................................................ 43
6.0 Oscillator Module........................................................................................................................................................................ 51
7.0 Interrupts .................................................................................................................................................................................... 61
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 73
9.0 Watchdog Timer (WDT) ............................................................................................................................................................. 75
10.0 Flash Program Memory Control ................................................................................................................................................. 79
11.0 I/O Ports ..................................................................................................................................................................................... 93
12.0 Interrupt-on-Change ................................................................................................................................................................. 105
13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 109
14.0 Temperature Indicator .............................................................................................................................................................. 111
15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 113
16.0 Timer0 Module ......................................................................................................................................................................... 127
17.0 Timer1 Module ......................................................................................................................................................................... 131
18.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 143
19.0 In-Circuit Serial Programming™ (ICSP™) ................................................................................................................................ 177
20.0 Instruction Set Summary .......................................................................................................................................................... 181
21.0 Electrical Specifications............................................................................................................................................................ 195
22.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 213
23.0 Development Support............................................................................................................................................................... 215
24.0 Packaging Information.............................................................................................................................................................. 219
Appendix A: Revision History............................................................................................................................................................. 227
Index .................................................................................................................................................................................................. 229
The Microchip Web Site ..................................................................................................................................................................... 233
Customer Change Notification Service .............................................................................................................................................. 233
Customer Support .............................................................................................................................................................................. 233
Reader Response .............................................................................................................................................................................. 234
Product Identification System ............................................................................................................................................................ 235
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 7
PIC16LF1902/3
TO OUR VALUED CUSTOMERS
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS41455A-page 8
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
1.0
DEVICE OVERVIEW
The PIC16LF1902/3 are described within this data
sheet. They are available in 28-pin packages.
Figure 1-1 shows a block diagram of the
PIC16LF1902/3 devices. Table 1-2 shows the pinout
descriptions.
Reference Table 1-1 for peripherals available per
device.
Peripheral
PIC16LF1903
DEVICE PERIPHERAL
SUMMARY
PIC16LF1902
TABLE 1-1:
ADC
●
●
Fixed Voltage Reference (FVR)
●
●
LCD
●
●
Temperature Indicator
●
●
Timer0
●
●
Timer1
●
●
Timers
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 9
PIC16LF1902/3
FIGURE 1-1:
PIC16LF1902/3 BLOCK DIAGRAM
Program
Flash Memory
RAM
CLKOUT
PORTA
PORTB
Timing
Generation
CLKIN
PORTC
CPU
INTRC
Oscillator
Figure 2-1
PORTE
MCLR
Note
1:
DS41455A-page 10
LCD
Timer0
Timer1
Temp.
Indicator
ADC
10-Bit
FVR
See applicable chapters for more information on peripherals.
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
TABLE 1-2:
PIC16LF1902/3 PINOUT DESCRIPTION
Name
RA0/AN0/SEG12
RA1/AN1/SEG7
RA2/AN2/COM2
RA3/AN3/VREF+/COM3/SEG15
RA4/T0CKI/SEG4
RA5/AN4/SEG5
RA6/CLKOUT/SEG1
RA7/CLKIN/SEG2
RB0/AN12/INT/SEG0
RB1(1)/AN10/SEG24/VLCD1
RB2(1)/AN8/SEG25/VLCD2
RB3
(1)
/AN9/SEG26/VLCD3
Function
Input
Type
RA0
TTL
AN0
AN
SEG12
—
RA1
TTL
Output
Type
Description
CMOS General purpose I/O.
—
A/D Channel 0 input.
AN
LCD Analog output.
CMOS General purpose I/O.
AN1
AN
—
A/D Channel 1 input.
SEG7
—
AN
LCD Analog output.
RA2
TTL
AN2
AN
CMOS General purpose I/O.
—
A/D Channel 2 input.
COM2
—
AN
LCD Analog output.
RA3
TTL
CMOS General purpose I/O.
AN3
AN
—
A/D Channel 3 input.
VREF+
AN
—
A/D Voltage Reference input.
COM3
—
AN
LCD Analog output.
SEG15
—
AN
LCD Analog output.
RA4
TTL
T0CKI
ST
SEG4
—
RA5
TTL
CMOS General purpose I/O.
—
Timer0 clock input.
AN
LCD Analog output.
CMOS General purpose I/O.
AN4
AN
—
A/D Channel 4 input.
SEG5
—
AN
LCD Analog output.
RA6
TTL
CLKOUT
—
SEG1
—
CMOS General purpose I/O.
CMOS FOSC/4 output.
AN
LCD Analog output.
RA7
TTL
CLKIN
CMOS
CMOS General purpose I/O.
—
External clock input (EC mode).
SEG2
—
AN
LCD Analog output.
RB0
TTL
AN12
AN
CMOS General purpose I/O.
—
INT
ST
—
External interrupt.
SEG0
—
AN
LCD Analog output.
A/D Channel 12 input.
RB1
TTL
AN10
AN
CMOS General purpose I/O.
—
SEG24
—
AN
LCD Analog output.
VLCD1
AN
—
LCD analog input.
RB2
TTL
AN8
AN
—
A/D Channel 8 input.
SEG25
—
AN
LCD Analog output.
VLCD2
AN
—
LCD analog input.
RB3
TTL
AN9
AN
—
SEG26
—
AN
LCD Analog output.
VLCD3
AN
—
LCD analog input.
A/D Channel 10 input.
CMOS General purpose I/O.
CMOS General purpose I/O.
A/D Channel 9 input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal
levels
Note 1: These pins have interrupt-on-change functionality.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 11
PIC16LF1902/3
TABLE 1-2:
PIC16LF1902/3 PINOUT DESCRIPTION (CONTINUED)
Name
RB4(1)/AN11/COM0
RB5(1)/AN13/COM1
RB6(1)/ICSPCLK/SEG14
RB7
(1)
/ICSPDAT/SEG13
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/SEG3
RC3/SEG6
RC4/T1G/SEG11
RC5/SEG10
RC6/SEG9
RC7/SEG8
RE3/MCLR/VPP
Function
Input
Type
Output
Type
Description
RB4
TTL
AN11
AN
CMOS General purpose I/O.
—
A/D Channel 11 input.
COM0
—
AN
LCD Analog output.
RB5
TTL
AN13
AN
CMOS General purpose I/O.
—
A/D Channel 13 input.
AN
LCD Analog output.
COM1
—
RB6
TTL
ICSPCLK
ST
—
Serial Programming Clock.
SEG14
—
AN
LCD Analog output.
CMOS General purpose I/O.
RB7
TTL
CMOS General purpose I/O.
ICSPDAT
ST
CMOS ICSP™ Data I/O.
SEG13
—
AN
RC0
TTL
T1OSO
XTAL
XTAL
T1CKI
ST
—
RC1
TTL
T1OSI
XTAL
RC2
TTL
SEG3
—
RC3
TTL
SEG6
—
RC4
TTL
T1G
XTAL
SEG11
—
RC5
TTL
SEG10
—
RC6
ST
SEG9
—
RC7
ST
SEG8
—
RE3
TTL
LCD Analog output.
CMOS General purpose I/O.
Timer1 oscillator connection.
Timer1 clock input.
CMOS General purpose I/O.
XTAL
Timer1 oscillator connection.
CMOS General purpose I/O.
AN
LCD Analog output.
CMOS General purpose I/O.
AN
LCD Analog output.
CMOS General purpose I/O.
XTAL
AN
Timer1 oscillator connection.
LCD Analog output.
CMOS General purpose I/O.
AN
LCD Analog output.
CMOS General purpose I/O.
AN
LCD Analog output.
CMOS General purpose I/O.
AN
LCD Analog output.
CMOS General purpose I/O.
MCLR
ST
—
Master Clear with internal pull-up.
VPP
HV
—
Programming voltage.
VDD
VDD
Power
—
Positive supply.
VSS
VSS
Power
—
Ground reference.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal
levels
Note 1: These pins have interrupt-on-change functionality.
DS41455A-page 12
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
2.0
ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
•
•
•
•
Automatic Interrupt Context Saving
16-level Stack with Overflow and Underflow
File Select Registers
Instruction Set
2.1
Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.
2.2
16-level Stack with Overflow and
Underflow
These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a software Reset. See Section 3.4 “Stack” for more details.
2.3
File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.5 “Indirect Addressing” for more details.
2.4
Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 20.0 “Instruction Set Summary” for more
details.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 13
PIC16LF1902/3
FIGURE 2-1:
CORE BLOCK DIAGRAM
15
Configuration
15
MUX
Flash
Program
Memory
Program
Bus
16-Level
8 Level Stack
Stack
(13-bit)
(15-bit)
14
Instruction
Instruction Reg
reg
8
Data Bus
Program Counter
RAM
Program Memory
Read (PMR)
12
RAM Addr
Addr MUX
Indirect
Addr
12
12
Direct Addr 7
5
BSR
FSR Reg
reg
15
FSR0reg
Reg
FSR
FSR1
Reg
FSR reg
15
STATUS Reg
reg
STATUS
8
3
Power-up
Timer
CLKIN
CLKOUT
Instruction
Decodeand
&
Decode
Control
Timing
Generation
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
MUX
ALU
8
W Reg
Internal
Oscillator
Block
VDD
DS41455A-page 14
VSS
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
3.0
MEMORY ORGANIZATION
3.1
These devices contain the following types of memory:
• Program Memory
- Configuration Words
- Device ID
- User ID
- Flash Program Memory
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
Program Memory Organization
The enhanced mid-range core has a 15-bit program
counter capable of addressing 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC16LF1902/3 family. Accessing a
location above these boundaries will cause a
wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figures 3-1, and 3-2).
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
• Stack
• Indirect Addressing
TABLE 3-1:
DEVICE SIZES AND ADDRESSES
Device
Program Memory Space (Words)
Last Program Memory Address
PIC16LF1902
2,048
07FFh
PIC16LF1903
4,096
0FFFh
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 15
PIC16LF1902/3
FIGURE 3-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC16LF1902
FIGURE 3-2:
PC<14:0>
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
On-chip
Program
Memory
PROGRAM MEMORY MAP
AND STACK FOR
PIC16LF1903
PC<14:0>
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
15
Stack Level 0
Stack Level 1
Stack Level 0
Stack Level 1
Stack Level 15
Stack Level 15
Reset Vector
0000h
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Interrupt Vector
0004h
0005h
Page 0
Rollover to Page 0
Wraps to Page 0
07FFh
0800h
On-chip
Program
Memory
Page 0
07FFh
0800h
Page 1
Rollover to Page 0
Wraps to Page 0
0FFFh
1000h
Wraps to Page 0
Rollover to Page 0
DS41455A-page 16
7FFFh
Preliminary
Rollover to Page 1
7FFFh
 2011 Microchip Technology Inc.
PIC16LF1902/3
3.1.1
READING PROGRAM MEMORY AS
DATA
There are two methods of accessing constants in program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.1.1.1
RETLW Instruction
The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
EXAMPLE 3-1:
constants
BRW
RETLW
RETLW
RETLW
RETLW
DATA0
DATA1
DATA2
DATA3
RETLW INSTRUCTION
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
constants
RETLW DATA0
;Index0 data
RETLW DATA1
;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW
LOW constants
MOVWF
FSR1L
MOVLW
HIGH constants
MOVWF
FSR1H
MOVIW 0[INDF1]
;THE PROGRAM MEMORY IS IN W
;Add Index in W to
;program counter to
;select data
;Index0 data
;Index1 data
my_function
;… LOTS OF CODE…
MOVLW
DATA_INDEX
call constants
;… THE CONSTANT IS IN W
The BRW instruction makes this type of table very simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
3.1.1.2
Indirect Read with FSR
The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the program memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.
The HIGH directive will set bit<7> if a label points to a
location in program memory.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 17
PIC16LF1902/3
3.2
3.2.1
Data Memory Organization
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-3):
•
•
•
•
12 core registers
20 Special Function Registers (SFR)
Up to 80 bytes of General Purpose RAM (GPR)
16 bytes of common RAM
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Table 3-2. For for detailed
information, see Table 3-4.
TABLE 3-2:
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect
Addressing” for more information.
Data Memory uses a 12-bit address. The upper 7-bit of
the address define the Bank address and the lower
5-bits select the registers/RAM in that bank.
DS41455A-page 18
CORE REGISTERS
Preliminary
CORE REGISTERS
Addresses
BANKx
x00h or x80h
x01h or x81h
x02h or x82h
x03h or x83h
x04h or x84h
x05h or x85h
x06h or x86h
x07h or x87h
x08h or x88h
x09h or x89h
x0Ah or x8Ah
x0Bh or x8Bh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
 2011 Microchip Technology Inc.
PIC16LF1902/3
3.2.1.1
STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 3-1:
U-0
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 20.0
“Instruction Set Summary”).
Note:
The C and DC bits operate as Borrow and
Digit Borrow out bits, respectively, in
subtraction.
STATUS: STATUS REGISTER
U-0
—
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
—
U-0
R-1/q
R-1/q
R/W-0/u
R/W-0/u
R/W-0/u
—
TO
PD
Z
DC(1)
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-5
Unimplemented: Read as ‘0’
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 19
PIC16LF1902/3
3.2.2
SPECIAL FUNCTION REGISTER
FIGURE 3-3:
The Special Function Registers (FSRs) are registers
used by the application to control the desired operation
of peripheral functions in the device. The Special
Function Registers occupy the 20 bytes after the core
registers of every data memory bank (addresses
x0Ch/x8Ch through x1Fh/x9Fh). The registers
associated with the operation of the peripherals are
described in the appropriate peripheral chapter of this
data sheet.
3.2.3
7-bit Bank Offset
0Bh
0Ch
GENERAL PURPOSE RAM
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
1Fh
20h
Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2
“Linear Data Memory” for more information.
3.2.4
Memory Region
00h
There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
3.2.3.1
BANKED MEMORY
PARTITIONING
General Purpose RAM
(80 bytes maximum)
COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
6Fh
70h
Common RAM
(16 bytes)
7Fh
3.2.5
DEVICE MEMORY MAPS
The memory maps for PIC16LF1902
PIC16LF1903 are as shown in Table 3-3.
DS41455A-page 20
Preliminary
and
 2011 Microchip Technology Inc.
 2011 Microchip Technology Inc.
TABLE 3-3:
PIC16LF1902/3 MEMORY MAP
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
Preliminary
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020h
—
General
Purpose
Register
96 Bytes
Core Registers
(Table 3-2)
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
TRISA
TRISB
TRISC
—
—
PIE1
PIE2
—
—
OPTION_REG
PCON
WDTCON
—
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
Core Registers
(Table 3-2)
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
09Fh
—
11Fh
0A0h General Purpose 120h
Register
32 Bytes
13Fh
General Purpose 140h
0EFh
0F0h
Register
48 Bytes(1)
Legend:
Note 1:
0FFh
LATA
LATB
LATC
—
—
—
—
—
—
—
BORCON
FVRCON
—
—
—
—
—
—
—
—
19Fh
1A0h
ANSELA
ANSELB
—
—
—
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
—
—
—
—
—
—
—
—
—
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h
—
WPUB
—
—
WPUE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26Fh
270h
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
—
Core Registers
(Table 3-2)
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
2FFh
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
36Fh
370h
2EFh
2F0h
BANK 7
380h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
27Fh
BANK 6
300h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
1FFh
BANK 5
280h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh
= Unimplemented data memory locations, read as ‘0’.
PIC16LF1903 only.
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
1EFh
1F0h
17Fh
BANK 4
200h
Core Registers
(Table 3-2)
General
Purpose
Register
80 Bytes(1)
16Fh
170h
Accesses
70h – 7Fh
07Fh
BANK 3
180h
—
Unimplemented
Read as ‘0’
3EFh
3F0h
Accesses
70h – 7Fh
37Fh
—
—
—
—
—
—
—
—
IOCBP
IOCBN
IOCBF
—
—
—
—
—
—
—
—
Accesses
70h – 7Fh
3FFh
DS41455A-page 21
PIC16LF1902/3
06Fh
070h
PORTA
PORTB
PORTC
—
PORTE
PIR1
PIR2
—
—
TMR0
TMR1L
TMR1H
T1CON
T1GCON
—
—
—
—
—
BANK 2
100h
PIC16LF1902/3 MEMORY MAP (CONTINUED)
BANK 8
400h
BANK 9
480h
Core Registers
(Table 3-2)
40Bh
40Ch
Unimplemented
Read as ‘0’
46Fh
470h
Common RAM
(Accesses
70h – 7Fh)
47Fh
Core Registers
(Table 3-2)
48Bh
48Ch
4EFh
4F0h
4FFh
BANK 16
800h
Preliminary
80Bh
80Ch
Core Registers
(Table 3-2)Table
3-2
87Fh
Common RAM
(Accesses
70h – 7Fh)
8EFh
8F0h
8FFh
 2011 Microchip Technology Inc.
Legend:
Common RAM
(Accesses
70h – 7Fh)
97Fh
9EFh
9F0h
9FFh
D7Fh
Common RAM
(Accesses
70h – 7Fh)
Common RAM
(Accesses
70h – 7Fh)
= Unimplemented data memory locations, read as ‘0’
A7Fh
DFFh
Common RAM
(Accesses
70h – 7Fh)
77Fh
AEFh
AF0h
AFFh
Unimplemented
Read as ‘0’
B6Fh
B70h
B7Fh
BANK 30
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
F0Bh
F0Ch
Unimplemented
Read as ‘0’
EFFh
Common RAM
(Accesses
70h – 7Fh)
F00h
E8Bh
E8Ch
Common RAM
(Accesses
70h – 7Fh)
Core Registers
(Table 3-2)
B8Bh
B8Ch
B0Bh
B0Ch
Common RAM
(Accesses
70h – 7Fh)
BANK 23
B80h
Core Registers
(Table 3-2)
BANK 29
EEFh
EF0h
Common RAM
(Accesses
70h – 7Fh)
BANK 22
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
E7Fh
76Fh
770h
Unimplemented
Read as ‘0’
B00h
E80h
Common RAM
(Accesses
70h – 7Fh)
70Bh
70Ch
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
E6Fh
E70h
Core Registers
(Table 3-2)
BANK 21
BANK 28
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
A8Bh
A8Ch
E0Bh
E0Ch
Common RAM
(Accesses
70h – 7Fh)
6FFh
Unimplemented
Read as ‘0’
A80h
E00h
Core Registers
(Table 3-2)
DEFh
DF0h
6EFh
6F0h
Unimplemented
Read as ‘0’
BANK 27
D8Bh
D8Ch
68Bh
68Ch
Core Registers
(Table 3-2)
A6Fh
A70h
BANK 14
700h
Core Registers
(Table 3-2)
BANK 20
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
D6Fh
D70h
67Fh
Common RAM
(Accesses
70h – 7Fh)
A0Bh
A0Ch
D80h
D0Bh
D0Ch
66Fh
670h
Unimplemented
Read as ‘0’
A00h
98Bh
98Ch
Common RAM
(Accesses
70h – 7Fh)
60Bh
60Ch
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
BANK 13
680h
Core Registers
(Table 3-2)
BANK 19
BANK 26
Core Registers
(Table 3-2)
CFFh
5FFh
Unimplemented
Read as ‘0’
980h
D00h
Common RAM
(Accesses
70h – 7Fh)
5EFh
5F0h
Unimplemented
Read as ‘0’
BANK 25
CEFh
CF0h
58Bh
58Ch
Core Registers
(Table 3-2)
96Fh
970h
BANK 12
600h
Core Registers
(Table 3-2)
BANK 18
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
C7Fh
57Fh
Common RAM
(Accesses
70h – 7Fh)
90Bh
90Ch
88Bh
88Ch
C8Bh
C8Ch
Common RAM
(Accesses
70h – 7Fh)
56Fh
570h
Unimplemented
Read as ‘0’
900h
C80h
C0Bh
C0Ch
50Bh
50Ch
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
C6Fh
C70h
Common RAM
(Accesses
70h – 7Fh)
BANK 11
580h
Core Registers
(Table 3-2)
BANK 17
BANK 24
C00h
Unimplemented
Read as ‘0’
880h
Unimplemented
Read as ‘0’
86Fh
870h
BANK 10
500h
Unimplemented
Read as ‘0’
F6Fh
F70h
F7Fh
Common RAM
(Accesses
70h – 7Fh)
Unimplemented
Read as ‘0’
BEFh
BF0h
BFFh
Common RAM
(Accesses
70h – 7Fh)
PIC16LF1902/3
DS41455A-page 22
TABLE 3-3:
PIC16LF1902/3
TABLE 3-3:
PIC16LF1902/3 MEMORY MAP (CONTINUED)
Bank 15
780h
Core Registers
(Table 3-2)
78Bh
78Ch
Unimplemented
Read as ‘0’
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Fh
7A0h
7A1h
7A2h
7A3h
7A4h
7A5h
7A6h
7A7h
7A8h
7A9h
7AAh
7ABh
7ACh
7ADh
7AEh
7AFh
7B0h
7B1h
7B2h
7B3h
7B4h
7B5h
7B6h
7B7h
7B8h
LCDCON
LCDPS
LCDREF
LCDCST
LCDRL
—
—
LCDSE0
LCDSE1
—
LCDSE3
Unimplemented
Read as ‘0’
LCDDATA0
LCDDATA1
—
LCDDATA3
LCDDATA4
—
LCDDATA6
LCDDATA7
—
LCDDATA9
LCDDATA10
—
LCDDATA12
—
—
LCDDATA15
—
—
LCDDATA18
—
—
LCDDATA21
—
—
Bank 31
F80h
Core Registers
(Table 3-2)
F8Bh
F8Ch
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
FF0h
FFFh
Unimplemented
Read as ‘0’
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
—
STKPTR
TOSL
TOSH
Common RAM
(Accesses
70h – 7Fh)
Unimplemented
Read as ‘0’
7EFh
Legend:
= Unimplemented data memory locations, read as ‘0’,
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 23
PIC16LF1902/3
3.2.6
CORE FUNCTION REGISTERS
SUMMARY
The Core Function registers listed in Table 3-4 can be
addressed from any Bank.
TABLE 3-4:
Addr
Name
CORE FUNCTION REGISTERS SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
Bank 0-31
x00h or
INDF0
x80h
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx
uuuu uuuu
x01h or
INDF1
x81h
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx
uuuu uuuu
x02h or
PCL
x82h
Program Counter (PC) Least Significant Byte
0000 0000
0000 0000
---1 1000
---q quuu
x03h or
STATUS
x83h
—
—
—
TO
PD
Z
DC
C
x04h or
FSR0L
x84h
Indirect Data Memory Address 0 Low Pointer
0000 0000
uuuu uuuu
x05h or
FSR0H
x85h
Indirect Data Memory Address 0 High Pointer
0000 0000
0000 0000
x06h or
FSR1L
x86h
Indirect Data Memory Address 1 Low Pointer
0000 0000
uuuu uuuu
x07h or
FSR1H
x87h
Indirect Data Memory Address 1 High Pointer
0000 0000
0000 0000
---0 0000
---0 0000
0000 0000
uuuu uuuu
-000 0000
-000 0000
0000 0000
0000 0000
x08h or
BSR
x88h
—
x09h or
WREG
x89h
—
BSR4
BSR3
BSR2
BSR1
BSR0
Working Register
x0Ah or
PCLATH
x8Ah
—
x0Bh or
INTCON
x8Bh
GIE
Legend:
—
Write Buffer for the upper 7 bits of the Program Counter
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
DS41455A-page 24
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
TABLE 3-5:
Addr
Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 0
00Ch PORTA
PORTA Data Latch when written: PORTA pins when read
xxxx xxxx uuuu uuuu
00Dh PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
00Eh PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
00Fh —
Unimplemented
010h PORTE
011h
PIR1
012h PIR2
—
—
—
—
—
TMR1GIF
ADIF
—
—
—
—
—
—
—
RE3
—
—
—
---- x--- ---- u---
—
—
TMR1IF
00-- ---0 0000 ---0
—
LCDIF
—
—
---- -0-- ---- -0--
013h —
Unimplemented
—
—
014h —
Unimplemented
—
—
015h TMR0
Timer0 Module Register
xxxx xxxx uuuu uuuu
016h TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
017h TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
018h T1CON
TMR1CS1 TMR1CS0
019h T1GCON
TMR1GE
01Ah
to —
01Fh
T1GPOL
xxxx xxxx uuuu uuuu
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
—
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
TMR1ON 0000 00-0 uuuu uu-u
T1GSS0
Unimplemented
0000 0x00 uuuu uxuu
—
—
Bank 1
08Ch TRISA
PORTA Data Direction Register
1111 1111 1111 1111
08Dh TRISB
PORTB Data Direction Register
1111 1111 1111 1111
08Eh TRISC
PORTC Data Direction Register
1111 1111 1111 1111
08Fh —
Unimplemented
—
—
—
—
—
—(2)
091h PIE1
TMR1GIE
ADIE
—
—
092h PIE2
—
—
—
—
090h TRISE
—
—
—
—
---- 1--- ---- 1---
—
—
—
TMR1IE
00-- ---0 0000 ---0
—
LCDIE
—
—
---- -0-- ---- -0--
093h —
Unimplemented
—
—
094h —
Unimplemented
—
—
095h OPTION_REG
WPUEN
INTEDG
096h PCON
STKOVF
STKUNF
—
RWDT
RMCLR
RI
POR
—
—
WDTPS4
WDTPS3
WDTPS2
WDTPS1
WDTPS0
—
IRCF3
IRCF2
IRCF1
IRCF0
—
SCS1
SCS0
-011 1-00 -011 1-00
T1OSCR
—
OSTS
HFIOFR
—
—
LFIOFR
HFIOFS
0-q0 --00 q-qq --0q
097h WDTCON
098h —
TMR0CS
TMR0SE
PSA
PS2
09Ah OSCSTAT
A/D Result Register Low
09Ch ADRESH
A/D Result Register High
00-1 11qq qq-q qquu
—
xxxx xxxx uuuu uuuu
—
CHS4
CHS3
CHS2
CHS1
CHS0
09Eh ADCON1
ADFM
ADCS2
ADCS1
ADCS0
—
—
1:
2:
BOR
SWDTEN --01 0110 --01 0110
xxxx xxxx uuuu uuuu
09Dh ADCON0
Note
1111 1111 1111 1111
—
09Bh ADRESL
09Fh —
PS0
Unimplemented
099h OSCCON
Legend:
PS1
GO/DONE
ADON
-000 0000 -000 0000
ADPREF1 ADPREF0 0000 ---- 0000 ----
Unimplemented
—
—
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 25
PIC16LF1902/3
TABLE 3-5:
Addr
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 2
10Ch LATA
PORTA Data Latch
xxxx xxxx uuuu uuuu
10Dh LATB
PORTB Data Latch
xxxx xxxx uuuu uuuu
10Eh LATC
PORTC Data Latch
xxxx xxxx uuuu uuuu
10Fh
to —
115h
Unimplemented
—
—
116h
BORCON
SBOREN
BORFS
—
—
—
—
—
BORRDY 10-- ---q uu-- ---u
117h
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
—
—
ADFVR1
ADFVR0 0q00 --00 0q00 --00
118h
to —
11Fh
Unimplemented
—
—
Bank 3
18Ch ANSELA
—
—
ANSA5
—
ANSA3
ANSA2
ANSA1
ANSA0
--1- 1111 --11 1111
18Dh ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111 --11 1111
18Eh —
Unimplemented
—
—
18Fh —
Unimplemented
—
—
190h —
Unimplemented
—
—
191h PMADRL
Program Memory Address Register Low Byte
192h PMADRH
193h PMDATL
—
0000 0000 0000 0000
Program Memory Address Register High Byte
1000 0000 1000 0000
Program Memory Read Data Register Low Byte
194h PMDATH
—
—
195h PMCON1
—(2)
CFGS
xxxx xxxx uuuu uuuu
Program Memory Read Data Register High Byte
LWLO
196h PMCON2
Program Memory Control Register 2
197h
to —
19Fh
Unimplemented
FREE
WRERR
WREN
--xx xxxx --uu uuuu
WR
RD
1000 x000 1000 q000
0000 0000 0000 0000
—
—
—
—
Bank 4
20Ch —
Unimplemented
20Dh WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
1111 1111 1111 1111
20Eh —
Unimplemented
—
—
20Fh —
Unimplemented
—
—
210h WPUE
211h
to —
21Fh
—
—
—
—
WPUE3
—
—
—
---- 1--- ---- 1---
Unimplemented
—
—
Unimplemented
—
—
Unimplemented
—
—
Bank 5
28Ch —
—
29Fh
Bank 6
30Ch —
—
31Fh
Legend:
Note
1:
2:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
DS41455A-page 26
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
TABLE 3-5:
Addr
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
—
—
Bank 7
38Ch —
—
393h
Unimplemented
394h IOCBP
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
0000 0000 0000 0000
395h IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
0000 0000 0000 0000
396h IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBF0
0000 0000 0000 0000
397h —
—
39Fh
Unimplemented
—
—
Unimplemented
—
—
Unimplemented
—
—
Bank 8-14
x0Ch
or
x8Ch
to —
x1Fh
or
x9Fh
Bank 15
78Ch —
—
790h
LCDEN
SLPEN
WERR
—
CS1
CS0
LMUX1
LMUX0
000- 0011 000- 0011
WFT
BIASMD
LCDA
WA
LP3
LP2
LP1
LP0
0000 0000 0000 0000
793h LCDREF
LCDIRE
—
LCDIRI
—
VLCD3PE
VLCD2PE
VLCD1PE
—
0-0- 000- 0-0- 000-
794h LCDCST
—
—
—
—
—
LCDCST2
LCDCST1 LCDCST0 ---- -000 ---- -000
LRLAP1
LRLAP0
LRLBP1
LRLBP0
—
LRLAT2
791h LCDCON
792h LCDPS
795h LCDRL
LRLAT1
LRLAT0
0000 -000 0000 -000
796h —
Unimplemented
—
—
797h —
Unimplemented
—
—
798h LCDSE0
799h LCDSE1
79Ah —
SE7
SE6
SE5
SE4
SE3
SE2
SE1
SE0
0000 0000 uuuu uuuu
SE15
SE14
SE13
SE12
SE11
SE10
SE9
SE8
0000 0000 uuuu uuuu
—
—
—
SE26
SE25
SE24
---- -000 ---- -uuu
Unimplemented
79Bh LCDSE3
79Dh —
—
79Fh
—
—
—
Unimplemented
—
—
—
7A0h LCDDATA0
SEG7
COM0
SEG6
COM0
SEG5
COM0
SEG4
COM0
SEG3
COM0
SEG2
COM0
SEG1
COM0
SEG0
COM0
xxxx xxxx uuuu uuuu
7A1h LCDDATA1
SEG15
COM0
SEG14
COM0
SEG13
COM0
SEG12
COM0
SEG11
COM0
SEG10
COM0
SEG9
COM0
SEG8
COM0
xxxx xxxx uuuu uuuu
7A2h —
Unimplemented
—
—
7A3h LCDDATA3
SEG7
COM1
SEG6
COM1
SEG5
COM1
SEG4
COM1
SEG3
COM1
SEG2
COM1
SEG1
COM1
SEG0
COM1
xxxx xxxx uuuu uuuu
7A4h LCDDATA4
SEG15
COM1
SEG14
COM1
SEG13
COM1
SEG12
COM1
SEG11
COM1
SEG10
COM1
SEG9
COM1
SEG8
COM1
xxxx xxxx uuuu uuuu
7A5h —
Unimplemented
—
—
7A6h LCDDATA6
SEG7
COM2
SEG6
COM2
SEG5
COM2
SEG4
COM2
SEG3
COM2
SEG2
COM2
SEG1
COM2
SEG0
COM2
xxxx xxxx uuuu uuuu
7A7h LCDDATA7
SEG15
COM2
SEG14
COM2
SEG13
COM2
SEG12
COM2
SEG11
COM2
SEG10
COM2
SEG9
COM2
SEG8
COM2
xxxx xxxx uuuu uuuu
7A8h —
Unimplemented
—
—
7A9h LCDDATA9
SEG7
COM3
SEG6
COM3
SEG5
COM3
SEG4
COM3
SEG3
COM3
SEG2
COM3
SEG1
COM3
SEG0
COM3
xxxx xxxx uuuu uuuu
7AAh LCDDATA10
SEG15
COM3
SEG14
COM3
SEG13
COM3
SEG12
COM3
SEG11
COM3
SEG10
COM3
SEG9
COM3
SEG8
COM3
xxxx xxxx uuuu uuuu
Legend:
Note
1:
2:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 27
PIC16LF1902/3
TABLE 3-5:
Addr
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
—
SEG26
COM0
SEG25
COM0
SEG24
COM0
Value on
POR, BOR
Value on all
other
Resets
—
—
Bank 15 (Continued)
7ABh —
Unimplemented
7ACh LCDDATA12
—
---- -xxx ---- -uuu
7ADh —
Unimplemented
—
—
7AEh —
Unimplemented
—
—
7AFh LCDDATA15
—
—
—
—
—
SEG26
COM1
SEG25
COM1
SEG24
COM1
---- -xxx ---- -uuu
7B0h —
Unimplemented
—
—
7B1h —
Unimplemented
—
—
7B2h LCDDATA18
—
—
—
—
—
SEG26
COM2
SEG25
COM2
SEG24
COM2
---- -xxx ---- -uuu
7B3h —
Unimplemented
—
—
7B4h —
Unimplemented
—
—
7B5h LCDDATA21
7B6h —
—
7EFh
—
—
—
—
—
SEG26
COM3
SEG25
COM3
SEG24
COM3
---- -xxx ---- -uuu
Unimplemented
—
—
Unimplemented
—
—
Unimplemented
—
—
Bank 16-30
x0Ch
or
x8Ch
to —
x1Fh
or
x9Fh
Bank 31
F8Ch —
—
FE3h
FE4h STATUS_SHAD
FE5h WREG_SHAD
FE6h BSR_SHAD
FE7h PCLATH_SHAD
—
—
—
—
—
Z_SHAD
DC_SHAD C_SHAD ---- -xxx ---- -uuu
Working Register Normal (Non-ICD) Shadow
—
—
—
—
xxxx xxxx uuuu uuuu
Bank Select Register Normal (Non-ICD) Shadow
Program Counter Latch High Register Normal (Non-ICD) Shadow
---x xxxx ---u uuuu
-xxx xxxx uuuu uuuu
FE8h FSR0L_SHAD
Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow
xxxx xxxx uuuu uuuu
FE9h FSR0H_SHAD
Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow
xxxx xxxx uuuu uuuu
FEAh FSR1L_SHAD
Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow
xxxx xxxx uuuu uuuu
FEBh FSR1H_SHAD
Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow
xxxx xxxx uuuu uuuu
FECh —
Unimplemented
FEDh STKPTR
FEEh TOSL
Note
1:
2:
—
—
—
Current Stack Pointer
—
—
---1 1111 ---1 1111
Top of Stack Low byte
FEFh TOSH
Legend:
—
xxxx xxxx uuuu uuuu
Top of Stack High byte
-xxx xxxx -uuu uuuu
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
DS41455A-page 28
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
3.3
3.3.3
PCL and PCLATH
COMPUTED FUNCTION CALLS
The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-4 shows the five
situations for the loading of the PC.
A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).
FIGURE 3-4:
If using the CALL instruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
PC
LOADING OF PC IN
DIFFERENT SITUATIONS
14
PCH
6
7
14
PCH
PCL
0
PCLATH
PC
8
ALU Result
PCL
0
4
0
14
11
PCL
0
CALLW
6
PCLATH
PCH
14
7
0
PCH
8
W
PCL
BRW
PCH
BRANCHING
If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRA instruction.
15
14
3.3.4
If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
0
PC + W
PC
The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address.
A computed CALLW is accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.
OPCODE <10:0>
PC
PC
Instruction with
PCL as
Destination
GOTO, CALL
6
PCLATH
0
PCL
0
BRA
15
PC + OPCODE <8:0>
3.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents
of the PCLATH register. This allows the entire contents
of the program counter to be changed by writing the
desired upper 7 bits to the PCLATH register. When the
lower 8 bits are written to the PCL register, all 15 bits of
the program counter will change to the values contained in the PCLATH register and those being written
to the PCL register.
3.3.2
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to
the program counter (ADDWF PCL). When performing a
table read using a computed GOTO method, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to the Application
Note AN556, “Implementing a Table Read” (DS00556).
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 29
PIC16LF1902/3
3.4
3.4.1
Stack
The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is 5 bits to allow detection of
overflow and underflow.
All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 3-3 and 3-3). The stack space is
not part of either program or data space. The PC is
PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The
stack is POPed in the event of a RETURN, RETLW or a
RETFIE instruction execution. PCLATH is not affected
by a PUSH or POP operation.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Word 2). This
means that after the stack has been PUSHed sixteen
times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is
enabled.
Note:
Note:
Care should be taken when modifying the
STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLW and
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIE will decrement STKPTR. At any
time STKPTR can be inspected to see how much stack
is left. The STKPTR always points at the currently used
place on the stack. Therefore, a CALL or CALLW will
increment the STKPTR and then write the PC, and a
return will unload the PC and then decrement the
STKPTR.
There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to an
interrupt address.
FIGURE 3-5:
ACCESSING THE STACK
Reference Figure 3-5 through Figure 3-8 for examples
of accessing the stack.
ACCESSING THE STACK EXAMPLE 1
TOSH:TOSL
0x0F
STKPTR = 0x1F
Stack Reset Disabled
(STVREN = 0)
0x0E
0x0D
0x0C
0x0B
0x0A
Initial Stack Configuration:
0x09
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
TOSH:TOSL
DS41455A-page 30
0x1F
0x0000
Preliminary
STKPTR = 0x1F
Stack Reset Enabled
(STVREN = 1)
 2011 Microchip Technology Inc.
PIC16LF1902/3
FIGURE 3-6:
ACCESSING THE STACK EXAMPLE 2
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
This figure shows the stack configuration
after the first CALL or a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL
FIGURE 3-7:
0x00
Return Address
STKPTR = 0x00
ACCESSING THE STACK EXAMPLE 3
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
will repeatedly place the return addresses
into the Program Counter and pop the stack.
0x0B
0x0A
0x09
0x08
0x07
TOSH:TOSL
 2011 Microchip Technology Inc.
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
Preliminary
STKPTR = 0x06
DS41455A-page 31
PIC16LF1902/3
FIGURE 3-8:
ACCESSING THE STACK EXAMPLE 4
TOSH:TOSL
3.4.2
0x0F
Return Address
0x0E
Return Address
0x0D
Return Address
0x0C
Return Address
0x0B
Return Address
0x0A
Return Address
0x09
Return Address
0x08
Return Address
0x07
Return Address
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
When the stack is full, the next CALL or
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
so the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
STKPTR = 0x10
OVERFLOW/UNDERFLOW RESET
If the STVREN bit in Configuration Word 2 is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.
3.5
Indirect Addressing
The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory
DS41455A-page 32
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
FIGURE 3-9:
INDIRECT ADDRESSING
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x0FFF
0x1000
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR
Address
Range
Reserved
0x7FFF
0x8000
0x0000
Program
Flash Memory
0xFFFF
Note:
0x7FFF
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 33
PIC16LF1902/3
3.5.1
TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.
FIGURE 3-10:
TRADITIONAL DATA MEMORY MAP
Direct Addressing
4
BSR
0
6
Indirect Addressing
From Opcode
0
7
0
Bank Select
Location Select
FSRxH
0
0
0
7
FSRxL
0
0
Bank Select
00000 00001 00010
11111
Bank 0 Bank 1 Bank 2
Bank 31
Location Select
0x00
0x7F
DS41455A-page 34
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
3.5.2
3.5.3
LINEAR DATA MEMORY
The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 3-11:
LINEAR DATA MEMORY
MAP
To make constant data access easier, the entire
program Flash memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower 8 bits of each memory location is accessible via
INDF. Writing to the program Flash memory cannot be
accomplished via the FSR/INDF interface. All
instructions that access program Flash memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.
FIGURE 3-12:
7
7
FSRnH
0
7
FSRnL
0
PROGRAM FLASH MEMORY
FSRnH
PROGRAM FLASH
MEMORY MAP
0
7
FSRnL
0
1
0 0 1
Location Select
Location Select
0x2000
0x8000
0x0000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x29AF
 2011 Microchip Technology Inc.
0xF6F
Preliminary
0xFFFF
0x7FFF
DS41455A-page 35
PIC16LF1902/3
NOTES:
DS41455A-page 36
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
4.0
DEVICE CONFIGURATION
Device Configuration consists of Configuration Word 1
and Configuration Word 2, Code Protection and Device
ID.
4.1
Configuration Words
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.
Note:
The DEBUG bit in Configuration Word 2 is
managed automatically by device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 37
PIC16LF1902/3
REGISTER 4-1:
CONFIGURATION WORD 1
U-1
U-1
R/P-1
—
—
CLKOUTEN
R/P-1
R/P-1
U-1
BOREN<1:0>
—
bit 13
R/P-1
R/P-1
R/P-1
CP
MCLRE
PWRTE
bit 8
R/P-1
R/P-1
WDTE<1:0>
U-1
R/P-1
—
R/P-1
FOSC<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
-n = Value when blank or after Bulk Erase
bit 13-12
Unimplemented: Read as ‘1’
bit 11
CLKOUTEN: Clock Out Enable bit
1 = CLKOUT function is disabled. I/O function on the CLKOUT pin.
0 = CLKOUT function is enabled on the CLKOUT pin
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled
bit 8
Unimplemented: Read as ‘1’
bit 7
CP: Code Protection bit
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 6
MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUE3 bit.
bit 5
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bit
11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled
bit 2
Unimplemented: Read as ‘1’
bit 1-0
FOSC<1:0>: Oscillator Selection bits
00 = INTOSC oscillator: I/O function on CLKIN pin
01 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin
10 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin
11 = ECH: External Clock, High-Power mode (4-32 MHz): device clock supplied to CLKIN pin
DS41455A-page 38
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
REGISTER 4-2:
CONFIGURATION WORD 2
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
U-1
LVP
DEBUG
ULPBOR
BORV
STVREN
—
bit 13
bit 8
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
R/P-1
R/P-1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
-n = Value when blank or after Bulk Erase
bit 13
LVP: Low-Voltage Programming Enable bit
1 = Low-voltage programming enabled
0 = High-voltage on MCLR must be used for programming
bit 12
DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11
ULPBOR: Ultra Low-Power BOR bit
1 = Ultra Low-Power BOR is disabled
0 = Ultra Low-Power BOR is enabled
bit 10
BORV: Brown-out Reset Voltage Selection bit
1 = Brown-out Reset voltage set to 1.9V (typical)
0 = Brown-out Reset voltage set to 2.5V (typical)
bit 9
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 8-2
Unimplemented: Read as ‘1’
bit 1-0
WRT<1:0>: Flash Memory Self-Write Protection bits
2 kW Flash memory (PIC16LF1902 only):
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by PMCON control
01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by PMCON control
00 = 000h to 7FFh write-protected, no addresses may be modified by PMCON control
4 kW Flash memory (PIC16LF1903 only):
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON control
01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON control
00 = 000h to FFFh write-protected, no addresses may be modified by PMCON control
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 39
PIC16LF1902/3
4.2
Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection is
controlled independently. Internal access to the
program memory is unaffected by any code protection
setting.
4.2.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Word 1. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection
setting.
See
Section 4.3
“Write
Protection” for more information.
4.3
Write Protection
Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Word 2 define the
size of the program memory block that is protected.
4.4
User ID
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations. For more information on
checksum
calculation,
see
the
“PIC16F193X/LF193X/PIC16F194X/LF194X/PIC16LF
190X
Memory
Programming
Specification”
(DS41397).
DS41455A-page 40
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
4.5
Device ID and Revision ID
The memory location 8006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
REGISTER 4-3:
DEVICEID: DEVICE ID REGISTER
R
R
R
R
R
R
DEV<8:3>
bit 13
R
R
bit 8
R
R
R
DEV<2:0>
R
R
R
REV<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
P = Programmable bit
bit 13-5
DEV<8:0>: Device ID bits
DEVICEID<13:0> Values
Device
bit 4-0
DEV<8:0>
REV<4:0>
PIC16LF1902
01 1100 000
x xxxx
PIC16LF1903
01 1100 001
x xxxx
REV<4:0>: Revision ID bits
These bits are used to identify the revision (see Table under DEV<8:0> above).
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 41
PIC16LF1902/3
NOTES:
DS41455A-page 42
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
5.0
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
RESETS
There are multiple ways to reset this device:
•
•
•
•
•
•
•
•
•
Power-on Reset (POR)
Brown-out Reset (BOR)
Ultra Low-Power Brown-out Reset (ULPBOR)
MCLR Reset
WDT Reset
RESET instruction
Stack Overflow
Stack Underflow
Programming mode exit
To allow VDD to stabilize, an optional power-up timer
can be enabled to extend the Reset time after a BOR
or POR event.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Programming Mode Exit
RESET Instruction
Stack Stack Overflow/Underflow Reset
Pointer
External Reset
MCLRE
MCLR
Sleep
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
Brown-out
Reset
ULPBOR
Reset
BOR
Enable
PWRT
Zero
LFINTOSC
64 ms
PWRTEN
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 43
PIC16LF1902/3
5.1
Power-on Reset (POR)
5.2
Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
5.1.1
•
•
•
•
POWER-UP TIMER (PWRT)
The Power-up Timer provides a nominal 64 ms
time-out on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Word 1.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
TABLE 5-1:
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in Configuration Word 1. The four operating modes are:
BOR is always on
BOR is off when in Sleep
BOR is controlled by software
BOR is always off
Refer to Table 5-1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Word 2.
A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a
duration greater than parameter TBORDC, the device
will reset. See Figure 5-2 for more information.
BOR OPERATING MODES
BOREN<1:0>
SBOREN
Device Mode
BOR Mode
Device Operation
Device Operation
upon wake- up from
upon release of POR
Sleep
11
X
X
Active
Waits for BOR ready(1)
Awake
Active
10
X
Sleep
Disabled
1
01
X
0
00
X
X
Waits for BOR ready
Active
Begins immediately
Disabled
Begins immediately
Disabled
Begins immediately
Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in
start-up.
5.2.1
BOR IS ALWAYS ON
5.2.3
BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Word 1 are set
to ‘11’, the BOR is always on. The device start-up will
be delayed until the BOR is ready and VDD is higher
than the BOR threshold.
When the BOREN bits of Configuration Word 1 are set
to ‘01’, the BOR is controlled by the SBOREN bit of the
BORCON register. The device start-up is not delayed
by the BOR ready condition or the VDD level.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
5.2.2
BOR IS OFF IN SLEEP
When the BOREN bits of Configuration Word 1 are set
to ‘10’, the BOR is on, except in Sleep. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.
BOR protection is unchanged by Sleep.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
DS41455A-page 44
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
FIGURE 5-2:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
TPWRT(1)
VDD
VBOR
Internal
Reset
< TPWRT
TPWRT(1)
VDD
VBOR
Internal
Reset
Note 1:
TPWRT(1)
TPWRT delay only if PWRTE bit is programmed to ‘0’.
REGISTER 5-1:
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u
R/W-0/u
U-0
U-0
U-0
U-0
U-0
R-q/u
SBOREN
BORFS
—
—
—
—
—
BORRDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
SBOREN: Software Brown-out Reset Enable bit
If BOREN <1:0> in Configuration Word 1  01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Word 1 = 01:
1 = BOR Enabled
0 = BOR Disabled
bit 6
BORFS: Brown-out Reset Fast Start bit(1)
If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)
BORFS is Read/Write, but has no effect.
If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):
1 = Band gap is forced on always (covers sleep/wake-up/operating cases)
0 = Band gap operates normally, and may turn off
bit 5-1
Unimplemented: Read as ‘0’
bit 0
BORRDY: Brown-out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 45
PIC16LF1902/3
5.3
Ultra Low-Power Brown-out Reset
(ULPBOR)
The Ultra Low-Power Brown-Out Reset (ULPBOR) is
an essential part of the Reset subsystem. Refer to
Figure 5-1 to see how the BOR interacts with other
modules.
The ULPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the ULPBOR. Refer to Register 5-2.
5.3.1
ENABLING ULPBOR
The ULPBOR is controlled by the ULPBOR bit of
Configuration Word 2. When the device is erased, the
ULPBOR module defaults to disabled.
5.3.1.1
ULPBOR Module Output
The output of the ULPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is to be OR’d together with the Reset signal of the
BOR module to provide the generic BOR signal which
goes to the PCON register and to the power control
block.
5.4
MCLR
5.5
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 9.0
“Watchdog Timer” for more information.
5.6
RESET Instruction
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 5-4
for default conditions after a RESET instruction has
occurred.
5.7
Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration Word
2. See Section 5.7 “Stack Overflow/Underflow Reset”
for more information.
5.8
Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
5.9
Power-Up Timer
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Word 1 and the LVP bit of
Configuration Word 2 (Table 5-2).
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
TABLE 5-2:
The Power-up Timer is controlled by the PWRTE bit of
Configuration Word 1.
MCLR CONFIGURATION
MCLRE
LVP
MCLR
0
0
Disabled
1
0
Enabled
x
1
Enabled
5.4.1
5.10
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1.
2.
MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
Note:
5.4.2
A Reset does not drive the MCLR pin low.
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 11.4 “PORTE Registers” for more information.
DS41455A-page 46
Start-up Sequence
3.
Power-up Timer runs to completion (if enabled).
Oscillator start-up timer runs to completion (if
required for oscillator source).
MCLR must be released (if enabled).
The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See
Section 6.0 “Oscillator Module” for more information.
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low
long enough, the Power-up Timer and oscillator
start-up timer will expire. Upon bringing MCLR high, the
device will begin execution immediately (see
Figure 5-3). This is useful for testing purposes or to
synchronize more than one device operating in parallel.
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
FIGURE 5-3:
RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-Up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 47
PIC16LF1902/3
5.11
Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Table 5-3 and Table 5-4 show the Reset conditions of these registers.
TABLE 5-3:
RESET STATUS BITS AND THEIR SIGNIFICANCE
STKOVF STKUNF RWDT
RMCLR
RI
POR
BOR
TO
PD
Condition
0
0
1
1
1
0
x
1
1
Power-on Reset
0
0
1
1
1
0
x
0
x
Illegal, TO is set on POR
0
0
1
1
1
0
x
x
0
Illegal, PD is set on POR
0
0
u
1
1
u
0
1
1
Brown-out Reset
u
u
0
u
u
u
u
0
u
WDT Reset
u
u
u
u
u
u
u
0
0
WDT Wake-up from Sleep
u
u
u
u
u
u
u
1
0
Interrupt Wake-up from Sleep
u
u
u
0
u
u
u
u
u
MCLR Reset during normal operation
u
u
u
0
u
u
u
1
0
MCLR Reset during Sleep
u
u
u
u
0
u
u
u
u
RESET Instruction Executed
1
u
u
u
u
u
u
u
u
Stack Overflow Reset (STVREN = 1)
u
1
u
u
u
u
u
u
u
Stack Underflow Reset (STVREN = 1)
TABLE 5-4:
RESET CONDITION FOR SPECIAL REGISTERS(2)
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
0000h
---1 1000
00-1 110x
MCLR Reset during normal operation
0000h
---u uuuu
uu-u 0uuu
MCLR Reset during Sleep
0000h
---1 0uuu
uu-u 0uuu
WDT Reset
0000h
---0 uuuu
uu-0 uuuu
WDT Wake-up from Sleep
PC + 1
---0 0uuu
uu-u uuuu
Brown-out Reset
0000h
---1 1uuu
00-1 11u0
---1 0uuu
uu-u uuuu
---u uuuu
uu-u u0uu
Condition
Interrupt Wake-up from Sleep
RESET Instruction Executed
PC + 1
(1)
0000h
Stack Overflow Reset (STVREN = 1)
0000h
---u uuuu
1u-u uuuu
Stack Underflow Reset (STVREN = 1)
0000h
---u uuuu
u1-u uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.
DS41455A-page 48
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
5.12
The PCON register bits are shown in Register 5-2.
Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
•
•
•
•
•
•
•
Power-on Reset (POR)
Brown-out Reset (BOR)
Reset Instruction Reset (RI)
MCLR Reset (RMCLR)
Watchdog Timer Reset (RWDT)
Stack Underflow Reset (STKUNF)
Stack Overflow Reset (STKOVF)
REGISTER 5-2:
PCON: POWER CONTROL REGISTER
R/W/HS-0/q
R/W/HS-0/q
U-0
STKOVF
STKUNF
—
R/W/HC-1/q R/W/HC-1/q
RWDT
RMCLR
R/W/HC-1/q
R/W/HC-q/u
R/W/HC-q/u
RI
POR
BOR
bit 7
bit 0
Legend:
HC = Bit is cleared by hardware
HS = Bit is set by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
STKOVF: Stack Overflow Flag bit
1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or set to ‘0’ by firmware
bit 6
STKUNF: Stack Underflow Flag bit
1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or set to ‘0’ by firmware
bit 5
Unimplemented: Read as ‘0’
bit 4
RWDT: Watchdog Timer Reset Flag bit
1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware
0 = A Watchdog Timer Reset has occurred (set to ‘0’ in hardware when a Watchdog Timer Reset)
bit 3
RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or set to ‘1’ by firmware
0 = A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)
bit 2
RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or set to ‘1’ by firmware
0 = A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET instruction)
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 49
PIC16LF1902/3
TABLE 5-5:
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BORCON
SBOREN
BORFS
—
—
—
—
—
BORRDY
45
PCON
STKOVF
STKUNF
—
RWDT
RMCLR
RI
POR
BOR
49
STATUS
—
—
—
TO
PD
Z
DC
C
19
WDTCON
—
—
SWDTEN
77
WDTPS<4:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
DS41455A-page 50
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
6.0
OSCILLATOR MODULE
6.1
Overview
The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing performance and minimizing power consumption. Figure 6-1
illustrates a block diagram of the oscillator module.
Clock sources can be supplied from external clock
circuits. In addition, the system clock source can be
supplied from one of two internal oscillators, with a
choice of speeds selectable via software. Additional
clock features include:
• Selectable system clock source between external
or internal sources via software.
• Fast start-up oscillator allows internal circuits to
power up and stabilize before switching to the 16
MHz HFINTOSC
The oscillator module can be configured in one of the
following clock modes:
1.
2.
3.
4.
ECL – External Clock Low Power mode
(0 MHz to 0.5 MHz)
ECM – External Clock Medium Power mode
(0.5 MHz to 4 MHz)
ECH – External Clock High Power mode
(4 MHz to 32 MHz)
INTOSC – Internal oscillator (31 kHz to 16 MHz).
Clock Source modes are selected by the FOSC<1:0>
bits in the Configuration Word 1. The FOSC bits
determine the type of oscillator that will be used when
the device is first powered.
The EC Clock mode relies on an external logic level
signal as the device clock source.
The INTOSC internal oscillator block produces a low
and high frequency clock source, designated
LFINTOSC and HFINTOSC. (see Internal Oscillator
Block, Figure 6-1). A wide selection of device clock
frequencies may be derived from these two clock
sources.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 51
PIC16LF1902/3
SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
FIGURE 6-1:
Low Power Mode
Event Switch
(SCS<1:0>)
CLKIN
EC
2
CLKIN
Primary Clock
00
T1CKI/
T1OSO
T1OSI
Secondary
Oscillator
(T1OSC)
Secondary Clock
INTOSC
01
1x
Clock Switch MUX
Secondary Oscillator
Internal Oscillator
IRCF<3:0>
4
Start-Up Osc
LF-INTOSC
(31 kHz)
DS41455A-page 52
INTOSC
Divide Circuit
16 MHz
Primary Osc
/1
/2
/4
/8
/16
HF-16 MHz
/32
HF-500 kHz
/64
HF-250 kHz
HF-8 MHz
HF-4 MHz
HF-2 MHz
HF-1 MHz
/128
HF-125 kHz
/256
HF-62.5 kHz
/512
HF-31.25 kHz
LF-31 kHz
1111
1110
1101
1100
1011
1010/
0111
1001/
0110
1000/
0101
0100
0011
0010
0001
0000
Internal Oscillator MUX
Start-up
Control
Logic
4
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
6.2
Clock Source Types
Clock sources can be classified as external or internal.
External clock sources rely on external circuitry for the
clock source to function. An example is: oscillator module (EC mode) circuit.
Internal clock sources are contained internally within the
oscillator module. The internal oscillator block has two
internal oscillators that are used to generate the internal
system clock sources: the 16 MHz High-Frequency
Internal Oscillator and the 31 kHz Low-Frequency
Internal Oscillator (LFINTOSC).
The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS) bits in the OSCCON register. See Section 6.3
“Clock Switching” for additional information.
6.2.1
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 6-2:
Clock from
Ext. System
FOSC/4 or I/O(1)
EXTERNAL CLOCK SOURCES
An external clock source can be used as the device
system clock by performing one of the following
actions:
Note 1:
EXTERNAL CLOCK (EC)
MODE OPERATION
CLKIN
PIC® MCU
CLKOUT
Output depends upon CLKOUTEN bit of the
Configuration Word 1.
• Program the FOSC<1:0> bits in the Configuration
Word 1 to select an external clock source that will
be used as the default system clock upon a
device Reset.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to:
- Secondary oscillator during run-time, or
- An external clock source determined by the
value of the FOSC bits.
See Section 6.3 “Clock Switching”for more information.
6.2.1.1
EC Mode
The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the CLKIN input. CLKOUT is
available for general purpose I/O or CLKOUT.
Figure 6-2 shows the pin connections for EC mode.
EC mode has 3 power modes to select from through
Configuration Word 1:
• High power, 4-20 MHz (FOSC = 11)
• Medium power, 0.5-4 MHz (FOSC = 10)
• Low power, 0-0.5 MHz (FOSC = 01)
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 53
PIC16LF1902/3
6.2.1.2
6.2.2
Secondary Oscillator
The secondary oscillator is a separate crystal oscillator
that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz
crystal connected between the T1CKI/T1OSO and
T1OSI device pins.
The secondary oscillator can be used as an alternate
system clock source and can be selected during
run-time using clock switching. Refer to Section 6.3
“Clock Switching” for more information.
FIGURE 6-3:
QUARTZ CRYSTAL
OPERATION
(SECONDARY
OSCILLATOR)
PIC®
The device may be configured to use the internal oscillator block as the system clock by performing one of the
following actions:
• Program the FOSC<1:0> bits in Configuration
Word 1 to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run-time. See Section 6.3
“Clock Switching”for more information.
In INTOSC mode, CLKIN is available for general
purpose I/O. CLKOUT is available for general purpose
I/O or CLKOUT.
The function of the CLKOUT pin is determined by the
state of the CLKOUTEN bit in Configuration Word 1.
MCU
The internal oscillator block has two independent
oscillators that provides the internal system clock
source.
T1CKI/T1OSO
C1
To Internal
Logic
1.
32.768 kHz
Quartz
Crystal
2.
T1OSI
C2
The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
16 MHz.
The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
6.2.2.1
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
• TB097, “Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS” (DS91097)
• AN1288, “Design Practices for
Low-Power External Oscillators”
(DS01288)
DS41455A-page 54
INTERNAL CLOCK SOURCES
HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 16 MHz internal clock source.
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 6-1). The frequency derived
from the HFINTOSC can be selected via software using
the IRCF<3:0> bits of the OSCCON register. See
Section 6.2.2.4 “Internal Oscillator Clock Switch
Timing” for more information.
The HFINTOSC is enabled by:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
• FOSC<1:0> = 11, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.
The High Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running and can be utilized.
The High Frequency Internal Oscillator Status Stable
bit (HFIOFS) of the OSCSTAT register indicates when
the HFINTOSC is running within 0.5% of its final value.
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
6.2.2.2
LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure 6-1). Select 31 kHz, via
software, using the IRCF<3:0> bits of the OSCCON
register. See Section 6.2.2.4 “Internal Oscillator
Clock Switch Timing” for more information. The
LFINTOSC is also the frequency for the Power-up Timer
(PWRT) and Watchdog Timer (WDT).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> bits of the OSCCON register = 000) as the
system clock source (SCS bits of the OSCCON
register = 1x), or when any of the following are enabled:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and
• FOSC<1:0> = 01, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running and can be utilized.
2.
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.
Internal Oscillator Clock Switch
Timing
When switching between the HFINTOSC and the
LFINTOSC, the new oscillator may already be shut
down to save power (see Figure 6-4). If this is the case,
there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC and
LFINTOSC oscillators. The sequence of a frequency
selection is as follows:
1.
Internal Oscillator Frequency
Selection
Following any Reset, the IRCF<3:0> bits
of the OSCCON register are set to ‘0111’
and the frequency selection is set to
500 kHz. The user can modify the IRCF
bits to select a different frequency.
The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower
power consumption can be obtained when changing
oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes
that use the same oscillator source.
6.2.2.4
Peripherals that use the LFINTOSC are:
6.2.2.3
Note:
3.
IRCF<3:0> bits of the OSCCON register are
modified.
If the new clock is shut down, a clock start-up
delay is started.
Clock switch circuitry waits for a falling edge of
the current clock.
The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
The new clock is now active.
The OSCSTAT register is updated as required.
Clock switch is complete.
The output of the 16 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 6-1). The Internal Oscillator Frequency
Select bits IRCF<3:0> of the OSCCON register select
the frequency output of the internal oscillators. One of
the following frequencies can be selected via software:
4.
•
•
•
•
•
•
•
•
•
•
•
See Figure 6-4 for more details.
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz (Default after Reset)
250 kHz
125 kHz
62.5 kHz
31.25 kHz
31 kHz (LFINTOSC)
 2011 Microchip Technology Inc.
5.
6.
7.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 6-1.
Start-up delay specifications are located in the
oscillator tables of Section 21.0 “Electrical
Specifications”
Preliminary
DS41455A-page 55
PIC16LF1902/3
FIGURE 6-4:
HFINTOSC
INTERNAL OSCILLATOR SWITCH TIMING
LFINTOSC (WDT disabled)
HFINTOSC
Start-up Time
2-cycle Sync
Running
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
0
0
System Clock
HFINTOSC
LFINTOSC (WDT enabled)
HFINTOSC
LFINTOSC
0
IRCF <3:0>
0
System Clock
LFINTOSC
HFINTOSC
LFINTOSC turns off unless WDT is enabled
LFINTOSC
Start-up Time
2-cycle Sync
Running
HFINTOSC
IRCF <3:0>
=0
0
System Clock
DS41455A-page 56
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
6.3
6.3.3
Clock Switching
SECONDARY OSCILLATOR
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:
The secondary oscillator is a separate crystal oscillator
associated with the Timer1 peripheral. It is optimized
for timekeeping operations with a 32.768 kHz crystal
connected between the T1OSI and T1CKI/T1OSO
device pins.
• Default system oscillator determined by FOSC
bits in Configuration Word 1
• Secondary oscillator 32 kHz crystal
• Internal Oscillator Block (INTOSC)
The secondary oscillator is enabled using the
T1OSCEN control bit in the T1CON register. See
Section 17.0 “Timer1 Module with Gate Control” for
more information about the Timer1 peripheral.
6.3.1
6.3.4
SYSTEM CLOCK SELECT (SCS)
BITS
The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
• When the SCS bits of the OSCCON register = 00,
the system clock source is determined by value of
the FOSC<1:0> bits in the Configuration Word 1.
• When the SCS bits of the OSCCON register = 01,
the system clock source is the secondary
oscillator.
• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
SECONDARY OSCILLATOR READY
(T1OSCR) BIT
The user must ensure that the secondary oscillator is
ready to be used before it is selected as a system clock
source. The Secondary Oscillator Ready (T1OSCR) bit
of the OSCSTAT register indicates whether the
secondary oscillator is ready to be used. After the
T1OSCR bit is set, the SCS bits can be configured to
select the secondary oscillator.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These oscillator delays are shown in Table 6-1.
6.3.2
OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCSTAT register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<1:0> bits in the Configuration
Word 1, or from the internal clock source. The OST
does not reflect the status of the secondary oscillator.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 57
PIC16LF1902/3
6.4
Oscillator Control Registers
REGISTER 6-1:
U-0
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0
R/W-1/1
R/W-1/1
R/W-1/1
IRCF<3:0>
—
U-0
R/W-0/0
R/W-0/0
SCS<1:0>
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
IRCF<3:0>: Internal Oscillator Frequency Select bits
000x = 31 kHz LF
001x = 31.25 kHz
0100 = 62.5 kHz
0101 = 125 kHz
0110 = 250 kHz
0111 = 500 kHz (default upon Reset)
1000 = 125 kHz(1)
1001 = 250 kHz(1)
1010 = 500 kHz(1)
1011 = 1 MHz
1100 = 2 MHz
1101 = 4 MHz
1110 = 8 MHz
1111 = 16 MHz
bit 2
Unimplemented: Read as ‘0’
bit 1-0
SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Secondary oscillator
00 = Clock determined by FOSC<1:0> in Configuration Word 1.
Note 1:
Duplicate frequency derived from HFINTOSC.
DS41455A-page 58
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
REGISTER 6-2:
OSCSTAT: OSCILLATOR STATUS REGISTER
R-1/q
U-0
R-q/q
R-0/q
U-0
U-0
R-0/0
R-0/q
T1OSCR
—
OSTS
HFIOFR
—
—
LFIOFR
HFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Conditional
bit 7
T1OSCR: Timer1 Oscillator Ready bit
If T1OSCEN = 1:
1 = Timer1 oscillator is ready
0 = Timer1 oscillator is not ready
If T1OSCEN = 0:
1 = Timer1 clock source is always ready
bit 6
Unimplemented: Read as ‘0’
bit 5
OSTS: Oscillator Start-up Time-out Status bit
1 = Running from the external clock source (EC)
0 = Running from an internal oscillator (FOSC<1:0> = 00)
bit 4
HFIOFR: High Frequency Internal Oscillator Ready bit
1 = HFINTOSC is ready
0 = HFINTOSC is not ready
bit 3-2
Unimplemented: Read as ‘0’
bit 1
LFIOFR: Low Frequency Internal Oscillator Ready bit
1 = LFINTOSC is ready
0 = LFINTOSC is not ready
bit 0
HFIOFS: High Frequency Internal Oscillator Stable bit
1 = HFINTOSC 16 MHz Oscillator is stable and is driving the INTOSC
0 = HFINTOSC 16 MHz is not stable, the Start-up Oscillator is driving INTOSC
TABLE 6-1:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name
Bit 7
Bit 6
OSCCON
—
OSCSTAT
T1OSCR
T1CON
Legend:
CONFIG1
Legend:
Bit 4
Bit 3
IRCF<3:0>
—
OSTS
TMR1CS<1:0>
Bit 2
Bit 1
—
HFIOFR
T1CKPS<1:0>
Bit 0
SCS<1:0>
Register
on Page
58
—
—
LFIOFR
HFIOFS
59
T1OSCEN
T1SYNC
—
TMR1ON
139
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
TABLE 6-2:
Name
Bit 5
Bits
SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
—
CLKOUTEN
13:8
—
—
—
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
BOREN<1:0>
—
Bit 8/0
—
FOSC<1:0>
Register
on Page
38
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
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NOTES:
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7.0
A block diagram of the interrupt logic is shown in
Figure 7.1 and Figure 7.1.
INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
•
•
•
•
•
Operation
Interrupt Latency
Interrupts During Sleep
INT Pin
Automatic Context Saving
Many peripherals produce Interrupts. Refer to the corresponding chapters for details.
FIGURE 7-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
Peripheral Interrupts
(TMR1IF) PIR1<0>
(TMR1IF) PIR1<0>
Wake-up
(If in Sleep mode)
INTF
INTE
IOCIF
IOCIE
Interrupt
to CPU
PEIE
PIRn<7>
PIEn<7>
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GIE
Preliminary
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7.1
Operation
7.2
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1 and PIE2 registers)
Interrupt Latency
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 or 4 instruction cycles. For asynchronous
interrupts, the latency is 3 to 5 instruction cycles,
depending on when the interrupt occurs. See Figure 7-2
and Figure 7.3 for more details.
The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will
be set, regardless of the status of the GIE, PEIE and
individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See Section 7.5 “Automatic
Context Saving”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
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FIGURE 7-2:
INTERRUPT LATENCY
CLKIN
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT
Interrupt Sampled
during Q1
Interrupt
GIE
PC
Execute
PC-1
PC
1 Cycle Instruction at PC
PC+1
0004h
0005h
Inst(PC)
NOP
NOP
Inst(0004h)
PC+1/FSR
ADDR
New PC/
PC+1
0004h
0005h
Inst(PC)
NOP
NOP
Inst(0004h)
FSR ADDR
PC+1
PC+2
0004h
0005h
INST(PC)
NOP
NOP
NOP
Inst(0004h)
Inst(0005h)
FSR ADDR
PC+1
0004h
0005h
INST(PC)
NOP
NOP
Inst(0004h)
Interrupt
GIE
PC
Execute
PC-1
PC
2 Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3 Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3 Cycle Instruction at PC
 2011 Microchip Technology Inc.
Preliminary
PC+2
NOP
NOP
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FIGURE 7-3:
INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CLKIN
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF
Interrupt Latency (2)
(5)
GIE
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note 1:
PC
Inst (PC)
Inst (PC – 1)
PC + 1
Inst (PC + 1)
PC + 1
—
Dummy Cycle
Inst (PC)
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
INTF flag is sampled here (every Q1).
2:
Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
CLKOUT not available in all Oscillator modes.
4:
For minimum width of INT pulse, refer to AC specifications in Section 21.0 “Electrical Specifications””.
5:
INTF is enabled to be set any time during the Q4-Q1 cycles.
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7.3
Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the Section 8.0
“Power-Down Mode (Sleep)” for more details.
7.4
INT Pin
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
7.5
Automatic Context Saving
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the Shadow registers:
•
•
•
•
•
W register
STATUS register (except for TO and PD)
BSR register
FSR registers
PCLATH register
Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding Shadow register should be modified and the
value will be restored when exiting the ISR. The
Shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s application, other registers may also need to be saved.
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7.5.1
INTCON REGISTER
Note:
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, interrupt-on-change and
external INT pin interrupts.
REGISTER 7-1:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all active interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4
INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3
IOCIE: Interrupt-on-Change Interrupt Enable bit
1 = Enables the interrupt-on-change interrupt
0 = Disables the interrupt-on-change interrupt
bit 2
TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
bit 1
INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
bit 0
IOCIF: Interrupt-on-Change Interrupt Flag bit
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state
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7.5.2
PIE1 REGISTER
The PIE1 register contains the interrupt enable bits, as
shown in Register 7-2.
REGISTER 7-2:
R/W-0/0
TMR1GIE
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
ADIE
—
—
—
—
—
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
TMR1GIE: Timer1 Gate Interrupt Enable bit
1 = Enables the Timer1 Gate Acquisition interrupt
0 = Disables the Timer1 Gate Acquisition interrupt
bit 6
ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5-1
Unimplemented: Read as ‘0’
bit 0
TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
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7.5.3
PIE2 REGISTER
The PIE2 register contains the interrupt enable bits, as
shown in Register 7-3.
REGISTER 7-3:
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0
U-0
U-0
U-0
U-0
R/W-0/0
U-0
U-0
—
—
—
—
—
LCDIE
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2
LCDIE: LCD Module Interrupt Enable bit
1 = Enables the LCD module interrupt
0 = Disables the LCD module interrupt
bit 1-0
Unimplemented: Read as ‘0’
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7.5.4
PIR1 REGISTER
The PIR1 register contains the interrupt flag bits, as
shown in Register 7-4.
REGISTER 7-4:
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
TMR1GIF
ADIF
—
—
—
—
—
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5-1
Unimplemented: Read as ‘0’
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
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7.5.5
PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 7-5.
REGISTER 7-5:
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
U-0
U-0
U-0
U-0
U-0
R/W-0/0
U-0
U-0
—
—
—
—
—
LCDIF
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2
LCDIF: LCD Module Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1-0
Unimplemented: Read as ‘0’
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TABLE 7-1:
Name
INTCON
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
OPTION_REG WPUEN
PIE1
TMR1GIE
INTEDG TMR0CS TMR0SE
PSA
PS<2:0>
ADIE
—
—
—
—
—
129
TMR1IE
67
PIE2
—
—
—
—
—
LCDIE
—
—
68
PIR1
TMR1GIF
ADIF
—
—
—
—
—
TMR1IF
69
PIR2
—
—
—
—
—
LCDIF
—
—
70
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts.
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8.0
POWER-DOWN MODE (SLEEP)
8.1
Wake-up from Sleep
The Power-Down mode is entered by executing a
SLEEP instruction.
The device can wake-up from Sleep through one of the
following events:
Upon entering Sleep mode, the following conditions
exist:
1.
2.
3.
4.
5.
6.
1.
WDT will be cleared but keeps running, if
enabled for operation during Sleep.
2. PD bit of the STATUS register is cleared.
3. TO bit of the STATUS register is set.
4. CPU clock is disabled.
5. 31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
6. Secondary oscillator is unaffected and peripherals that operate from it may continue operation
in Sleep.
7. ADC is unaffected, if the dedicated FRC clock is
selected.
8. Capacitive Sensing oscillator is unaffected.
9. I/O ports maintain the status they had before
SLEEP was executed (driving high, low or
high-impedance).
10. Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following conditions should be considered:
•
•
•
•
•
•
I/O pins should not be floating
External circuitry sinking current from I/O pins
Internal circuitry sourcing current from I/O pins
Current draw from pins with internal weak pull-ups
Modules using 31 kHz LFINTOSC
Modules using Secondary oscillator
External Reset input on MCLR pin, if enabled
BOR Reset, if enabled
POR Reset
Watchdog Timer, if enabled
Any external interrupt
Interrupts by peripherals capable of running during Sleep (see individual peripheral for more
information)
The first three events will cause a device Reset. The
last three events are considered a continuation of program execution. To determine whether a device Reset
or wake-up event occurred, refer to Section 5.11,
Determining the Cause of a Reset.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will call the Interrupt Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include the FVR module. See 13.0 “Fixed Voltage Reference (FVR)” for more information.
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8.1.1
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction
- SLEEP instruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
cleared.
FIGURE 8-1:
• If the interrupt occurs during or after the execution of a SLEEP instruction
- SLEEP instruction will be completely executed
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
CLKOUT(2)
Interrupt flag
Interrupt Latency (1)
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
PC
Instruction
Fetched
Instruction
Executed
Note
1:
PC + 1
Inst(PC) = Sleep
Inst(PC - 1)
PC + 2
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
Dummy Cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
TABLE 8-1:
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBF0
106
IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
106
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
106
TMR1GIE
ADIE
—
—
—
—
—
TMR1IE
67
IOCBP
PIE1
PIE2
—
—
—
—
—
LCDIE
—
—
68
PIR1
TMR1GIF
ADIF
—
—
—
—
—
TMR1IF
69
PIR2
—
—
—
—
—
LCDIF
—
—
70
STATUS
—
—
—
TO
PD
Z
DC
C
19
—
—
SWDTEN
77
WDTCON
Legend:
WDTPS<4:0>
— = unimplemented location, read as ‘0’. Shaded cells are not used in Power-down mode.
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9.0
WATCHDOG TIMER
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (typical)
• Multiple Reset conditions
• Operation during Sleep
FIGURE 9-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
LFINTOSC
23-bit Programmable
Prescaler WDT
WDT Time-out
WDTE<1:0> = 10
Sleep
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9.1
Independent Clock Source
9.3
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1 ms. See
Section 21.0 “Electrical Specifications” for the
LFINTOSC tolerances.
9.2
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Word 1. See Table 9-1.
WDT IS ALWAYS ON
When the WDTE bits of Configuration Word 1 are set to
‘11’, the WDT is always on.
WDT protection is active during Sleep.
9.2.2
WDT protection is not active during Sleep.
WDT CONTROLLED BY SOFTWARE
When the WDTE bits of Configuration Word 1 are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
WDT protection is unchanged by Sleep. See Table 9-1
for more details.
TABLE 9-1:
WDT OPERATING MODES
WDTE<1:0>
SWDTEN
Device
Mode
WDT
Mode
11
X
X
Active
Awake
Active
10
X
Sleep
Disabled
1
X
01
0
00
TABLE 9-2:
X
X
9.4
Clearing the WDT
•
•
•
•
•
•
•
Any Reset
CLRWDT instruction is executed
Device enters Sleep
Device wakes up from Sleep
Oscillator fail event
WDT is disabled
Oscillator Start-up TImer (OST) is running
See Table 9-2 for more information.
WDT IS OFF IN SLEEP
When the WDTE bits of Configuration Word 1 are set to
‘10’, the WDT is on, except in Sleep.
9.2.3
The WDTPS bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is 2 seconds.
The WDT is cleared when any of the following conditions occur:
WDT Operating Modes
9.2.1
Time-Out Period
9.5
Operation During Sleep
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 6.0 “Oscillator
Module” for more information on the OST.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. See Section 3.0 “Memory Organization” and
STATUS register (Register 3-1) for more information.
Active
Disabled
Disabled
WDT CLEARING CONDITIONS
Conditions
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Cleared until the end of OST
Change INTOSC divider (IRCF bits)
DS41455A-page 76
Unaffected
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
REGISTER 9-1:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
WDTPS<4:0>
bit 7
R/W-0/0
SWDTEN
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-1
WDTPS<4:0>: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
00000 = 1:32 (Interval 1 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01010 = 1:32768 (Interval 1s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01100 = 1:131072 (217) (Interval 4s nominal)
01101 = 1:262144 (218) (Interval 8s nominal)
01110 = 1:524288 (219) (Interval 16s nominal)
01111 = 1:1048576 (220) (Interval 32s nominal)
10000 = 1:2097152 (221) (Interval 64s nominal)
10001 = 1:4194304 (222) (Interval 128s nominal)
10010 = 1:8388608 (223) (Interval 256s nominal)
10011 = Reserved. Results in minimum interval (1:32)
•
•
•
11111 = Reserved. Results in minimum interval (1:32)
bit 0
Note 1:
SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 00:
This bit is ignored.
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 1x:
This bit is ignored.
Times are approximate. WDT time is based on 31 kHz LFINTOSC.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 77
PIC16LF1902/3
NOTES:
DS41455A-page 78
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
10.0
FLASH PROGRAM MEMORY
CONTROL
10.1
The Flash program memory is readable and writable
during normal operation over the full VDD range.
Program memory is indirectly addressed using Special
Function Registers (SFRs). The SFRs used to access
program memory are:
•
•
•
•
•
•
PMCON1
PMCON2
PMDATL
PMDATH
PMADRL
PMADRH
PMADRL and PMADRH Registers
The PMADRH:PMADRL register pair can address up
to a maximum of 32K words of program memory. When
selecting a program address value, the MSB of the
address is written to the PMADRH register and the LSB
is written to the PMADRL register.
10.1.1
PMCON1 AND PMCON2
REGISTERS
PMCON1 is the control register for Flash Program
Memory accesses.
When accessing the program memory, the
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the
PMADRL and PMADRH registers form a 2-byte word
that holds the 15-bit address of the program memory
location being read.
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range of
the device.
The Flash Program Memory Self-Write Protection bits,
WRT<1:0> of Configuration Word 2, can be used to
prohibit self-writes to a portion or all of the Flash
program memory.
When the device is code-protected (CP = 0)(1), the
device programmer can no longer access program
memory. When code-protected, the CPU may continue
to read and self-write program memory.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.
The PMCON2 register is a write-only register. Attempting
to read the PMCON2 register will return all ‘0’s.
To enable writes to the program memory, a specific
pattern (the unlock sequence), must be written to the
PMCON2 register. The required unlock sequence
prevents inadvertent writes to the program memory
write latches and Flash program memory.
Note 1: Code protection of the entire Flash
Program Memory array is enabled by
clearing the CP bit of Configuration Word
1.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 79
PIC16LF1902/3
FIGURE 10-1:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Flash ADDR
Flash Data
PC + 1
INSTR (PC)
INSTR(PC - 1)
executed here
PC
+3
PC+3
PMADRH,PMADRL
INSTR (PC + 1)
BSF PMCON1,RD
executed here
PMDATH,PMDATL
INSTR(PC + 1)
instruction ignored
Forced NOP
executed here
PC + 4
INSTR (PC + 3)
INSTR(PC + 2)
instruction ignored
Forced NOP
executed here
PC + 5
INSTR (PC + 4)
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
PMDATH
PMDATL
Register
EXAMPLE 10-1:
FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
*
data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWL
PMADRL
PROG_ADDR_LO
PMADRL
PROG_ADDR_HI
PMADRH
; Select Bank for PMCON registers
;
; Store LSB of address
;
; Store MSB of address
BCF
BCF
BSF
NOP
NOP
BSF
PMCON1,CFGS
INTCON,GIE
PMCON1,RD
INTCON,GIE
;
;
;
;
;
;
Do not select Configuration Space
Disable interrupts
Initiate read
Ignored (Figure 10-1)
Ignored (Figure 10-1)
Restore interrupts
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
Get LSB of word
Store in user location
Get MSB of word
Store in user location
DS41455A-page 80
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
10.2
Flash Program Memory Overview
It is important to understand the Flash program memory
structure for erase and programming operations. Flash
program memory is arranged in rows. A row consists of
a fixed number of 14-bit program memory words. A row
is the minimum size that can be erased by user software.
Flash program memory may only be written or erased
if the destination address is in a segment of memory
that is not write-protected, as defined in bits WRT<1:0>
of Configuration Word 2.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the PMDATH:PMDATL register pair.
Note:
If the user wants to modify only a portion
of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
Then, new data and retained data can be
written into the write latches to reprogram
the row of Flash program memory.
See Table 10-1 for Erase Row size and the number of
write latches for Flash program memory.
TABLE 10-1:
FLASH MEMORY
ORGANIZATION BY DEVICE
Device
Row Erase
(words)
Write Latches
(words)
PIC16LF1902/3
32
32
10.2.1
READING THE FLASH PROGRAM
MEMORY
To read a program memory location, the user must:
1.
Write
the
desired
address
to
the
PMADRH:PMADRL register pair.
Clear the CFGS bit of the PMCON1 register.
Then, set control bit RD of the PMCON1 register.
2.
3.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF PMCON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.
PMDATH:PMDATL register pair will hold this value until
another read or until it is written to by the user.
Note:
10.2.2
The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
two-cycle instruction on the next
instruction after the RD bit is set.
FLASH MEMORY UNLOCK
SEQUENCE
The unlock sequence is a mechanism that protects the
Flash program memory from unintended self-write programming or erasing. The sequence must be executed
and completed without interruption to successfully
complete:
• Row Erase
• Load program memory write latches
• Write of program memory write latches to program memory
• Write of program memory write latches to User
IDs
The unlock sequence consist of the following steps:
1. Write 55h to PMCON2
2. Write AAh to PMCON2
3. Set the WR bit in PMCON1
4. NOP instruction
5. NOP instruction
Once the WR bit is set, the processor will always force
two NOP instructions. If an Erase Row or Program Row
operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is
complete and then resume with the next instruction. If the
operation was loading the program memory write latches,
the processor will always force the two NOP instructions
and continue uninterrupted with the next instruction.
Since the unlock sequence cannot be interrupted, global
interrupts should be disabled prior to the unlock sequence
and re-enabled after the unlock sequence is completed.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 81
PIC16LF1902/3
10.2.3
ERASING FLASH PROGRAM
MEMORY
5.
While executing code, program memory can only be
erased by rows. To erase a row:
1.
2.
3.
4.
Load the PMADRH:PMADRL register pair with
the address of new row to be erased.
Clear the CFGS bit of the PMCON1 register.
Set the FREE and WREN bits of the PMCON1
register.
Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence).
EXAMPLE 10-2:
Set control bit WR of the PMCON1 register to
begin the erase operation.
See Example 10-2.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms erase time. This is not Sleep mode as the
clocks and peripherals will continue to run. After the
erase cycle, the processor will resume operation with
the third instruction after the PMCON1 write instruction.
ERASING ONE ROW OF PROGRAM MEMORY
Required
Sequence
; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
BSF
BSF
INTCON,GIE
PMADRL
ADDRL,W
PMADRL
ADDRH,W
PMADRH
PMCON1,CFGS
PMCON1,FREE
PMCON1,WREN
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
NOP
; Disable ints so required sequences will execute properly
; Load lower 8 bits of erase address boundary
; Load upper 6 bits of erase address boundary
; Not configuration space
; Specify an erase operation
; Enable writes
;
;
;
;
;
;
;
;
Start of required sequence to initiate erase
Write 55h
Write AAh
Set WR bit to begin erase
Any instructions here are ignored as processor
halts to begin erase sequence
Processor will stop here and wait for erase complete.
; after erase processor continues with 3rd instruction
BCF
BSF
DS41455A-page 82
PMCON1,WREN
INTCON,GIE
; Disable writes
; Enable interrupts
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
10.2.4
WRITING TO FLASH PROGRAM
MEMORY
Program memory is programmed using the following
steps:
1.
2.
3.
4.
Load the address in PMADRH:PMADRL of the
row to be programmed.
Load each write latch with data.
Initiate a programming operation.
Repeat steps 1 through 3 until all data is written.
The following steps should be completed to load the
write latches and program a block of program memory.
These steps are divided into two parts. First, each write
latch is loaded with data from the PMDATH:PMDATL
using the unlock sequence with LWLO = 1. When the
last word to be loaded into the write latch is ready, the
LWLO bit is cleared and the unlock sequence
executed. This initiates the programming operation,
writing all the latches into Flash Program Memory.
Note:
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten. Program memory can only be erased one row at a time. No
automatic erase occurs upon the initiation of the write.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 10-2 (block writes to program memory with 32
write latches) for more details.
The write latches are aligned to the address boundary
defined by PMADRH:PMADRL with the 5 LSBs being
ignored. Write operations do not cross these boundaries. At the completion of a program memory write operation, the write latches are reset to contain 0x3FFF.
The write latches are aligned to the Flash row address
boundary defined by the upper 10-bits of
PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>)
with the lower 5-bits of PMADRL, (PMADRL<4:0>)
determining the write latch being loaded. Write operations do not cross these boundaries. At the completion
of a program memory write operation, the data in the
write latches is reset to contain 0x3FFF.
The special unlock sequence is required
to load a write latch with data or initiate a
Flash programming operation. If the
unlock sequence is interrupted, writing to
the latches or program memory will not be
initiated.
1.
2.
3.
Set the WREN bit of the PMCON1 register.
Clear the CFGS bit of the PMCON1 register.
Set the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘1’, the write sequence will only load the write
latches and will not initiate the write to Flash
Program Memory.
4. Load the PMADRH:PMADRL register pair with
the address of the location to be written.
5. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
6. Execute the unlock sequence (Section 10.2.2
“Flash Memory Unlock Sequence”). The write
latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘0’, the write sequence will initiate the write to
Flash Program Memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence (Section 10.2.2
“Flash Memory Unlock Sequence”). The
entire program memory latch content is now
written to Flash program memory.
It is not necessary to load all the program memory write
latches with user program data. However, all the
program memory write latches will be written to
program memory simultaneously.
Note:
 2011 Microchip Technology Inc.
Preliminary
Write latches that have not been loaded
will contain 0x3FFF, the Reset value after
each write operation.
DS41455A-page 83
PIC16LF1902/3
An example of the complete write sequence is shown in
Example 10-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using indirect addressing.
DS41455A-page 84
Preliminary
 2011 Microchip Technology Inc.
 2011 Microchip Technology Inc.
FIGURE 10-2:
7
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
6
0 7
5 4
PMADRH
-
r9
r8
r7
r6
r5
7
0
PMADRL
r4
r3
r2
r1
r0
c4
c3
c2
c1
c0
5
-
0
7
PMDATH
6
0
PMDATL
8
14
10
Program Memory Write Latches
5
14
Write Latch #0
00h
PMADRL<4:0>
Preliminary
14
CFGS = 0
14
Write Latch #1
01h
14
Write Latch #30 Write Latch #31
1Eh
1Fh
14
14
14
Row
Addr
Addr
Addr
Addr
000h
0000h
0001h
001Eh
001Fh
001h
0020h
0021h
003Eh
003Fh
002h
0040h
0041h
005Eh
005Fh
3FEh
7FC0h
7FC1h
7FDEh
7FDFh
3FFh
7FE0h
7FE1h
7FFEh
7FFFh
Flash Program Memory
DS41455A-page 85
400h
CFGS = 1
8000h-8003h
8004h-8005h
8006h
8007h-8008h
8009h-801Fh
USER ID 0 - 3
reserved
DEVICEID
REVID
Configuration
Words
reserved
Configuration Memory
PIC16LF1902/3
PMADRH<6:0>
:PMADRL<7:5>
Row
Address
Decode
14
PIC16LF1902/3
EXAMPLE 10-3:
;
;
;
;
;
;
;
WRITING TO FLASH PROGRAM MEMORY
This write routine assumes the following:
1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
stored in little endian format
3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
BSF
INTCON,GIE
PMADRH
ADDRH,W
PMADRH
ADDRL,W
PMADRL
LOW DATA_ADDR
FSR0L
HIGH DATA_ADDR
FSR0H
PMCON1,CFGS
PMCON1,WREN
PMCON1,LWLO
;
;
;
;
;
;
;
;
;
;
;
;
;
Disable ints so required sequences will execute properly
Bank 3
Load initial address
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
PMDATL
FSR0++
PMDATH
; Load first data byte into lower
;
; Load second data byte into upper
;
MOVF
XORLW
ANDLW
BTFSC
GOTO
PMADRL,W
0x1F
0x1F
STATUS,Z
START_WRITE
; Check if lower bits of address are '00000'
; Check if we're on the last of 32 addresses
;
; Exit if last of 32 words,
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
PMADRL,F
LOOP
; Still loading latches Increment address
; Write next latches
PMCON1,LWLO
; No more loading latches - Actually start Flash program
; memory write
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
;
Load initial data address
Load initial data address
Not configuration space
Enable writes
Only Load Write Latches
Required
Sequence
LOOP
NOP
INCF
GOTO
Required
Sequence
START_WRITE
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BCF
BSF
DS41455A-page 86
PMCON1,WREN
INTCON,GIE
Start of required write sequence:
Write 55h
Write AAh
Set WR bit to begin write
NOP instructions are forced as processor
loads program memory write latches
Start of required write sequence:
Write 55h
Write AAh
Set WR bit to begin write
NOP instructions are forced as processor writes
all the program memory write latches simultaneously
to program memory. After NOPs, the processor
stalls until the self-write process in complete
; after write processor continues with 3rd instruction
; Disable writes
; Enable interrupts
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
10.3
Modifying Flash Program Memory
When modifying existing data in a program memory
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
1.
2.
3.
4.
5.
6.
7.
Load the starting address of the row to be
modified.
Read the existing data from the row into a RAM
image.
Modify the RAM image to contain the new data
to be written into program memory.
Load the starting address of the row to be
rewritten.
Erase the program memory row.
Load the write latches with data from the RAM
image.
Initiate a programming operation.
TABLE 10-2:
10.4
User ID, Device ID and
Configuration Word Access
Instead of accessing program memory, the User ID’s,
Device ID/Revision ID and Configuration Words can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 10-2.
When read access is initiated on an address outside
the
parameters
listed
in
Table 10-2,
the
PMDATH:PMDATL register pair is cleared, reading
back ‘0’s.
USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address
Function
Read Access
Write Access
8000h-8003h
8006h
8007h-8008h
User IDs
Device ID/Revision ID
Configuration Words 1 and 2
Yes
Yes
Yes
Yes
No
No
EXAMPLE 10-4:
CONFIGURATION WORD AND DEVICE ID ACCESS
* This code block will read 1 word of program memory at the memory address:
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
CLRF
PMADRL
PROG_ADDR_LO
PMADRL
PMADRH
; Select correct Bank
;
; Store LSB of address
; Clear MSB of address
BSF
BCF
BSF
NOP
NOP
BSF
PMCON1,CFGS
INTCON,GIE
PMCON1,RD
INTCON,GIE
;
;
;
;
;
;
Select Configuration Space
Disable interrupts
Initiate read
Executed (See Figure 10-1)
Ignored (See Figure 10-1)
Restore interrupts
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
Get LSB of word
Store in user location
Get MSB of word
Store in user location
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 87
PIC16LF1902/3
10.5
Write Verify
Depending on the application, good programming
practice may dictate that the value written to program
memory should be verified to the desired value to be
written.
DS41455A-page 88
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
REGISTER 10-1:
R/W-x/u
PMDATL: PROGRAM MEMORY DATA REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
PMDAT<7:0>: Read/write value for Least Significant bits of program memory
REGISTER 10-2:
PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
PMDAT<13:8>: Read/write value for Most Significant bits of program memory
REGISTER 10-3:
R/W-0/0
PMADRL: PROGRAM MEMORY ADDRESS REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
PMADR<7:0>: Specifies the Least Significant bits for program memory address
REGISTER 10-4:
U-1
PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
R/W-0/0
R/W-0/0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<14:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘1’
bit 6-0
PMADR<14:8>: Specifies the Most Significant bits for program memory address
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 89
PIC16LF1902/3
REGISTER 10-5:
PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
U-1(1)
R/W-0/0
R/W-0/0
R/W/HC-0/0
R/W/HC-x/q(2)
R/W-0/0
R/S/HC-0/0
R/S/HC-0/0
—
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7
Unimplemented: Read as ‘1’
bit 6
CFGS: Configuration Select bit
1 = Access Configuration, User ID and Device ID Registers
0 = Access Flash Program Memory
bit 5
LWLO: Load Write Latches Only bit(3)
1 = Only the addressed program memory write latch is loaded/updated on the next WR command
0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches
will be initiated on the next WR command
bit 4
FREE: Program Flash Erase Enable bit
1 = Performs an erase operation on the next WR command (hardware cleared upon completion)
0 = Performs an write operation on the next WR command
bit 3
WRERR: Program/Erase Error Flag bit
1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically
on any set attempt (write ‘1’) of the WR bit).
0 = The program or erase operation completed normally.
bit 2
WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1
WR: Write Control bit
1 = Initiates a program Flash program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive.
bit 0
RD: Read Control bit
1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set
(not cleared) in software.
0 = Does not initiate a program Flash read.
Note 1:
2:
3:
Unimplemented bit, read as ‘1’.
The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1).
The LWLO bit is ignored during a program memory erase operation (FREE = 1).
DS41455A-page 90
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
REGISTER 10-6:
W-0/0
PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
Program Memory Control Register 2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Flash memory Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.
TABLE 10-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
—
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
90
PMCON1
PMCON2
Program Memory Control Register 2
91
PMADRL
PMADRL<7:0>
89
—
PMADRH
PMADRH<6:0>
PMDATL
PMDATH
—
—
INTCON
GIE
PEIE
Legend:
CONFIG1
CONFIG2
Legend:
89
PMDATH<5:0>
TMR0IE
INTE
IOCIE
89
TMR0IF
INTF
IOCIF
66
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module.
TABLE 10-4:
Name
89
PMDATL<7:0>
Bits
SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
Bit 10/2
13:8
—
—
FCMEN
7:0
CP
MCLRE
PWRTE
13:8
—
—
LVP
DEBUG
ULPBOR
BORV
7:0
—
—
—
—
—
—
Bit 9/1
Bit 8/0
—
BOREN<1:0>
WDTE<1:0>
FOSC<2:0>
STVREN
—
WRT<1:0>
Register
on Page
46
48
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 91
PIC16LF1902/3
NOTES:
DS41455A-page 92
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
11.0
I/O PORTS
FIGURE 11-1:
GENERIC I/O PORT
OPERATION
In general, when a peripheral is enabled on a port pin,
that pin cannot be used as a general purpose output.
However, the pin can still be read.
Each port has three standard registers for its operation.
These registers are:
• TRISx registers (data direction)
• PORTx registers (reads the levels on the pins of
the device)
• LATx registers (output latch)
D
Write LATx
Write PORTx
Some ports may have one or more of the following
additional registers. These registers are:
Q
CK
VDD
Data Register
Data Bus
Read PORTx
To peripherals
ANSELx
Device
PORTA
PORTB
PORTC
PORTE
PORT AVAILABILITY PER
DEVICE
PIC16LF1902/3
●
●
●
●
The Data Latch (LATA register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A write operation to the LATA register has the same
affect as a write to the corresponding PORTA register.
A read of the LATA register reads of the values held in
the I/O PORT latches, while a read of the PORTA
register reads the actual I/O pin value.
EXAMPLE 11-1:
;
;
;
;
VSS
INITIALIZING PORTA
This code example illustrates
initializing the PORTA register. The
other ports are initialized in the same
manner.
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
The port has analog functions and has an ANSELA.
register which can disable the digital input and save
power. A simplified model of a generic I/O port, without
the interfaces to other peripherals, is shown in
Figure 11-1.
 2011 Microchip Technology Inc.
TRISx
I/O pin
• ANSELx (analog select)
• WPUx (weak pull-up)
TABLE 11-1:
Read LATx
Preliminary
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00111000'
TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<5:3> as inputs
;and set RA<2:0> as
;outputs
DS41455A-page 93
PIC16LF1902/3
11.1
11.1.2
PORTA Registers
PORTA is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 11-2). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). The exception is RA3, which is
input only and its TRIS bit will always read as ‘1’.
Example 11-1 shows how to initialize PORTA.
Reading the PORTA register (Register 11-1) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATA).
PORTA FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTA pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 11-2.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input functions, such as ADC, comparator and
CapSense inputs, are not shown in the priority lists.
These inputs are active when the I/O pin is set for
Analog mode using the ANSELx registers. Digital
output functions may control the pin when it is in Analog
mode with the priority shown in Table 11-2.
TABLE 11-2:
Pin Name
PORTA OUTPUT PRIORITY
Function Priority(1)
The TRISA register (Register 11-2) controls the
PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
RA0
SEG12 (LCD)
AN0
RA0
RA1
SEG7
AN1
RA1
11.1.1
RA2
COM2
AN2
RA2
RA3
VREF+
COM3
SEG15
AN3
RA3
RA4
SEG4
T0CKI
RA4
RA5
SEG6
AN5
RA5
RA6
CLKOUT
SEG1
RA6
RA7
CLKIN
SEG2
RA7
ANSELA REGISTER
The ANSELA register (Register 11-4) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note:
The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
Note 1:
DS41455A-page 94
Preliminary
Priority listed from highest to lowest.
 2011 Microchip Technology Inc.
PIC16LF1902/3
REGISTER 11-1:
PORTA: PORTA REGISTER
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R-x/x
R/W-x/x
R/W-x/x
R/W-x/x
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
RA<7:0>: PORTA I/O Value bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 7-0
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of
actual I/O pin values.
REGISTER 11-2:
TRISA: PORTA TRI-STATE REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
TRISA<7:4>: PORTA Tri-State Control bits
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
bit 3
TRISA3: RA3 Port Tri-State Control bit
This bit is always ‘1’ as RA3 is an input only
bit 2-0
TRISA<2:0>: PORTA Tri-State Control bits
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
REGISTER 11-3:
LATA: PORTA DATA LATCH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Note 1:
LATA<7:0>: RA<7:4> Output Latch Value bits(1)
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of
actual I/O pin values.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 95
PIC16LF1902/3
REGISTER 11-4:
ANSELA: PORTA ANALOG SELECT REGISTER
U-0
U-0
R/W-1/1
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
—
—
ANSA5
—
ANSA3
ANSA2
ANSA1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5
ANSA5: Analog Select between Analog or Digital Function on pins RA5, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 4
Unimplemented: Read as ‘0’
bit 3-0
ANSA<3:0>: Analog Select between Analog or Digital Function on pins RA<3:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
TABLE 11-3:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
ANSELA
LATA
OPTION_REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
—
—
ANSA5
—
ANSA3
ANSA2
ANSA1
ANSA0
96
LATA2
LATA1
LATA0
LATA7
LATA6
LATA5
LATA4
LATA3
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
95
PS<2:0>
129
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
95
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
95
Legend:
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
TABLE 11-4:
Name
CONFIG1
Legend:
Bits
SUMMARY OF CONFIGURATION WORD WITH PORTA
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
—
CLKOUTEN
13:8
—
—
—
7:0
CP
MCLRE
PWRTE
Bit 10/2
WDTE<1:0>
Bit 9/1
BOREN<1:0>
—
Bit 8/0
—
FOSC<1:0>
Register
on Page
38
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
DS41455A-page 96
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
11.2
11.2.2
PORTB Registers
PORTB is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISB
(Register 11-6). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 11-1 shows how to initialize an I/O port.
Reading the PORTB register (Register 11-5) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATB).
Each PORTB pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 11-5.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in Table 11-5.
TABLE 11-5:
Pin Name
The TRISB register (Register 11-6) controls the PORTB
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
11.2.1
The state of the ANSELB bits has no effect on digital output functions. A pin with TRIS clear and ANSELB set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected
port.
The ANSELB bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
Note 1:
 2011 Microchip Technology Inc.
Preliminary
PORTB OUTPUT PRIORITY
Function Priority(1)
RB0
SEG0
AN12
INT
IOC
RB0
RB1
SEG24
AN10
VLCD1
IOC
RB1
RB2
SEG25
AN8
VLCD2
IOC
RB2
RB3
SEG26
AN9
VLCD3
IOC
RB3
RB4
COM0
AN11
IOC
RB4
RB5
COM1
AN13
IOC
RB5
RB6
SEG14
IOC
RB6
RB7
SEG13
IOC
RB7
ANSELB REGISTER
The ANSELB register (Register 11-8) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
Note:
PORTB FUNCTIONS AND OUTPUT
PRIORITIES
Priority listed from highest to lowest.
DS41455A-page 97
PIC16LF1902/3
REGISTER 11-5:
PORTB: PORTB REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
RB<7:0>: PORTB General Purpose I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 7-0
Note 1:
Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
REGISTER 11-6:
TRISB: PORTB TRI-STATE REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
TRISB<7:0>: PORTB Tri-State Control bits
1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
REGISTER 11-7:
LATB: PORTB DATA LATCH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
LATB<7:0>: PORTB Output Latch Value bits(1)
Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
DS41455A-page 98
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
REGISTER 11-8:
ANSELB: PORTB ANALOG SELECT REGISTER
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
ANSB<5:0>: Analog Select between Analog or Digital Function on pins RB<5:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external
control of the voltage on the pin.
REGISTER 11-9:
WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
2:
WPUB<7:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
TABLE 11-6:
Name
ANSELB
LATB
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
99
98
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
98
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
98
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
99
WPUB
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 99
PIC16LF1902/3
11.3
11.3.1
PORTC Registers
PORTC is an 8-bit wide bidirectional port. The
corresponding data direction register is TRISC
(Register 11-6). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 11-1 shows how to initialize an I/O port.
Reading the PORTC register (Register 11-5) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATC).
PORTC FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTC pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 11-7.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in Table 11-7.
TABLE 11-7:
Pin Name
The TRISC register (Register 11-6) controls the PORTC
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISC register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
Preliminary
Function Priority(1)
RC0
SOSCO (T1OSCO)
T1CKI
RC0
RC1
SOSC1 (T1OSCI)
RC1
RC2
SEG2
RC2
RC3
SEG6
RC3
RC4
SEG11
T1G
RC4
RC5
SEG10
RC5
RC6
SEG9
RC6
RC7
SEG8
RC7
Note 1:
DS41455A-page 100
PORTC OUTPUT PRIORITY
Priority listed from highest to lowest.
 2011 Microchip Technology Inc.
PIC16LF1902/3
REGISTER 11-10: PORTC: PORTC REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
RC<7:0>: PORTC General Purpose I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 7-0
Note 1:
Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
REGISTER 11-11: TRISC: PORTC TRI-STATE REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
TRISC<7:0>: PORTC Tri-State Control bits(1)
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
bit 7-0
REGISTER 11-12: LATC: PORTC DATA LATCH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
LATC<7:0>: PORTC Output Latch Value bits(1)
Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 101
PIC16LF1902/3
TABLE 11-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
98
Name
LATC
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
98
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
98
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
DS41455A-page 102
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
11.4
11.4.1
PORTE Registers
RE3 is input only, and also functions as MCLR. The
MCLR feature can be disabled via a configuration fuse.
RE3 also supplies the programming voltage. The TRIS bit
for RE3 (TRISE3) always reads ‘1’.
PORTE FUNCTIONS AND OUTPUT
PRIORITIES
No output priorities, RE3 is an input only pin.
REGISTER 11-13: PORTE: PORTE REGISTER
U-0
U-0
U-0
U-0
R-x/u
U-0
U-0
U-0
—
—
—
—
RE3
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3
RE3: PORTE Input Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 2-0
Unimplemented: Read as ‘0’
REGISTER 11-14: TRISE: PORTE TRI-STATE REGISTER
U-0
U-0
U-0
U-0
U-1(1)
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3
Unimplemented: Read as ‘1’
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
Unimplemented, read as ‘1’.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 103
PIC16LF1902/3
REGISTER 11-15: WPUE: WEAK PULL-UP PORTE REGISTER
U-0
U-0
U-0
U-0
R/W-1/1
U-0
U-0
U-0
—
—
—
—
WPUE3
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3
WPUE: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
2:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
TABLE 11-9:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7
ADCON0
—
PORTE
—
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CHS<4:0>
—
—
Bit 1
Bit 0
Register
on Page
GO/DONE
ADON
119
—
RE3
—
—
—
103
—
—
—
103
—
—
—
104
TRISE
—
—
—
—
—(1)
WPUE
—
—
—
—
WPUE3
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTE.
Note 1: Unimplemented, read as ‘1’.
DS41455A-page 104
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
12.0
INTERRUPT-ON-CHANGE
12.3
The PORTB pins can be configured to operate as
Interrupt-On-Change (IOC) pins. An interrupt can be
generated by detecting a signal that has either a rising
edge or a falling edge. Any individual PORTB pin, or
combination of PORTB pins, can be configured to
generate an interrupt. The interrupt-on-change module
has the following features:
•
•
•
•
Interrupt-on-Change enable (Master Switch)
Individual pin configuration
Rising and falling edge detection
Individual pin interrupt flags
The IOCBFx bits located in the IOCBF register are
status flags that correspond to the Interrupt-on-change
pins of PORTB. If an expected edge is detected on an
appropriately enabled pin, then the status flag for that pin
will be set, and an interrupt will be generated if the IOCIE
bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCBFx bits.
12.4
Clearing Interrupt Flags
The individual status flags, (IOCBFx bits), can be
cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
Figure 12-1 is a block diagram of the IOC module.
12.1
Interrupt Flags
Enabling the Module
To allow individual PORTB pins to generate an interrupt,
the IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
EXAMPLE 12-1:
12.2
Individual Pin Configuration
For each PORTB pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a
rising edge, the associated IOCBPx bit of the IOCBP
register is set. To enable a pin to detect a falling edge,
the associated IOCBNx bit of the IOCBN register is set.
A pin can be configured to detect rising and falling
edges simultaneously by setting both the IOCBPx bit
and the IOCBNx bit of the IOCBP and IOCBN registers,
respectively.
FIGURE 12-1:
MOVLW
XORWF
ANDWF
12.5
0xff
IOCBF, W
IOCBF, F
Operation in Sleep
The Interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCBF
register will be updated prior to the first instruction
executed out of Sleep.
INTERRUPT-ON-CHANGE BLOCK DIAGRAM
IOCIE
IOCBNx
D
Q
IOCBFx
From all other IOCBFx
individual pin detectors
CK
R
IOC Interrupt to
CPU Core
RBx
IOCBPx
D
Q
CK
R
Q2 Clock Cycle
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 105
PIC16LF1902/3
REGISTER 12-1:
IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
IOCBP<7:0>: Interrupt-on-Change Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 12-2:
IOCBN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
IOCBN<7:0>: Interrupt-on-Change Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 12-3:
IOCBF: INTERRUPT-ON-CHANGE FLAG REGISTER
R/W/HS-0/0
R/W/HS-0/0
IOCBF7
IOCBF6
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCBF5
IOCBF4
IOCBF3
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
IOCBF2
IOCBF1
IOCBF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS - Bit is set in hardware
bit 7-0
IOCBF<7:0>: Interrupt-on-Change Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling
edge was detected on RBx.
0 = No change was detected, or the user cleared the detected change.
DS41455A-page 106
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
TABLE 12-1:
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
99
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
Name
IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBF0
106
IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
106
IOCBP
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
106
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
98
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 107
PIC16LF1902/3
NOTES:
DS41455A-page 108
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
13.0
FIXED VOLTAGE REFERENCE
(FVR)
13.1
Independent Gain Amplifiers
The output of the FVR supplied to the ADC is routed
through two independent programmable gain
amplifiers. Each amplifier can be configured to amplify
the reference voltage by 1x or 2x, to produce the two
possible voltage levels.
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V or
2.048V selectable output levels. The output of the FVR
can be configured to supply a reference voltage to the
following:
The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Reference Section 15.0 “Analog-to-Digital Converter
(ADC) Module” for additional information.
• ADC input channel
• ADC positive reference
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
13.2
FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Section 21.0 “Electrical Specifications” for the
minimum delay requirement.
FIGURE 13-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0>
2
x1
x2
FVR BUFFER1
(To ADC Module)
1.024V Fixed
Reference
+
FVREN
FVRRDY
-
Any peripheral requiring
the Fixed Reference
(See Table 13-1)
TABLE 13-1:
Peripheral
PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)
Conditions
Description
HFINTOSC
FOSC<2:0> = 100 and
IRCF<3:0> = 000x
BOREN<1:0> = 11
BOR always enabled
BOR
BOREN<1:0> = 10 and BORFS = 1
BOR disabled in Sleep mode, BOR Fast Start enabled.
BOREN<1:0> = 01 and BORFS = 1
BOR under software control, BOR Fast Start enabled
 2011 Microchip Technology Inc.
INTOSC is active and device is not in Sleep
Preliminary
DS41455A-page 109
PIC16LF1902/3
REGISTER 13-1:
FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0
R-q/q
R/W-0/0
R/W-0/0
U-0
U-0
FVREN
FVRRDY(1)
TSEN
TSRNG
—
—
R/W-0/0
R/W-0/0
ADFVR<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
FVREN: Fixed Voltage Reference Enable bit
0 = Fixed Voltage Reference is disabled
1 = Fixed Voltage Reference is enabled
bit 6
FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
0 = Fixed Voltage Reference output is not ready or not enabled
1 = Fixed Voltage Reference output is ready for use
bit 5
TSEN: Temperature Indicator Enable bit
0 = Temperature Indicator is disabled
1 = Temperature Indicator is enabled
bit 4
TSRNG: Temperature Indicator Range Selection bit
0 = VOUT = VDD - 2VT (Low Range)
1 = VOUT = VDD - 4VT (High Range)
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit
00 = ADC Fixed Voltage Reference Peripheral output is off.
01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)
10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
11 = Reserved
Note 1:
2:
FVRRDY will output the true state of the band gap.
Fixed Voltage Reference output cannot exceed VDD.
TABLE 13-2:
Name
FVRCON
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on page
FVREN
FVRRDY
TSEN
TSRNG
—
—
ADFVR1
ADFVR0
110
Shaded cells are not used with the Fixed Voltage Reference.
DS41455A-page 110
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
14.0
TEMPERATURE INDICATOR
MODULE
FIGURE 14-1:
This family of devices is equipped with a temperature
circuit designed to measure the operating temperature
of the silicon die. The circuit’s range of operating
temperature falls between of -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC.
VDD
TSEN
TSRNG
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator,
depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, “Use and Calibration of the Internal
Temperature Indicator” (DS01333) for more details
regarding the calibration process.
14.1
TEMPERATURE CIRCUIT
DIAGRAM
VOUT
ADC
MUX
ADC
n
CHS bits
(ADCON0 register)
Circuit Operation
Figure 14-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is
achieved by measuring the forward voltage drop across
multiple silicon junctions.
Equation 14-1 describes the output characteristics of
the temperature indicator.
EQUATION 14-1:
VOUT RANGES
High Range: VOUT = VDD - 4VT
14.2
Minimum Operating VDD vs.
Minimum Sensing Temperature
When the temperature circuit is operated in low range,
the device may be operated at any operating voltage
that is within specifications.
When the temperature circuit is operated in high range,
the device operating voltage, VDD, must be high
enough to ensure that the temperature circuit is correctly biased.
Table 14-1 shows the recommended minimum VDD vs.
range setting.
Low Range: VOUT = VDD - 2VT
TABLE 14-1:
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See
Section 13.0 “Fixed Voltage Reference (FVR)” for
more information.
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.
 2011 Microchip Technology Inc.
RECOMMENDED VDD VS.
RANGE
Min. VDD, TSRNG = 1
Min. VDD, TSRNG = 0
3.6V
1.8V
14.3
Temperature Output
The output of the circuit is measured using the internal
Analog-to-Digital converter. A channel is reserved for
the temperature circuit output. Refer to Section 15.0
“Analog-to-Digital Converter (ADC) Module” for
detailed information.
14.4
ADC Acquisition Time
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between sequential
conversions of the temperature indicator output.
Preliminary
DS41455A-page 111
PIC16LF1902/3
NOTES:
DS41455A-page 112
Preliminary
 2011 Microchip Technology Inc.
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15.0
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 15-1 shows the block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
FIGURE 15-1:
ADC BLOCK DIAGRAM
VDD
ADPREF = 00
VREF+
AN0
00000
AN1
00001
AN2
00010
VREF+/AN3
00011
AN4
00100
Reserved
00101
Reserved
00110
Reserved
00111
AN8
01000
AN9
01001
AN10
01010
AN11
01011
AN12
01100
AN13
01101
ADPREF = 10
ADC
10
GO/DONE
ADFM
ADON(1)
16
VSS
Temperature Indicator
11101
Reserved
11110
FVR Buffer1
11111
0 = Left Justify
1 = Right Justify
ADRESH
ADRESL
CHS<4:0>(2)
Note 1:
2:
When ADON = 0, all multiplexer inputs are disconnected.
See ADCON0 register (Example 15-1) for detailed analog channel selection per device.
 2011 Microchip Technology Inc.
Preliminary
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15.1
15.1.4
ADC Configuration
When configuring and using the ADC the following
functions must be considered:
•
•
•
•
•
•
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Result formatting
15.1.1
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 11.0 “I/O Ports” for more information.
Note:
15.1.2
The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
•
•
•
•
•
•
•
PORT CONFIGURATION
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 15-2.
For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 21.0 “Electrical Specifications” for
more information. Table 15-1 gives examples of appropriate ADC clock selections.
Note:
CHANNEL SELECTION
CONVERSION CLOCK
There are up to 11 channel selections available:
• AN<13:0> pins
• Temperature Indicator
• FVR (Fixed Voltage Reference) Output
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
Refer to Section 13.0 “Fixed Voltage Reference
(FVR)” and Section 14.0 “Temperature Indicator
Module” for more information on these channel selections.
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 15.2
“ADC Operation” for more information.
15.1.3
ADC VOLTAGE REFERENCE
The ADPREF bits of the ADCON1 register provides
control of the positive voltage reference. The positive
voltage reference can be:
• VREF+ pin
• VDD
• FVR
See Section 13.0 “Fixed Voltage Reference (FVR)”
for more details on the fixed voltage reference.
DS41455A-page 114
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
TABLE 15-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
Clock Source
ADCS<2:0>
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
FOSC/2
000
100 ns(2)
125 ns(2)
250 ns(2)
500 ns(2)
2.0 s
FOSC/4
100
200 ns
(2)
(2)
(2)
FOSC/8
001
400 ns(2)
0.5 s(2)
FOSC/16
101
800 ns
010
FOSC/64
FRC
FOSC/32
Legend:
Note 1:
2:
3:
4:
1.0 s
4.0 s
1.0 s
2.0 s
8.0 s(3)
1.0 s
2.0 s
4.0 s
16.0 s(3)
1.6 s
2.0 s
4.0 s
110
3.2 s
4.0 s
x11
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
250 ns
500 ns
8.0 s
(3)
1.0-6.0 s(1,4)
8.0 s
(3)
16.0 s
(3)
1.0-6.0 s(1,4)
32.0 s(3)
64.0 s(3)
1.0-6.0 s(1,4)
Shaded cells are outside of recommended range.
The FRC source has a typical TAD time of 1.6 s for VDD.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
FIGURE 15-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b4
b1
b0
b6
b7
b2
b9
b8
b3
b5
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 115
PIC16LF1902/3
15.1.5
INTERRUPTS
15.1.6
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON1 register controls the output format.
Figure 15-3 shows the two output formats.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
FIGURE 15-3:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
10-bit A/D Result
Unimplemented: Read as ‘0’
MSB
(ADFM = 1)
bit 7
LSB
bit 0
Unimplemented: Read as ‘0’
DS41455A-page 116
bit 0
bit 7
bit 0
10-bit A/D Result
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
15.2
15.2.1
15.2.4
ADC Operation
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the
GO/DONE bit of the ADCON0 register to a ‘1’ will start
the Analog-to-Digital conversion.
Note:
15.2.2
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 15.2.5 “A/D Conversion
Procedure”.
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
• Update the ADRESH and ADRESL registers with
new conversion result
15.2.3
ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH and ADRESL registers will be updated with
the partially complete Analog-to-Digital conversion
sample. Incomplete bits will match the last bit
converted.
Note:
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
 2011 Microchip Technology Inc.
Preliminary
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PIC16LF1902/3
15.2.5
A/D CONVERSION PROCEDURE
EXAMPLE 15-1:
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1.
2.
3.
4.
5.
6.
7.
8.
Configure Port:
• Disable pin output driver (Refer to the TRIS
register)
• Configure pin as analog (Refer to the ANSEL
register)
Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Turn on ADC module
Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
A/D CONVERSION
;This code block configures the ADC
;for polling, Vdd and Vss references, Frc
;clock and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL
ADCON1
;
MOVLW
B’11110000’ ;Right justify, Frc
;clock
MOVWF
ADCON1
;Vdd and Vss Vref
BANKSEL
TRISA
;
BSF
TRISA,0
;Set RA0 to input
BANKSEL
ANSEL
;
BSF
ANSEL,0
;Set RA0 to analog
BANKSEL
ADCON0
;
MOVLW
B’00000001’ ;Select channel AN0
MOVWF
ADCON0
;Turn ADC On
CALL
SampleTime
;Acquisiton delay
BSF
ADCON0,ADGO ;Start conversion
BTFSC
ADCON0,ADGO ;Is conversion done?
GOTO
$-1
;No, test again
BANKSEL
ADRESH
;
MOVF
ADRESH,W
;Read upper 2 bits
MOVWF
RESULTHI
;store in GPR space
BANKSEL
ADRESL
;
MOVF
ADRESL,W
;Read lower 8 bits
MOVWF
RESULTLO
;Store in GPR space
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 15.3 “A/D Acquisition
Requirements”.
DS41455A-page 118
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
15.2.6
ADC REGISTER DEFINITIONS
The following registers are used to control the
operation of the ADC.
REGISTER 15-1:
U-0
ADCON0: A/D CONTROL REGISTER 0
R/W-0/0
R/W-0/0
—
R/W-0/0
R/W-0/0
R/W-0/0
CHS<4:0>
R/W-0/0
R/W-0/0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-2
CHS<4:0>: Analog Channel Select bits
00000 = AN0
00001 = AN1
00010 = AN2
00011 = AN3
00100 = AN4
00101 = Reserved. No channel connected.
00110 = Reserved. No channel connected.
00111 = Reserved. No channel connected.
01000 = AN8
01001 = AN9
01010 = AN10
01011 = AN11
01100 = AN12
01101 = AN13
01110 = Reserved. No channel connected.
•
•
•
11100 = Reserved. No channel connected.
11101 = Temperature Indicator(2)
11110 = Reserved. No channel connected.
11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(1)
bit 1
GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0
ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1:
2:
See Section 13.0 “Fixed Voltage Reference (FVR)” for more information.
See Section 14.0 “Temperature Indicator Module” for more information.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 119
PIC16LF1902/3
REGISTER 15-2:
R/W-0/0
ADCON1: A/D CONTROL REGISTER 1
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
ADCS<2:0>
U-0
U-0
—
—
R/W-0/0
R/W-0/0
ADPREF<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4
ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock supplied from a dedicated RC oscillator)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC (clock supplied from a dedicated RC oscillator)
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits
00 = VREF+ is connected to VDD
01 = Reserved
10 = VREF+ is connected to external VREF+ pin(1)
11 = Reserved
Note 1:
When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a
minimum voltage specification exists. See Section 21.0 “Electrical Specifications” for details.
DS41455A-page 120
Preliminary
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PIC16LF1902/3
REGISTER 15-3:
R/W-x/u
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:2>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
ADRES<9:2>: ADC Result Register bits
Upper 8 bits of 10-bit conversion result
REGISTER 15-4:
R/W-x/u
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u
ADRES<1:0>
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
ADRES<1:0>: ADC Result Register bits
Lower 2 bits of 10-bit conversion result
bit 5-0
Reserved: Do not use.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 121
PIC16LF1902/3
REGISTER 15-5:
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
—
—
—
—
—
—
R/W-x/u
R/W-x/u
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Reserved: Do not use.
bit 1-0
ADRES<9:8>: ADC Result Register bits
Upper 2 bits of 10-bit conversion result
REGISTER 15-6:
R/W-x/u
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
ADRES<7:0>: ADC Result Register bits
Lower 8 bits of 10-bit conversion result
DS41455A-page 122
Preliminary
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PIC16LF1902/3
15.3
A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 15-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 15-4. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 15-1:
Assumptions:
source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an A/D acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 15-1 may be
used. This equation assumes that 1/2 LSb error is used
(1,024 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k  5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  
The value for TC can be approximated with the following equations:
1
 = V CHOLD
V AP P LI ED  1 – -------------------------n+1


2
–1
;[1] VCHOLD charged to within 1/2 lsb
–TC
----------

RC
V AP P LI ED  1 – e  = V CHOLD


;[2] VCHOLD charge response to VAPPLIED
– Tc
---------

1
RC
 ;combining [1] and [2]
V AP P LI ED  1 – e  = V A PP LIE D  1 – -------------------------n+1



2
–1
Note: Where n = number of bits of the ADC.
Solving for TC:
T C = – C HOLD  R IC + R SS + R S  ln(1/511)
= – 10pF  1k  + 7k  + 10k   ln(0.001957)
= 1.12 µs
Therefore:
T A CQ = 2µs + 1.12µs +   50°C- 25°C   0.05 µs/°C  
= 4.42µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 123
PIC16LF1902/3
FIGURE 15-4:
ANALOG INPUT MODEL
VDD
Analog
Input
pin
Rs
VT  0.6V
CPIN
5 pF
VA
RIC  1k
Sampling
Switch
SS Rss
I LEAKAGE(1)
VT  0.6V
CHOLD = 10 pF
VSS/VREF-
6V
5V
VDD 4V
3V
2V
= Sample/Hold Capacitance
= Input Capacitance
Legend: CHOLD
CPIN
RSS
I LEAKAGE = Leakage current at the pin due to
various junctions
= Interconnect Resistance
RIC
RSS
= Resistance of Sampling Switch
SS
= Sampling Switch
VT
= Threshold Voltage
5 6 7 8 9 10 11
Sampling Switch
(k)
Note 1: Refer to Section 21.0 “Electrical Specifications”.
FIGURE 15-5:
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
ADC Output Code
3FDh
3FCh
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB
VREF-
DS41455A-page 124
1.5 LSB
Zero-Scale
Transition
Full-Scale
Transition
Preliminary
VREF+
 2011 Microchip Technology Inc.
PIC16LF1902/3
TABLE 15-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ADCON0
—
CHS4
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
119
ADCON1
ADFM
ADCS2
ADCS1
ADCS0
—
—
ADPREF1
ADPREF0
120
ADRESH
A/D Result Register High
ADRESL
A/D Result Register Low
121, 122
121, 122
ANSELA
—
—
ANSA5
—
ANSA3
ANSA2
ANSA1
ANSA0
96
ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
99
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
PIE1
TMR1GIE
ADIE
—
—
—
—
—
TMR1IE
67
PIR1
TMR1GIF
ADIF
—
—
—
—
—
TMR1IF
69
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
95
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
98
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
—
—
ADFVR1
ADFVR0
110
Legend:
x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not
used for ADC module.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 125
PIC16LF1902/3
NOTES:
DS41455A-page 126
Preliminary
 2011 Microchip Technology Inc.
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16.0
16.1.2
TIMER0 MODULE
8-BIT COUNTER MODE
The Timer0 module is an 8-bit timer/counter with the
following features:
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin.
•
•
•
•
•
•
8-Bit Counter mode using the T0CKI pin is selected by
setting the TMR0CS bit in the OPTION_REG register to
‘1’.
8-bit timer/counter register (TMR0)
8-bit prescaler (independent of Watchdog Timer)
Programmable internal or external clock source
Programmable external clock edge selection
Interrupt on overflow
TMR0 can be used to gate Timer1
The rising or falling transition of the incrementing edge
is determined by the TMR0SE bit in the OPTION_REG
register.
Figure 16-1 is a block diagram of the Timer0 module.
16.1
Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
16.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note:
The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
FIGURE 16-1:
BLOCK DIAGRAM OF THE TIMER0
FOSC/4
Data Bus
0
8
T0CKI
1
Sync
2 TCY
1
TMR0
0
TMR0SE TMR0CS
8-bit
Prescaler
PSA
Set Flag bit TMR0IF
on Overflow
Overflow to Timer1
8
PS<2:0>
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Preliminary
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PIC16LF1902/3
16.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
Note:
The Watchdog Timer (WDT) uses its own
independent prescaler.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION_REG
register. In order to have a 1:1 prescaler value for the
Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
16.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
Note:
16.1.5
The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep.
8-BIT COUNTER MODE
SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 21.0 “Electrical
Specifications”.
16.1.6
OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
DS41455A-page 128
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 2011 Microchip Technology Inc.
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REGISTER 16-1:
OPTION_REG: OPTION REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
R/W-1/1
R/W-1/1
R/W-1/1
PS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
WPUEN: Weak Pull-up Enable bit
1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5
TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4
TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS<2:0>: Prescaler Rate Select bits
TABLE 16-1:
Name
INTCON
TRISA
Timer0 Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
OPTION_REG WPUEN
TMR0
Bit Value
INTEDG TMR0CS TMR0SE
PSA
PS<2:0>
129
Timer0 Module Register
TRISA7
TRISA6
TRISA5
127*
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
95
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
* Page provides register information.
 2011 Microchip Technology Inc.
Preliminary
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NOTES:
DS41455A-page 130
Preliminary
 2011 Microchip Technology Inc.
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17.0
• Gate Value Status
• Gate Event Interrupt
TIMER1 MODULE WITH GATE
CONTROL
Figure 17-1 is a block diagram of the Timer1 module.
The Timer1 module is a 16-bit timer/counter with the
following features:
•
•
•
•
•
•
•
16-bit timer/counter register pair (TMR1H:TMR1L)
Programmable internal or external clock source
2-bit prescaler
Dedicated 32 kHz oscillator circuit
Multiple Timer1 gate (count enable) sources
Interrupt on overflow
Wake-up on overflow (external clock,
Asynchronous mode only)
• Selectable Gate Source Polarity
• Gate Toggle Mode
• Gate Single-pulse Mode
FIGURE 17-1:
TIMER1 BLOCK DIAGRAM
T1GSS<1:0>
T1G
T1GSPM
0
From Timer0
Overflow
0
T1G_IN
1
T1GVAL
0
Single Pulse
TMR1ON
T1GPOL
D
Q
CK
R
Q
1
Acq. Control
1
Q1
Data Bus
D
Q
RD
T1GCON
EN
Interrupt
T1GGO/DONE
Set
TMR1GIF
det
T1GTM
TMR1GE
Set flag bit
TMR1IF on
Overflow
TMR1ON
TMR1(2)
TMR1H
EN
TMR1L
Q
D
T1CLK
Synchronized
clock input
0
1
TMR1CS<1:0>
T1OSO
Reserved
T1OSC
T1OSI
T1SYNC
OUT
11
1
Synchronize(3)
Prescaler
1, 2, 4, 8
det
10
EN
0
T1OSCEN
(1)
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
2
T1CKPS<1:0>
FOSC/2
Internal
Clock
Sleep input
T1CKI
To LCD and Clock Switching Modules
Note 1: ST Buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
 2011 Microchip Technology Inc.
Preliminary
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PIC16LF1902/3
17.1
Timer1 Operation
17.2
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
The TMR1CS<1:0> and T1OSCEN bits of the T1CON
register are used to select the clock source for Timer1.
Table 17-2 displays the clock source selections.
17.2.1
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and increments on every selected edge of the external source.
INTERNAL CLOCK SOURCE
When the internal clock source is selected the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
When the FOSC internal clock source is selected, the
Timer1 register value will increment by four counts every
instruction clock cycle. Due to this condition, a 2 LSB
error in resolution will occur when reading the Timer1
value. To utilize the full resolution of Timer1, an
asynchronous input signal must be used to gate the
Timer1 clock input.
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 17-1 displays the Timer1 enable
selections.
TABLE 17-1:
Clock Source Selection
TIMER1 ENABLE
SELECTIONS
The following asynchronous source may be used:
• Asynchronous event on the T1G pin to Timer1
Gate
Timer1
Operation
TMR1ON
TMR1GE
0
0
Off
17.2.2
0
1
Off
1
0
Always On
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
1
1
Count Enabled
EXTERNAL CLOCK SOURCE
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI or the
capacitive sensing oscillator signal. Either of these
external clock sources can be synchronized to the
microcontroller system clock or they can run
asynchronously.
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the dedicated internal oscillator circuit.
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
•
•
•
•
TABLE 17-2:
Timer1 enabled after POR
Write to TMR1H or TMR1L
Timer1 is disabled
Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
CLOCK SOURCE SELECTIONS
TMR1CS1
TMR1CS0
T1OSCEN
Clock Source
0
0
x
Instruction Clock (FOSC/4)
0
1
x
System Clock (FOSC)
1
0
0
External Clocking on T1CKI Pin
1
0
1
Osc. Circuit on T1OSI/T1OSO Pins
1
1
x
LFINTOSC
DS41455A-page 132
Preliminary
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PIC16LF1902/3
17.3
Timer1 Prescaler
17.6
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 Gate
circuitry. This is also referred to as Timer1 Gate Enable.
Timer1 Gate can also be driven by multiple selectable
sources.
17.6.1
17.4
Timer1 Oscillator
A dedicated low-power 32.768 kHz oscillator circuit is
built-in between pins T1OSI (input) and T1OSO. This
internal circuit is to be used in conjunction with an
external 32.768 kHz crystal.
The oscillator circuit is enabled by setting the
T1OSCEN bit of the T1CON register. The oscillator will
continue to run during Sleep.
Note:
17.5
The oscillator requires a start-up and stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
Note:
17.5.1
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
TIMER1 GATE ENABLE
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit of the T1GCON register.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 17-3 for timing details.
TABLE 17-3:
TIMER1 GATE ENABLE
SELECTIONS
T1CLK
T1GPOL
T1G

0
0
Counts

0
1
Holds Count

1
0
Holds Count

1
1
Counts
Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 17.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
Timer1 Gate
17.6.2
Timer1 Operation
TIMER1 GATE SOURCE
SELECTION
The Timer1 Gate source can be selected from one of
four different sources. Source selection is controlled by
the T1GSS bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T1GPOL bit of the
T1GCON register.
TABLE 17-4:
T1GSS
TIMER1 GATE SOURCES
Timer1 Gate Source
00
Timer1 Gate Pin
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
 2011 Microchip Technology Inc.
Preliminary
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PIC16LF1902/3
17.6.2.1
T1G Pin Gate Operation
17.6.4
The T1G pin is one source for Timer1 Gate Control. It
can be used to supply an external source to the Timer1
Gate circuitry.
17.6.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 Gate circuitry.
17.6.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
The Timer1 Gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See Figure 17-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note:
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
TIMER1 GATE SINGLE-PULSE
MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next incrementing
edge. On the next trailing edge of the pulse, the
T1GGO/DONE bit will automatically be cleared. No other
gate events will be allowed to increment Timer1 until the
T1GGO/DONE bit is once again set in software. See
Figure 17-5 for timing details.
If the Single Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1
Gate source to be measured. See Figure 17-6 for
timing details.
17.6.5
TIMER1 GATE VALUE STATUS
When Timer1 Gate Value Status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
Gate is not enabled (TMR1GE bit is cleared).
17.6.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
Gate is not enabled (TMR1GE bit is cleared).
DS41455A-page 134
Preliminary
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PIC16LF1902/3
17.7
Timer1 Interrupt
17.8
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
•
•
•
•
TMR1ON bit of the T1CON register
TMR1IE bit of the PIE1 register
PEIE bit of the INTCON register
GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note:
The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
•
•
•
•
•
TMR1ON bit of the T1CON register must be set
TMR1IE bit of the PIE1 register must be set
PEIE bit of the INTCON register must be set
T1SYNC bit of the T1CON register must be set
TMR1CS bits of the T1CON register must be
configured
• T1OSCEN bit of the T1CON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
Timer1 oscillator will continue to operate in Sleep
regardless of the T1SYNC bit setting.
FIGURE 17-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
Arrows indicate counter increments.
In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 135
PIC16LF1902/3
FIGURE 17-3:
TIMER1 GATE ENABLE MODE
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
Timer1
N
FIGURE 17-4:
N+1
N+2
N+3
N+4
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
Timer1
DS41455A-page 136
N
N+1 N+2 N+3
N+4
Preliminary
N+5 N+6 N+7 N+8
 2011 Microchip Technology Inc.
PIC16LF1902/3
FIGURE 17-5:
TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
Timer1
TMR1GIF
N
N+1
Set by hardware on
falling edge of T1GVAL
Cleared by software
 2011 Microchip Technology Inc.
N+2
Preliminary
Cleared by
software
DS41455A-page 137
PIC16LF1902/3
FIGURE 17-6:
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
Timer1
TMR1GIF
DS41455A-page 138
N
Cleared by software
N+1
N+2
N+3
Set by hardware on
falling edge of T1GVAL
Preliminary
N+4
Cleared by
software
 2011 Microchip Technology Inc.
PIC16LF1902/3
17.9
Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 17-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 17-1:
R/W-0/u
T1CON: TIMER1 CONTROL REGISTER
R/W-0/u
TMR1CS<1:0>
R/W-0/u
R/W-0/u
T1CKPS<1:0>
R/W-0/u
R/W-0/u
U-0
R/W-0/u
T1OSCEN
T1SYNC
—
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
TMR1CS<1:0>: Timer1 Clock Source Select bits
11 = Reserved
10 = Timer1 clock source is pin or oscillator:
If T1OSCEN = 0:
External clock from T1CKI pin (on the rising edge)
If T1OSCEN = 1:
Crystal oscillator on T1OSI/T1OSO pins
01 = Timer1 clock source is system clock (FOSC)
00 = Timer1 clock source is instruction clock (FOSC/4)
bit 5-4
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: LP Oscillator Enable Control bit
1 = Dedicated Timer1 oscillator circuit enabled
0 = Dedicated Timer1 oscillator circuit disabled
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS<1:0> = 1X
1 = Do not synchronize external clock input
0 = Synchronize external clock input with system clock (FOSC)
TMR1CS<1:0> = 0X
This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.
bit 1
Unimplemented: Read as ‘0’
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Clears Timer1 Gate flip-flop
 2011 Microchip Technology Inc.
Preliminary
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PIC16LF1902/3
17.10 Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON), shown in
Register 17-2, is used to control Timer1 Gate.
REGISTER 17-2:
T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W/HC-0/u
R-x/x
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
R/W-0/u
R/W-0/u
T1GSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7
TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6
T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5
T1GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
T1GSPM: Timer1 Gate Single-Pulse Mode bit
1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 gate Single-Pulse mode is disabled
bit 3
T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
bit 2
T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 1-0
T1GSS<1:0>: Timer1 Gate Source Select bits
00 = Timer1 Gate pin
01 = Timer0 overflow output
10 = Reserved
11 = Reserved
DS41455A-page 140
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
TABLE 17-5:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
TMR1GIE
ADIE
—
—
—
—
—
TMR1IE
67
PIR1
TMR1GIF
ADIF
—
—
—
—
—
TMR1IF
69
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
135*
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
135*
PIE1
TRISC
TRISC7
TRISC6
T1CON
TMR1CS1 TMR1CS0
T1GCON
TMR1GE
T1GPOL
TRISC5
TRISC4
T1CKPS<1:0>
T1GTM
T1GSPM
TRISC3
TRISC2
T1OSCEN T1SYNC
T1GGO/
DONE
T1GVAL
TRISC1
TRISC0
101
—
TMR1ON
139
T1GSS1
T1GSS0
140
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.
* Page provides register information.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 141
PIC16LF1902/3
NOTES:
DS41455A-page 142
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
18.0
LIQUID CRYSTAL DISPLAY
(LCD) DRIVER MODULE
18.1
The module contains the following registers:
The Liquid Crystal Display (LCD) driver module
generates the timing control to drive a static or
multiplexed LCD panel. In the PIC16LF1902/3 device,
the module drives the panels of up to four commons
and up to 72 total segments. The LCD module also
provides control of the LCD pixel data.
The LCD driver module supports:
• Direct driving of LCD panel
• Three LCD clock sources with selectable prescaler
• Up to four common pins:
- Static (1 common)
- 1/2 multiplex (2 commons)
- 1/3 multiplex (3 commons)
- 1/4 multiplex (4 commons)
• 19 Segment pins
• Static, 1/2 or 1/3 LCD Bias
Note:
LCD Registers
•
•
•
•
•
LCD Control register (LCDCON)
LCD Phase register (LCDPS)
LCD Reference Ladder register (LCDRL)
LCD Contrast Control register (LCDCST)
LCD Reference Voltage Control register
(LCDREF)
• Up to 3 LCD Segment Enable registers (LCDSEn)
• Up to 12 LCD data registers (LCDDATAn)
COM3 and SEG15 share the same
physical pin on the PIC16LF1902/3,
therefore SEG15 is not available when
using 1/4 multiplex displays.
FIGURE 18-1:
LCD DRIVER MODULE BLOCK DIAGRAM
Data Bus
SEG<26:24, 15:0>(2)
LCDDATAx
MUX
Registers
To I/O Pads(1)
Timing Control
LCDCON
COM<3:0>(3)
LCDPS
To I/O Pads(1)
LCDSEn
FOSC/256
T1OSC
LFINTOSC
Note 1:
2:
Clock Source
Select and
Prescaler
These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of
the LCD module.
COM3 and SEG15 share the same physical pin, therefore SEG15 is not available when using 1/4 multiplex displays.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 143
PIC16LF1902/3
TABLE 18-1:
LCD SEGMENT AND DATA
REGISTERS
# of LCD Registers
Device
PIC16LF1902/3
Segment
Enable
Data
3
12
The LCDCON register (Register 18-1) controls the
operation of the LCD driver module. The LCDPS register (Register 18-2) configures the LCD clock source
prescaler and the type of waveform; Type-A or Type-B.
The LCDSEn registers (Register 18-5) configure the
functions of the port pins.
The following LCDSEn registers are available:
• LCDSE0
• LCDSE1
• LCDSE3
SE<7:0>
SE<15:8>
SE<26:24>
Once the module is initialized for the LCD panel, the
individual bits of the LCDDATAn registers are
cleared/set to represent a clear/dark pixel, respectively:
•
•
•
•
•
•
•
•
•
•
•
•
LCDDATA0
LCDDATA1
LCDDATA3
LCDDATA4
LCDDATA6
LCDDATA7
LCDDATA9
LCDDATA10
LCDDATA12
LCDDATA15
LCDDATA18
LCDDATA21
SEG<7:0>COM0
SEG<15:8>COM0
SEG<7:0>COM1
SEG<15:8>COM1
SEG<7:0>COM2
SEG<15:8>COM2
SEG<7:0>COM3
SEG<15:8>COM3
SEG<26:24>COM0
SEG<26:24>COM1
SEG<26:24>COM2
SEG<26:24>COM3
As an example,
Register 18-6.
LCDDATAn
is
detailed
in
Once the module is configured, the LCDEN bit of the
LCDCON register is used to enable or disable the LCD
module. The LCD panel can also operate during Sleep
by clearing the SLPEN bit of the LCDCON register.
DS41455A-page 144
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
REGISTER 18-1:
LCDCON: LIQUID CRYSTAL DISPLAY (LCD) CONTROL REGISTER
R/W-0/0
R/W-0/0
R/C-0/0
U-0
LCDEN
SLPEN
WERR
—
R/W-0/0
R/W-0/0
R/W-1/1
CS<1:0>
R/W-1/1
LMUX<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
C = Only clearable bit
bit 7
LCDEN: LCD Driver Enable bit
1 = LCD driver module is enabled
0 = LCD driver module is disabled
bit 6
SLPEN: LCD Driver Enable in Sleep Mode bit
1 = LCD driver module is disabled in Sleep mode
0 = LCD driver module is enabled in Sleep mode
bit 5
WERR: LCD Write Failed Error bit
1 = LCDDATAn register written while the WA bit of the LCDPS register = 0 (must be cleared in
software)
0 = No LCD write error
bit 4
Unimplemented: Read as ‘0’
bit 3-2
CS<1:0>: Clock Source Select bits
00 = FOSC/256
01 = T1OSC (Timer1)
1x = LFINTOSC (31 kHz)
bit 1-0
LMUX<1:0>: Commons Select bits
Multiplex
00
Static (COM0)
19
Static
01
1/2 (COM<1:0>)
38
1/2 or 1/3
10
1/3 (COM<2:0>)
57
1/2 or 1/3
11
Note 1:
Maximum Number of Pixels
LMUX<1:0>
1/4 (COM<3:0>)
PIC16LF1902/3
72
(1)
Bias
1/3
On these devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 72 segments.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 145
PIC16LF1902/3
REGISTER 18-2:
LCDPS: LCD PHASE REGISTER
R/W-0/0
R/W-0/0
R-0/0
R-0/0
WFT
BIASMD
LCDA
WA
R/W-0/0
R/W-0/0
R/W-1/1
R/W-1/1
LP<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
C = Only clearable bit
bit 7
WFT: Waveform Type bit
1 = Type-B phase changes on each frame boundary
0 = Type-A phase changes within each common type
bit 6
BIASMD: Bias Mode Select bit
When LMUX<1:0> = 00:
0 = Static Bias mode (do not set this bit to ‘1’)
When LMUX<1:0> = 01:
1 = 1/2 Bias mode
0 = 1/3 Bias mode
When LMUX<1:0> = 10:
1 = 1/2 Bias mode
0 = 1/3 Bias mode
When LMUX<1:0> = 11:
0 = 1/3 Bias mode (do not set this bit to ‘1’)
bit 5
LCDA: LCD Active Status bit
1 = LCD driver module is active
0 = LCD driver module is inactive
bit 4
WA: LCD Write Allow Status bit
1 = Writing to the LCDDATAn registers is allowed
0 = Writing to the LCDDATAn registers is not allowed
bit 3-0
LP<3:0>: LCD Prescaler Selection bits
1111 = 1:16
1110 = 1:15
1101 = 1:14
1100 = 1:13
1011 = 1:12
1010 = 1:11
1001 = 1:10
1000 = 1:9
0111 = 1:8
0110 = 1:7
0101 = 1:6
0100 = 1:5
0011 = 1:4
0010 = 1:3
0001 = 1:2
0000 = 1:1
DS41455A-page 146
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
REGISTER 18-3:
LCDREF: LCD REFERENCE VOLTAGE CONTROL REGISTER
R/W-0/0
U-0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
LCDIRE
—
LCDIRI
—
VLCD3PE
VLCD2PE
VLCD1PE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
C = Only clearable bit
bit 7
LCDIRE: LCD Internal Reference Enable bit
1 = Internal LCD Reference is enabled and connected to the Internal Contrast Control circuit
0 = Internal LCD Reference is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
LCDIRI: LCD Internal Reference Ladder Idle Enable bit
Allows the Internal FVR buffer to shut down when the LCD Reference Ladder is in power mode ‘B’
1 = When the LCD Reference Ladder is in power mode ‘B’, the LCD Internal FVR buffer is disabled.
0 = The LCD Internal FVR Buffer ignores the LCD Reference Ladder Power mode.
bit 4
Unimplemented: Read as ‘0’
bit 3
VLCD3PE: VLCD3 Pin Enable bit
1 = The VLCD3 pin is connected to the internal bias voltage LCDBIAS3(1)
0 = The VLCD3 pin is not connected
bit 2
VLCD2PE: VLCD2 Pin Enable bit
1 = The VLCD2 pin is connected to the internal bias voltage LCDBIAS2(1)
0 = The VLCD2 pin is not connected
bit 1
VLCD1PE: VLCD1 Pin Enable bit
1 = The VLCD1 pin is connected to the internal bias voltage LCDBIAS1(1)
0 = The VLCD1 pin is not connected
bit 0
Unimplemented: Read as ‘0’
Note 1:
Normal pin controls of TRISx and ANSELx are unaffected.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 147
PIC16LF1902/3
REGISTER 18-4:
LCDCST: LCD CONTRAST CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
LCDCST<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
C = Only clearable bit
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
LCDCST<2:0>: LCD Contrast Control bits
Selects the resistance of the LCD contrast control resistor ladder
Bit Value = Resistor ladder
000 = Minimum Resistance (Maximum contrast). Resistor ladder is shorted.
001 = Resistor ladder is at 1/7th of maximum resistance
010 = Resistor ladder is at 2/7th of maximum resistance
011 = Resistor ladder is at 3/7th of maximum resistance
100 = Resistor ladder is at 4/7th of maximum resistance
101 = Resistor ladder is at 5/7th of maximum resistance
110 = Resistor ladder is at 6/7th of maximum resistance
111 = Resistor ladder is at maximum resistance (Minimum contrast).
DS41455A-page 148
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
REGISTER 18-5:
LCDSEn: LCD SEGMENT ENABLE REGISTERS
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SEn
SEn
SEn
SEn
SEn
SEn
SEn
SEn
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
SEn: Segment Enable bits
1 = Segment function of the pin is enabled
0 = I/O function of the pin is enabled
REGISTER 18-6:
R/W-x/u
LCDDATAn: LCD DATA REGISTERS
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
SEGx-COMy: Pixel On bits
1 = Pixel on (dark)
0 = Pixel off (clear)
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 149
PIC16LF1902/3
18.2
Using bits CS<1:0> of the LCDCON register can select
any of these clock sources.
LCD Clock Source Selection
The LCD module has 3 possible clock sources:
18.2.1
• FOSC/256
• T1OSC
• LFINTOSC
The first clock source is the system clock divided by
256 (FOSC/256). This divider ratio is chosen to provide
about 1 kHz output when the system clock is 8 MHz.
The divider is not programmable. Instead, the LCD
prescaler bits LP<3:0> of the LCDPS register are used
to set the LCD frame clock rate.
LCD PRESCALER
A 4-bit counter is available as a prescaler for the LCD
clock. The prescaler is not directly readable or writable;
its value is set by the LP<3:0> bits of the LCDPS register,
which determine the prescaler assignment and prescale
ratio.
The prescale values are selectable from 1:1 through
1:16.
The second clock source is the T1OSC. This also gives
about 1 kHz when a 32.768 kHz crystal is used with the
Timer1 oscillator. To use the Timer1 oscillator as a
clock source, the T1OSCEN bit of the T1CON register
should be set.
The third clock source is the 31 kHz LFINTOSC, which
provides approximately 1 kHz output.
The second and third clock sources may be used to
continue running the LCD while the processor is in
Sleep.
FOSC
LCD CLOCK GENERATION
÷256
To Ladder
Power Control
T1OSC 32 kHz
Crystal Osc.
Static
÷2
1/2
4-bit Prog
Prescaler
÷ 32
Counter
Segment
Clock
÷1, 2, 3, 4
Ring Counter
1/3,
1/4
LFINTOSC
Nominal = 31 kHz
LP<3:0>
CS<1:0>
DS41455A-page 150
÷4
COM0
COM1
COM2
COM3
FIGURE 18-2:
LMUX<1:0>
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
18.3
TABLE 18-2:
LCD Bias Voltage Generation
The LCD module can be configured for one of three
bias types:
• Static Bias (2 voltage levels: VSS and VLCD)
• 1/2 Bias (3 voltage levels: VSS, 1/2 VLCD and
VLCD)
• 1/3 Bias (4 voltage levels: VSS, 1/3 VLCD,
2/3 VLCD and VLCD)
FIGURE 18-3:
LCD BIAS VOLTAGES
Static Bias
1/2 Bias
1/3 Bias
LCD Bias 0
VSS
VSS
VSS
LCD Bias 1
—
1/2 VDD
1/3 VDD
LCD Bias 2
—
1/2 VDD
2/3 VDD
LCD Bias 3
VLCD3
VLCD3
VLCD3
So that the user is not forced to place external components and use up to three pins for bias voltage generation,
internal contrast control and an internal reference ladder
are provided internally to the PIC16LF1902/3. Both of
these features may be used in conjunction with the external VLCD<3:1> pins, to provide maximum flexibility. Refer
to Figure 18-3.
LCD BIAS VOLTAGE GENERATION BLOCK DIAGRAM
LCDIRE
VDD
LCDA
Power Mode Switching
(LRLAP or LRLBP)
2
A
2
B
2
LCDCST<2:0>
VLCD3PE
LCDA
VLCD3
lcdbias3
VLCD2PE
VLCD2
lcdbias2
BIASMD
VLCD1PE
VLCD1
lcdbias1
lcdbias0
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 151
PIC16LF1902/3
18.4
18.4.2
LCD Bias Internal Reference
Ladder
The internal reference ladder can be used to divide the
LCD bias voltage two or three equally spaced voltages
that will be supplied to the LCD segment pins. To create
this, the reference ladder consists of three matched
resistors. Refer to Figure 18-3.
POWER MODES
The internal reference ladder may be operated in one of
three power modes. This allows the user to trade off LCD
contrast for power in the specific application. The larger
the LCD glass, the more capacitance is present on a
physical LCD segment, requiring more current to
maintain the same contrast level.
When in 1/2 Bias mode (BIASMD = 1), then the middle
resistor of the ladder is shorted out so that only two
voltages are generated. The current consumption of the
ladder is higher in this mode, with the one resistor
removed.
Three different power modes are available, LP, MP and
HP. The internal reference ladder can also be turned off
for applications that wish to provide an external ladder
or to minimize power consumption. Disabling the
internal reference ladder results in all of the ladders
being disconnected, allowing external voltages to be
supplied.
TABLE 18-3:
Whenever the LCD module is inactive (LCDA = 0), the
internal reference ladder will be turned off.
18.4.1
Power
Mode
BIAS MODE INTERACTION
LCD INTERNAL LADDER
POWER MODES (1/3 BIAS)
Nominal Resistance of
Entire Ladder
Nominal
IDD
3 Mohm
300 kohm
30 kohm
1 µA
10 µA
100 µA
Low
Medium
High
DS41455A-page 152
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
18.4.3
AUTOMATIC POWER MODE
SWITCHING
The LCDRL register allows switching between two
power modes, designated ‘A’ and ‘B’. ‘A’ Power mode
is active for a programmable time, beginning at the
time when the LCD segments transition. ‘B’ Power
mode is the remaining time before the segments or
commons change again. The LRLAT<2:0> bits select
how long, if any, that the ‘A’ Power mode is active.
Refer to Figure 18-4.
As an LCD segment is electrically only a capacitor, current is drawn only during the interval where the voltage
is switching. To minimize total device current, the LCD
internal reference ladder can be operated in a different
power mode for the transition portion of the duration.
This is controlled by the LCDRL Register
(Register 18-7).
FIGURE 18-4:
To implement this, the 5-bit prescaler used to divide
the 32 kHz clock down to the LCD controller’s 1 kHz
base rate is used to select the power mode.
LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM –
TYPE A
Single Segment Time
32 kHz Clock
Ladder Power
Control
‘H00
‘H01
‘H02
‘H03
‘H04
‘H05
‘H06
‘H07
‘H0E
‘H0F
‘H00
‘H01
Segment Clock
‘H3
LRLAT<2:0>
Segment Data
LRLAT<2:0>
Power Mode
Power Mode A
Power Mode B
Mode A
V1
COM0
V0
V1
SEG0
V0
V1
V0
COM0-SEG0
-V1
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 153
LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE A WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE)
Single Segment Time
Single Segment Time
32 kHz Clock
Ladder Power
Control
‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05
‘H06 ‘H07
‘H0E ‘H0F ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07
‘H0E ‘H0F
Segment Clock
Segment Data
Power Mode
Power Mode A
LRLAT<2:0> = 011
Power Mode B
Power Mode A
Power Mode B
LRLAT<2:0> = 011
Preliminary
V2
V1
COM0-SEG0
V0
-V1
-V2
PIC16LF1902/3
DS41455A-page 154
FIGURE 18-5:
 2011 Microchip Technology Inc.
 2011 Microchip Technology Inc.
FIGURE 18-6:
LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE B WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE)
Single Segment Time
Single Segment Time
Single Segment Time
Single Segment Time
32 kHz Clock
Ladder Power
Control
‘H00 ‘H01 ‘H02 ‘H03
‘H0E ‘H0F ‘H10 ‘H11 ‘H12 ‘H13
‘H1E ‘H1F ‘H00 ‘H01 ‘H02 ‘H03
‘H0E ‘H0F ‘H10 ‘H11 ‘H12 ‘H13
‘H1E ‘H1F
Mode B
Mode B
Segment Clock
Segment Data
Power Mode
Power Mode A
LRLAT<2:0> = 011
Power
Mode B
Power Mode A
LRLAT<2:0> = 011
Power
Mode B
Power Mode A
LRLAT<2:0> = 011
Power
Power Mode A
Power
LRLAT<2:0> = 011
Preliminary
V2
V1
COM0-SEG0
V0
-V1
DS41455A-page 155
PIC16LF1902/3
-V2
PIC16LF1902/3
REGISTER 18-7:
R/W-0/0
LCDRL: LCD REFERENCE LADDER CONTROL REGISTERS
R/W-0/0
LRLAP<1:0>
R/W-0/0
R/W-0/0
LRLBP<1:0>
U-0
R/W-0/0
—
R/W-0/0
R/W-0/0
LRLAT<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits
During Time interval A (Refer toFigure 18-4):
00 = Internal LCD Reference Ladder is powered down and unconnected
01 = Internal LCD Reference Ladder is powered in Low-Power mode
10 = Internal LCD Reference Ladder is powered in Medium-Power mode
11 = Internal LCD Reference Ladder is powered in High-Power mode
bit 5-4
LRLBP<1:0>: LCD Reference Ladder B Time Power Control bits
During Time interval B (Refer to Figure 18-4):
00 = Internal LCD Reference Ladder is powered down and unconnected
01 = Internal LCD Reference Ladder is powered in Low-Power mode
10 = Internal LCD Reference Ladder is powered in Medium-Power mode
11 = Internal LCD Reference Ladder is powered in High-Power mode
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LRLAT<2:0>: LCD Reference Ladder A Time Interval Control bits
Sets the number of 32 kHz clocks that the A Time Interval Power mode is active
For type A waveforms (WFT = 0):
000 = Internal LCD Reference Ladder is always in ‘B’ Power mode
001 = Internal LCD Reference Ladder is in ‘A’ Power mode for 1 clock and ‘B’ Power mode for 15 clocks
010 = Internal LCD Reference Ladder is in ‘A’ Power mode for 2 clocks and ‘B’ Power mode for 14 clocks
011 = Internal LCD Reference Ladder is in ‘A’ Power mode for 3 clocks and ‘B’ Power mode for 13 clocks
100 = Internal LCD Reference Ladder is in ‘A’ Power mode for 4 clocks and ‘B’ Power mode for 12 clocks
101 = Internal LCD Reference Ladder is in ‘A’ Power mode for 5 clocks and ‘B’ Power mode for 11 clocks
110 = Internal LCD Reference Ladder is in ‘A’ Power mode for 6 clocks and ‘B’ Power mode for 10 clocks
111 = Internal LCD Reference Ladder is in ‘A’ Power mode for 7 clocks and ‘B’ Power mode for 9 clocks
For type B waveforms (WFT = 1):
000 = Internal LCD Reference Ladder is always in ‘B’ Power mode.
001 = Internal LCD Reference Ladder is in ‘A’ Power mode for 1 clock and ‘B’ Power mode for 31 clocks
010 = Internal LCD Reference Ladder is in ‘A’ Power mode for 2 clocks and ‘B’ Power mode for 30 clocks
011 = Internal LCD Reference Ladder is in ‘A’ Power mode for 3 clocks and ‘B’ Power mode for 29 clocks
100 = Internal LCD Reference Ladder is in ‘A’ Power mode for 4 clocks and ‘B’ Power mode for 28 clocks
101 = Internal LCD Reference Ladder is in ‘A’ Power mode for 5 clocks and ‘B’ Power mode for 27 clocks
110 = Internal LCD Reference Ladder is in ‘A’ Power mode for 6 clocks and ‘B’ Power mode for 26 clocks
111 = Internal LCD Reference Ladder is in ‘A’ Power mode for 7 clocks and ‘B’ Power mode for 25 clocks
DS41455A-page 156
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
18.4.4
CONTRAST CONTROL
The LCD contrast control circuit consists of a
seven-tap resistor ladder, controlled by the LCDCST
bits. Refer to Figure 18-7.
FIGURE 18-7:
The contrast control circuit is used to decrease the
output voltage of the signal source by a total of
approximately 10%, when LCDCST = 111.
Whenever the LCD module is inactive (LCDA = 0), the
contrast control ladder will be turned off (open).
INTERNAL REFERENCE AND CONTRAST CONTROL BLOCK DIAGRAM
VDDIO
7 Stages
R
R
R
R
3.072V
Analog
MUX
From FVR
Buffer
7
To top of
Reference Ladder
0
LCDCST<2:0>
3
Internal Reference
18.4.5
Contrast control
18.4.6
INTERNAL REFERENCE
Under firmware control, an internal reference for the
LCD bias voltages can be enabled. When enabled, the
source of this voltage can be either VDDIO or a voltage
one times the main fixed voltage reference (1.024V).
When no internal reference is selected, the LCD contrast control circuit is disabled and LCD bias must be
provided externally.
Whenever the LCD module is inactive (LCDA = 0), the
internal reference will be turned off.
When the internal reference is enabled and the Fixed
Voltage Reference is selected, the LCDIRI bit can be
used to minimize power consumption by tieing into the
LCD reference ladder automatic power mode switching.
When LCDIRI = 1 and the LCD reference ladder is in
Power mode ‘B’, the LCD internal FVR buffer is
disables.
Note:
VLCD<3:1> PINS
The VLCD<3:1> pins provide the ability for an external
LCD bias network to be used instead of the internal ladder. Use of the VLCD<3:1> pins does not prevent use
of the internal ladder. Each VLCD pin has an independent control in the LCDREF register (Register 18-3),
allowing access to any or all of the LCD Bias signals.
This architecture allows for maximum flexibility in different applications
For example, the VLCD<3:1> pins may be used to add
capacitors to the internal reference ladder, increasing
the drive capacity.
For applications where the internal contrast control is
insufficient, the firmware can choose to only enable the
VLCD3 pin, allowing an external contrast control circuit
to use the internal reference divider.
The LCD module automatically turns on the
fixed voltage reference when needed.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 157
PIC16LF1902/3
18.5
TABLE 18-5:
LCD Multiplex Types
The LCD driver module can be configured into one of
four multiplex types:
•
•
•
•
Multiplex
Frame Frequency(2) =
Static
Clock source(1)/(4 x (LCD Prescaler) x 32 x 1))
1/2
Clock source(1)/(2 x (LCD Prescaler) x 32 x 2))
1/3
Clock source(1)/(1 x (LCD Prescaler) x 32 x 3))
1/4
Clock source(1)/(1 x (LCD Prescaler) x 32 x 4))
Static (only COM0 is used)
1/2 multiplex (COM<1:0> are used)
1/3 multiplex (COM<2:0> are used)
1/4 multiplex (COM<3:0> are used)
The LMUX<1:0> bit setting of the LCDCON register
decides which of the LCD common pins are used (see
Table 18-4 for details).
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. If the pin is a COM drive,
then the TRIS setting of that pin is overridden.
TABLE 18-4:
LMUX
<1:0>
COM3
COM2
COM1
COM1
Static
00
Unused
Unused
Unused
Active
1/2
01
Unused
Unused
Active
Active
1/3
10
Unused
Active
Active
Active
1/4
11
Active
Active
Active
Active
18.6
Note 1:
2:
Clock source
LFINTOSC.
is
FOSC/256,
T1OSC
APPROXIMATE FRAME
FREQUENCY (IN Hz) USING
FOSC @ 8 MHz, TIMER1 @
32.768 kHz OR LFINTOSC
LP<3:0>
Static
1/2
1/3
1/4
2
122
122
162
122
3
81
81
108
81
4
61
61
81
61
5
49
49
65
49
6
41
41
54
41
7
35
35
47
35
Segment Enables
or
See Figure 18-2.
TABLE 18-6:
COMMON PIN USAGE
Multiplex
FRAME FREQUENCY
FORMULAS
The LCDSEn registers are used to select the pin
function for each segment pin. The selection allows
each pin to operate as either an LCD segment driver or
as one of the pin’s alternate functions. To configure the
pin as a segment pin, the corresponding bits in the
LCDSEn registers must be set to ‘1’.
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. Any bit set in the LCDSEn
registers overrides any bit settings in the corresponding
TRIS register.
Note:
18.7
On a Power-on Reset, these pins are
configured as normal I/O, not LCD pins.
Pixel Control
The LCDDATAx registers contain bits which define the
state of each pixel. Each bit defines one unique pixel.
Register 18-6 shows the correlation of each bit in the
LCDDATAx registers to the respective common and
segment signals.
Any LCD pixel location not being used for display can
be used as general purpose RAM.
18.8
LCD Frame Frequency
The rate at which the COM and SEG outputs change is
called the LCD frame frequency.
DS41455A-page 158
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
TABLE 18-7:
LCD
Function
LCD SEGMENT MAPPING WORKSHEET
COM0
LCDDATAx
Address
COM1
LCD
Segment
LCDDATAx
Address
COM2
LCD
Segment
LCDDATAx
Address
COM3
LCD
Segment
LCDDATAx
Address
SEG0
LCDDATA0, 0
LCDDATA3, 0
LCDDATA6, 0
LCDDATA9, 0
SEG1
LCDDATA0, 1
LCDDATA3, 1
LCDDATA6, 1
LCDDATA9, 1
SEG2
LCDDATA0, 2
LCDDATA3, 2
LCDDATA6, 2
LCDDATA9, 2
SEG3
LCDDATA0, 3
LCDDATA3, 3
LCDDATA6, 3
LCDDATA9, 3
SEG4
LCDDATA0, 4
LCDDATA3, 4
LCDDATA6, 4
LCDDATA9, 4
SEG5
LCDDATA0, 5
LCDDATA3, 5
LCDDATA6, 5
LCDDATA9, 5
SEG6
LCDDATA0, 6
LCDDATA3, 6
LCDDATA6, 6
LCDDATA9, 6
SEG7
LCDDATA0, 7
LCDDATA3, 7
LCDDATA6, 7
LCDDATA9, 7
SEG8
LCDDATA1, 0
LCDDATA4, 0
LCDDATA7, 0
LCDDATA10, 0
SEG9
LCDDATA1, 1
LCDDATA4, 1
LCDDATA7, 1
LCDDATA10, 1
SEG10
LCDDATA1, 2
LCDDATA4, 2
LCDDATA7, 2
LCDDATA10, 2
SEG11
LCDDATA1, 3
LCDDATA4, 3
LCDDATA7, 3
LCDDATA10, 3
SEG12
LCDDATA1, 4
LCDDATA4, 4
LCDDATA7, 4
LCDDATA10, 4
SEG13
LCDDATA1, 5
LCDDATA4, 5
LCDDATA7, 5
LCDDATA10, 5
SEG14
LCDDATA1, 6
LCDDATA4, 6
LCDDATA7, 6
LCDDATA10, 6
SEG15
LCDDATA1, 7
LCDDATA4, 7
LCDDATA7, 7
LCDDATA10, 7
SEG24
LCDDATA2, 5
LCDDATA5, 5
LCDDATA8, 5
LCDDATA11, 5
SEG25
LCDDATA2, 6
LCDDATA5, 6
LCDDATA8, 6
LCDDATA11, 6
SEG26
LCDDATA2, 7
LCDDATA5, 7
LCDDATA8, 7
LCDDATA11, 7
 2011 Microchip Technology Inc.
Preliminary
LCD
Segment
DS41455A-page 159
PIC16LF1902/3
18.9
LCD Waveform Generation
LCD waveforms are generated so that the net AC
voltage across the dark pixel should be maximized and
the net AC voltage across the clear pixel should be
minimized. The net DC voltage across any pixel should
be zero.
The COM signal represents the time slice for each
common, while the SEG contains the pixel data.
The pixel signal (COM-SEG) will have no DC
component and it can take only one of the two RMS
values. The higher RMS value will create a dark pixel
and a lower RMS value will create a clear pixel.
The LCDs can be driven by two types of waveform:
Type-A and Type-B. In Type-A waveform, the phase
changes within each common type, whereas in Type-B
waveform, the phase changes on each frame
boundary. Thus, Type-A waveform maintains 0 VDC
over a single frame, whereas Type-B waveform takes
two frames.
Note 1: If Sleep has to be executed with LCD
Sleep disabled (LCDCON<SLPEN> is
‘1’), then care must be taken to execute
Sleep only when VDC on all the pixels is
‘0’.
2: When the LCD clock source is FOSC/256,
if Sleep is executed, irrespective of the
LCDCON<SLPEN> setting, the LCD
immediately goes into Sleep. Thus, take
care to see that VDC on all pixels is ‘0’
when Sleep is executed.
As the number of commons increases, the delta
between the two RMS values decreases. The delta
represents the maximum contrast that the display can
have.
Figure 18-8 through Figure 18-18 provide waveforms
for static, half-multiplex, 1/3-multiplex and 1/4-multiplex
drives for Type-A and Type-B waveforms.
FIGURE 18-8:
TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE
V1
COM0 pin
V0
COM0
V1
SEG0 pin
V0
V1
SEG1 pin
V0
V1
V0
DS41455A-page 160
SEG1
SEG0
SEG2
SEG7
SEG6
SEG5
SEG4
SEG3
COM0-SEG0
segment voltage
(active)
-V1
COM0-SEG1
segment voltage
(inactive)
V0
1 Frame
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
FIGURE 18-9:
TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2
COM0 pin
COM1
V1
V0
V2
COM1 pin
COM0
V1
V0
V2
V1
SEG0 pin
V0
V2
V1
SEG1 pin
SEG1
V2
SEG0
SEG2
SEG3
V0
V1
V0
COM0-SEG0
segment voltage
(active)
-V1
-V2
V2
V1
V0
COM0-SEG1
segment voltage
(inactive)
-V1
1 Frame
-V2
1 Segment Time
Note:
1 Frame = 2 single segment times.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 161
PIC16LF1902/3
FIGURE 18-10:
TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2
COM1
V1
COM0 pin
V0
COM0
V2
COM1 pin
V1
V0
V2
SEG0 pin
V1
SEG1
SEG0
SEG3
SEG2
V0
V2
SEG1 pin
V1
V0
V2
V1
V0
COM0-SEG0
segment voltage
(active)
-V1
-V2
V2
V1
V0
COM0-SEG1
segment voltage
(inactive)
-V1
2 Frames
-V2
1 Segment Time
Note:
1 Frame = 2 single segment times.
DS41455A-page 162
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
FIGURE 18-11:
TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V3
COM1
V2
COM0 pin
V1
V0
V3
COM0
V2
COM1 pin
V1
V0
V3
V2
SEG0 pin
V1
V0
SEG1
SEG0
SEG2
SEG3
V3
V2
SEG1 pin
V1
V0
V3
V2
V1
V0
COM0-SEG0
segment voltage
(active)
-V1
-V2
-V3
V3
V2
V1
V0
COM0-SEG1
segment voltage
(inactive)
-V1
1 Frame
-V2
-V3
1 Segment Time
Note:
1 Frame = 2 single segment times.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 163
PIC16LF1902/3
FIGURE 18-12:
TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V3
COM1
V2
COM0 pin
V1
V0
V3
COM0
V2
COM1 pin
V1
V0
V3
V2
SEG0 pin
V1
V0
SEG1
SEG0
SEG2
SEG3
V3
V2
SEG1 pin
V1
V0
V3
V2
V1
V0
COM0-SEG0
segment voltage
(active)
-V1
-V2
-V3
V3
V2
V1
V0
COM0-SEG1
segment voltage
(inactive)
-V1
2 Frames
-V2
-V3
1 Segment Time
Note:
1 Frame = 2 single segment times.
DS41455A-page 164
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
FIGURE 18-13:
TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
V2
COM0 pin
V1
V0
V2
COM2
COM1 pin
V1
V0
COM1
V2
COM0
COM2 pin
V1
V0
V2
SEG0 and
SEG2 pins
V1
V0
V2
V1
V0
SEG0
SEG1
SEG2
SEG1 pin
V2
V1
V0
COM0-SEG0
segment voltage
(inactive)
-V1
-V2
V2
V1
V0
COM0-SEG1
segment voltage
(active)
-V1
-V2
1 Frame
1 Segment Time
Note:
 2011 Microchip Technology Inc.
1 Frame = 2 single segment times.
Preliminary
DS41455A-page 165
PIC16LF1902/3
FIGURE 18-14:
TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
V2
COM0 pin
V1
V0
COM2
V2
COM1 pin
V1
COM1
V0
COM0
V2
COM2 pin
V1
V0
V2
V1
V0
SEG0
SEG1
SEG2
SEG0 pin
V2
SEG1 pin
V1
V0
V2
V1
V0
COM0-SEG0
segment voltage
(inactive)
-V1
-V2
V2
V1
V0
COM0-SEG1
segment voltage
(active)
-V1
-V2
2 Frames
1 Segment Time
Note:
DS41455A-page 166
1 Frame = 2 single segment times.
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
FIGURE 18-15:
TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V3
V2
COM0 pin
V1
V0
V3
COM2
V2
COM1 pin
V1
COM1
V0
COM0
V3
V2
COM2 pin
V1
V0
V3
V2
V1
V0
SEG0
SEG1
SEG2
SEG0 and
SEG2 pins
V3
V2
SEG1 pin
V1
V0
V3
V2
V1
V0
COM0-SEG0
segment voltage
(inactive)
-V1
-V2
-V3
V3
V2
V1
V0
COM0-SEG1
segment voltage
(active)
-V1
-V2
-V3
1 Frame
1 Segment Time
Note:
 2011 Microchip Technology Inc.
1 Frame = 2 single segment times.
Preliminary
DS41455A-page 167
PIC16LF1902/3
FIGURE 18-16:
TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V3
V2
COM0 pin
V1
V0
V3
COM2
V2
COM1 pin
V1
COM1
V0
COM0
V3
V2
COM2 pin
V1
V0
V3
V2
V1
V0
SEG0
SEG1
SEG2
SEG0 pin
V3
V2
SEG1 pin
V1
V0
V3
V2
V1
V0
COM0-SEG0
segment voltage
(inactive)
-V1
-V2
-V3
V3
V2
V1
V0
COM0-SEG1
segment voltage
(active)
-V1
-V2
-V3
2 Frames
1 Segment Time
Note:
DS41455A-page 168
1 Frame = 2 single segment times.
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
FIGURE 18-17:
TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
COM3
COM2
COM1
COM0 pin
V3
V2
V1
V0
COM1 pin
V3
V2
V1
V0
COM2 pin
V3
V2
V1
V0
COM3 pin
V3
V2
V1
V0
SEG0 pin
V3
V2
V1
V0
SEG1 pin
V3
V2
V1
V0
SEG0
SEG1
COM0
V3
V2
V1
V0
-V1
-V2
-V3
COM0-SEG0
segment voltage
(active)
COM0-SEG1
segment voltage
(inactive)
1 Frame
V3
V2
V1
V0
-V1
-V2
-V3
1 Segment Time
Note:
1 Frame = 2 single segment times.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 169
PIC16LF1902/3
FIGURE 18-18:
TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
COM3
COM0 pin
V3
V2
V1
V0
COM1 pin
V3
V2
V1
V0
COM2 pin
V3
V2
V1
V0
COM3 pin
V3
V2
V1
V0
SEG0 pin
V3
V2
V1
V0
SEG1 pin
V3
V2
V1
V0
COM2
COM1
SEG0
SEG1
COM0
V3
V2
V1
V0
-V1
-V2
-V3
COM0-SEG0
segment voltage
(active)
COM0-SEG1
segment voltage
(inactive)
2 Frames
V3
V2
V1
V0
-V1
-V2
-V3
1 Segment Time
Note:
DS41455A-page 170
1 Frame = 2 single segment times.
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
18.10 LCD Interrupts
The LCD module provides an interrupt in two cases. An
interrupt when the LCD controller goes from active to
inactive controller. An interrupt also provides unframe
boundaries for Type B waveform. The LCD timing generation provides an interrupt that defines the LCD
frame timing.
18.10.1
LCD INTERRUPT ON MODULE
SHUTDOWN
An LCD interrupt is generated when the module completes shutting down (LCDA goes from ‘1’ to ‘0’).
18.10.2
LCD FRAME INTERRUPTS
A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes accessing all pixel data required for a frame. This will occur at
a fixed interval before the frame boundary (TFINT), as
shown in Figure 18-19. The LCD controller will begin to
access data for the next frame within the interval from
the interrupt to when the controller begins to access
data after the interrupt (TFWR). New data must be written within TFWR, as this is when the LCD controller will
begin to access the data for the next frame.
When the LCD driver is running with Type-B waveforms
and the LMUX<1:0> bits are not equal to ‘00’ (static
drive), there are some additional issues that must be
addressed. Since the DC voltage on the pixel takes two
frames to maintain zero volts, the pixel data must not
change between subsequent frames. If the pixel data
were allowed to change, the waveform for the odd
frames would not necessarily be the complement of the
waveform generated in the even frames and a DC
component would be introduced into the panel.
Therefore, when using Type-B waveforms, the user
must synchronize the LCD pixel updates to occur within
a subframe after the frame interrupt.
To correctly sequence writing while in Type-B, the
interrupt will only occur on complete phase intervals. If
the user attempts to write when the write is disabled,
the WERR bit of the LCDCON register is set and the
write does not occur.
Note:
The LCD frame interrupt is not generated
when the Type-A waveform is selected
and when the Type-B with no multiplex
(static) is selected.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 171
PIC16LF1902/3
FIGURE 18-19:
WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE
(EXAMPLE – TYPE-B, NON-STATIC)
LCD
Interrupt
Occurs
Controller Accesses
Next Frame Data
COM0
V3
V2
V1
V0
COM1
V3
V2
V1
V0
COM2
V3
V2
V1
V0
V3
V2
V1
V0
COM3
2 Frames
TFINT
Frame
Boundary
Frame
Boundary
TFWR
Frame
Boundary
TFWR = TFRAME/2*(LMUX<1:0> + 1) + TCY/2
TFINT = (TFWR/2 – (2 TCY + 40 ns))  minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns)
(TFWR/2 – (1 TCY + 40 ns))  maximum = 1.5(TFRAME/4) – (1 TCY + 40 ns)
DS41455A-page 172
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
18.11 Operation During Sleep
The LCD module can operate during Sleep. The
selection is controlled by bit SLPEN of the LCDCON
register. Setting the SLPEN bit allows the LCD module
to go to Sleep. Clearing the SLPEN bit allows the
module to continue to operate during Sleep.
If a SLEEP instruction is executed and SLPEN = 1, the
LCD module will cease all functions and go into a very
low-current Consumption mode. The module will stop
operation immediately and drive the minimum LCD
voltage on both segment and common lines.
Figure 18-20 shows this operation.
The LCD module can be configured to operate during
Sleep. The selection is controlled by bit SLPEN of the
LCDCON register. Clearing SLPEN and correctly configuring the LCD module clock will allow the LCD module to operate during Sleep. Setting SLPEN and
correctly executing the LCD module shutdown will disable the LCD module during Sleep and save power.
If a SLEEP instruction is executed and SLPEN = 1, the
LCD module will immediately cease all functions, drive
the outputs to Vss and go into a very low-current mode.
The SLEEP instruction should only be executed after
the LCD module has been disabled and the current
cycle completed, thus ensuring that there are no DC
voltages on the glass. To disable the LCD module,
clear the LCDEN bit. The LCD module will complete the
disabling process after the current frame, clear the
LCDA bit and optionally cause an interrupt.
The steps required to properly enter Sleep with the
LCD disabled are:
• Clear LCDEN
• Wait for LCDA = 0 either by polling or by interrupt
• Execute SLEEP
If SLPEN = 0 and SLEEP is executed while the LCD
module clock source is FOSC/4, then the LCD module
will halt with the pin driving the last LCD voltage pattern. Prolonged exposure to a fixed LCD voltage pattern will cause damage to the LCD glass. To prevent
LCD glass damage, either perform the proper LCD
module shutdown prior to Sleep, or change the LCD
module clock to allow the LCD module to continue
operation during Sleep.
If a SLEEP instruction is executed and SLPEN = 0 and
the LCD module clock is either T1OSC or LFINTOSC,
the module will continue to display the current contents
of the LCDDATA registers. While in Sleep, the LCD
data cannot be changed. If the LCDIE bit is set, the
device will wake from Sleep on the next LCD frame
boundary. The LCD module current consumption will
not decrease in this mode; however, the overall device
power consumption will be lower due to the shutdown
of the CPU and other peripherals.
 2011 Microchip Technology Inc.
Table 18-8 shows the status of the LCD module during
a Sleep while using each of the three available clock
sources.
Note:
When the LCDEN bit is cleared, the LCD
module will be disabled at the completion
of frame. At this time, the port pins will
revert to digital functionality. To minimize
power consumption due to floating digital
inputs, the LCD pins should be driven low
using the PORT and TRIS registers.
If a SLEEP instruction is executed and SLPEN = 0, the
module will continue to display the current contents of
the LCDDATA registers. To allow the module to
continue operation while in Sleep, the clock source
must be either the LFINTOSC or T1OSC external
oscillator. While in Sleep, the LCD data cannot be
changed. The LCD module current consumption will
not decrease in this mode; however, the overall
consumption of the device will be lower due to shut
down of the core and other peripheral functions.
Table 18-8 shows the status of the LCD module during
Sleep while using each of the three available clock
sources:
TABLE 18-8:
Clock Source
T1OSC
LCD MODULE STATUS
DURING SLEEP
SLPEN
Operational
During Sleep
0
Yes
1
No
LFINTOSC
0
Yes
1
No
FOSC/4
0
No
1
No
Note:
The LFINTOSC or external T1OSC
oscillator must be used to operate the
LCD module during Sleep.
If LCD interrupts are being generated (Type-B waveform with a multiplex mode not static) and LCDIE = 1,
the device will awaken from Sleep on the next frame
boundary.
Preliminary
DS41455A-page 173
PIC16LF1902/3
FIGURE 18-20:
SLEEP ENTRY/EXIT WHEN SLPEN = 1
V3
V2
V1
COM0
V0
V3
V2
V1
V0
COM1
V3
V2
V1
V0
COM2
V3
V2
V1
V0
SEG0
2 Frames
SLEEP Instruction Execution
DS41455A-page 174
Preliminary
Wake-up
 2011 Microchip Technology Inc.
PIC16LF1902/3
18.12 Configuring the LCD Module
18.14 LCD Current Consumption
The following is the sequence of steps to configure the
LCD module.
When using the LCD module the current consumption
consists of the following three factors:
1.
• Oscillator Selection
• LCD Bias Source
• Capacitance of the LCD segments
2.
3.
4.
5.
6.
7.
Select the frame clock prescale using bits
LP<3:0> of the LCDPS register.
Configure the appropriate pins to function as
segment drivers using the LCDSEn registers.
Configure the LCD module for the following
using the LCDCON register:
- Multiplex and Bias mode, bits LMUX<1:0>
- Timing source, bits CS<1:0>
- Sleep mode, bit SLPEN
Write initial values to pixel data registers,
LCDDATA0 through LCDDATA21.
Clear LCD Interrupt Flag, LCDIF bit of the PIR2
register and if desired, enable the interrupt by
setting bit LCDIE of the PIE2 register.
Configure bias voltages by setting the LCDRL,
LCDREF and the associated ANSELx
registers as needed.
Enable the LCD module by setting bit LCDEN of
the LCDCON register.
18.13 Disabling the LCD Module
To disable the LCD module, write all ‘0’s to the
LCDCON register.
 2011 Microchip Technology Inc.
The current consumption of just the LCD module can
be considered negligible compared to these other
factors.
18.14.1
OSCILLATOR SELECTION
The current consumed by the clock source selected
must be considered when using the LCD module. See
Section 21.0 “Electrical Specifications” for oscillator
current consumption information.
18.14.2
LCD BIAS SOURCE
The LCD bias source, internal or external, can contribute significantly to the current consumption. Use the
highest possible resistor values while maintaining
contrast to minimize current.
18.14.3
CAPACITANCE OF THE LCD
SEGMENTS
The LCD segments which can be modeled as capacitors which must be both charged and discharged every
frame. The size of the LCD segment and its technology
determines the segment’s capacitance.
Preliminary
DS41455A-page 175
PIC16LF1902/3
TABLE 18-9:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH LCD OPERATION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTF
IOCIF
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
LCDCON
LCDEN
SLPEN
WERR
—
CS1
CS0
LCDCST
LMUX<1:0>
66
145
—
—
—
—
—
LCDDATA0
SEG7
COM0
SEG6
COM0
SEG5
COM0
SEG4
COM0
SEG3
COM0
SEG2
COM0
SEG1
COM0
SEG0
COM0
149
LCDDATA1
SEG15
COM0
SEG14
COM0
SEG13
COM0
SEG12
COM0
SEG11
COM0
SEG10
COM0
SEG9
COM0
SEG8
COM0
149
LCDDATA3
SEG7
COM1
SEG6
COM1
SEG5
COM1
SEG4
COM1
SEG3
COM1
SEG2
COM1
SEG1
COM1
SEG0
COM1
149
LCDDATA4
SEG15
COM1
SEG14
COM1
SEG13
COM1
SEG12
COM1
SEG11
COM1
SEG10
COM1
SEG9
COM1
SEG8
COM1
149
LCDDATA6
SEG7
COM2
SEG6
COM2
SEG5
COM2
SEG4
COM2
SEG3
COM2
SEG2
COM2
SEG1
COM2
SEG0
COM2
149
LCDDATA7
SEG15
COM2
SEG14
COM2
SEG13
COM2
SEG12
COM2
SEG11
COM2
SEG10
COM2
SEG9
COM2
SEG8
COM2
149
LCDDATA9
SEG7
COM3
SEG6
COM3
SEG5
COM3
SEG4
COM3
SEG3
COM3
SEG2
COM3
SEG1
COM3
SEG0
COM3
149
LCDDATA10
SEG15
COM3
SEG14
COM3
SEG13
COM3
SEG12
COM3
SEG11
COM3
SEG10
COM3
SEG9
COM3
SEG8
COM3
149
LCDDATA12
—
—
—
—
—
SEG26
COM0
SEG25
COM0
SEG24
COM0
149
LCDDATA15
—
—
—
—
—
SEG26
COM1
SEG25
COM1
SEG24
COM1
149
LCDDATA18
—
—
—
—
—
SEG26
COM2
SEG25
COM2
SEG24
COM2
149
LCDDATA21
—
—
—
—
—
SEG26
COM3
SEG25
COM3
SEG24
COM3
149
WFT
BIASMD
LCDA
WA
LCDIRE
—
LCDIRI
—
LCDPS
LCDREF
LCDRL
LRLAP<1:0>
LRLBP<1:0>
LCDCST<2:0>
Register
on Page
148
LP<3:0>
VLCD3PE
VLCD2PE
—
146
VLCD1PE
—
LRLAT<2:0>
147
156
LCDSE0
SE<7:0>
149
LCDSE1
SE<15:8>
149
LCDSE3
—
—
—
—
—
PIE2
—
—
—
—
—
—
—
—
—
—
PIR2
T1CON
Legend:
TMR1CS1 TMR1CS0 T1CKPS1
T1CKPS0 T1OSCEN
SE<26:24>
149
LCDIE
—
—
68
LCDIF
—
—
70
T1SYNC
—
TMR1ON
139
— = unimplemented location, read as ‘0’. Shaded cells are not used by the LCD module.
DS41455A-page 176
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
19.0
Some programmers produce VPP greater than VIHH
(9.0V), an external circuit is required to limit the VPP
voltage. See Figure 19-1 for example circuit.
IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
• VSS
In Program/Verify mode the Program Memory, User
IDs and the Configuration Words are programmed
through serial communications. The ICSPDAT pin is a
bidirectional I/O used for transferring the serial data
and the ICSPCLK pin is the clock input. For more
information
on
ICSP™
refer
to
the
“PIC16F193X/LF193X/PIC16F194X/LF194X/PIC16LF
190X
Memory
Programming
Specification”
(DS41397).
19.1
High-Voltage Programming Entry
Mode
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT
pins low then raising the voltage on MCLR/VPP to VIHH.
FIGURE 19-1:
VPP LIMITER EXAMPLE CIRCUIT
RJ11-6PIN
6
5
4
3
2
1
1
VPP
2
VDD
3
VSS
4
ICSP_DATA
5
ICSP_CLOCK
6
NC
RJ11-6PIN
®
To MPLAB ICD 2
R1
To Target Board
270 Ohm
LM431BCMX
1
2 A
K
3 A U1
6 A
NC 4
7 A
NC 5
R2
VREF
8
10k 1%
Note:
R3
24k 1%
The MPLAB® ICD 2 produces a VPP
voltage greater than the maximum VPP
specification of the PIC16LF1902/3.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 177
PIC16LF1902/3
19.2
FIGURE 19-2:
Low-Voltage Programming Entry
Mode
The Low-Voltage Programming Entry mode allows the
PIC16LF1902/3 devices to be programmed using VDD
only, without high voltage. When the LVP bit of
Configuration Word 2 is set to ‘1’, the low-voltage ICSP
programming entry is enabled. To disable the
Low-Voltage ICSP mode, the LVP bit must be
programmed to ‘0’.
VDD
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1.
2.
ICD RJ-11 STYLE
CONNECTOR INTERFACE
ICSPDAT
NC
2 4 6
ICSPCLK
1 3 5
VPP/MCLR
MCLR is brought to VIL.
A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
VSS
Pin Description*
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
1 = VPP/MCLR
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 5.3 “Ultra
Low-Power Brown-out Reset (ULPBOR)” for more
information.
4 = ICSPDAT
2 = VDD Target
3 = VSS (ground)
5 = ICSPCLK
6 = No Connect
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.
19.3
Target
PC Board
Bottom Side
Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 19-3.
Common Programming Interfaces
Connection to a target device is typically done through
an ICSP™ header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6 pin, 6
connector) configuration. See Figure 19-2.
FIGURE 19-3:
PICkit™ STYLE CONNECTOR INTERFACE
Pin 1 Indicator
Pin Description*
1
2
3
4
5
6
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
*
DS41455A-page 178
The 6-pin header (0.100" spacing) accepts 0.025" square pins.
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 19-4 for more
information.
FIGURE 19-4:
TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
VPP
MCLR/VPP
VSS
VSS
Data
ICSPDAT
Clock
ICSPCLK
*
*
*
To Normal Connections
* Isolation devices (as required).
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 179
PIC16LF1902/3
NOTES:
DS41455A-page 180
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
20.0
INSTRUCTION SET SUMMARY
20.1
Read-Modify-Write Operations
• Byte Oriented
• Bit Oriented
• Literal and Control
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
The literal and control category contains the most varied instruction word format.
TABLE 20-1:
Each PIC16 instruction is a 14-bit word containing the
operation code (opcode) and all required operands.
The opcodes are broken into three broad categories.
Table 20-3 lists the instructions recognized by the
MPASMTM assembler.
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
• Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
• One additional instruction cycle will be used when
any instruction references an indirect file register
and the file select register is pointing to program
memory.
One instruction cycle consists of 4 oscillator cycles; for
an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
OPCODE FIELD
DESCRIPTIONS
Field
f
Description
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
n
FSR or INDF number. (0-1)
mm
Pre-post increment-decrement mode
selection
TABLE 20-2:
ABBREVIATION
DESCRIPTIONS
Field
Program Counter
TO
Time-out bit
C
DC
Z
PD
 2011 Microchip Technology Inc.
Description
PC
Preliminary
Carry bit
Digit carry bit
Zero bit
Power-down bit
DS41455A-page 181
PIC16LF1902/3
FIGURE 20-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
OPCODE
8
7
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11 10
OPCODE
0
k (literal)
k = 11-bit immediate value
MOVLP instruction only
13
OPCODE
7
6
0
k (literal)
k = 7-bit immediate value
MOVLB instruction only
13
OPCODE
5 4
0
k (literal)
k = 5-bit immediate value
BRA instruction only
13
OPCODE
9
8
0
k (literal)
k = 9-bit immediate value
FSR Offset instructions
13
OPCODE
7
6
n
5
0
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSR Increment instructions
13
OPCODE
3
2 1
0
n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
DS41455A-page 182
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
TABLE 20-3:
PIC16LF1902/3 ENHANCED INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
ASRF
LSLF
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BYTE ORIENTED SKIP OPERATIONS
DECFSZ
INCFSZ
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
BCF
BSF
f, b
f, b
Bit Clear f
Bit Set f
1(2)
1(2)
00
00
1, 2
1, 2
1011 dfff ffff
1111 dfff ffff
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
01
01
00bb bfff ffff
01bb bfff ffff
2
2
1, 2
1, 2
BIT-ORIENTED SKIP OPERATIONS
BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1 (2)
1 (2)
01
01
10bb bfff ffff
11bb bfff ffff
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110
1001
1000
0000
0001
0000
1100
1010
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
Subtract W from literal
Exclusive OR literal with W
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z
Z
Z
C, DC, Z
Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 183
PIC16LF1902/3
TABLE 20-3:
PIC16LF1902/3 ENHANCED INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
–
k
–
k
k
k
–
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
–
–
–
–
–
f
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
ADDFSR
MOVIW
n, k
n mm
MOVWI
k[n]
n mm
Add Literal k to FSRn
Move Indirect FSRn to W with pre/post inc/dec
modifier, mm
Move INDFn to W, Indexed Indirect.
Move W to Indirect FSRn with pre/post inc/dec
modifier, mm
Move W to INDFn, Indexed Indirect.
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
00
00
00
00
00
00
0000
0000
0000
0000
0000
0000
0110
0000
0110
0000
0110
0110
0100 TO, PD
0000
0010
0001
0011 TO, PD
0fff
INHERENT OPERATIONS
1
1
1
1
1
1
C-COMPILER OPTIMIZED
k[n]
1
1
11
00
0001 0nkk kkkk
0000 0001 0nmm Z
2, 3
1
1
11
00
1111 0nkk kkkk Z
0000 0001 1nmm
2
2, 3
1
11
1111 1nkk kkkk
2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
DS41455A-page 184
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
20.2
Instruction Descriptions
ADDFSR
Add Literal to FSRn
ANDLW
AND literal with W
Syntax:
[ label ] ADDFSR FSRn, k
Syntax:
[ label ] ANDLW
Operands:
-32  k  31
n  [ 0, 1]
Operands:
0  k  255
Operation:
(W) .AND. (k)  (W)
Operation:
FSR(n) + k  FSR(n)
Status Affected:
Z
Status Affected:
None
Description:
Description:
The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
The contents of W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W register.
AND W with f
k
FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds
will cause the FSR to wrap-around.
ADDLW
Add literal and W
ANDWF
Syntax:
[ label ] ADDLW
Syntax:
[ label ] ANDWF
Operands:
0  f  127
d 0,1
Operation:
(W) .AND. (f)  (destination)
k
Operands:
0  k  255
Operation:
(W) + k  (W)
Status Affected:
C, DC, Z
Description:
The contents of the W register are
added to the eight-bit literal ‘k’ and the
result is placed in the W register.
ADDWF
Add W and f
f,d
Status Affected:
Z
Description:
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ASRF
Arithmetic Right Shift
Syntax:
[ label ] ADDWF
Syntax:
[ label ] ASRF
Operands:
0  f  127
d 0,1
Operands:
0  f  127
d [0,1]
Operation:
(W) + (f)  (destination)
Operation:
(f<7>) dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
f,d
Status Affected:
C, DC, Z
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
ADDWFC
ADD W and CARRY bit to f
Syntax:
[ label ] ADDWFC
Operands:
0  f  127
d [0,1]
Operation:
(W) + (f) + (C)  dest
Status Affected:
C, DC, Z
Description:
Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
 2011 Microchip Technology Inc.
f {,d}
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register ‘f’.
register f
C
f {,d}
Preliminary
DS41455A-page 185
PIC16LF1902/3
BCF
Bit Clear f
Syntax:
[ label ] BCF
BTFSC
f,b
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b
0  f  127
0b7
Operands:
0  f  127
0b7
Operands:
Operation:
0  (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is cleared.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
BRA
Relative Branch
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] BRA label
[ label ] BRA $+k
Syntax:
[ label ] BTFSS f,b
Operands:
0  f  127
0b<7
Operands:
-256  label - PC + 1  255
-256  k  255
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k  PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have incremented to fetch the next instruction,
the new address will be PC + 1 + k.
This instruction is a two-cycle instruction. This branch has a limited range.
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP is
executed instead, making this a
2-cycle instruction.
BRW
Relative Branch with W
Syntax:
[ label ] BRW
Operands:
None
Operation:
(PC) + (W)  PC
Status Affected:
None
Description:
Add the contents of W (unsigned) to
the PC. Since the PC will have incremented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a two-cycle instruction.
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0  f  127
0b7
Operation:
1  (f<b>)
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is set.
DS41455A-page 186
f,b
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0  k  2047
Operands:
None
Operation:
(PC)+ 1 TOS,
k  PC<10:0>,
(PCLATH<6:3>)  PC<14:11>
Operation:
Status Affected:
None
00h  WDT
0  WDT prescaler,
1  TO
1  PD
Description:
Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The eleven-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALL is a two-cycle instruction.
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
CALLW
Subroutine Call With W
COMF
Complement f
Syntax:
[ label ] CALLW
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
(PC) +1  TOS,
(W)  PC<7:0>,
(PCLATH<6:0>) PC<14:8>
0  f  127
d  [0,1]
Operation:
(f)  (destination)
Status Affected:
Z
Description:
The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
DECF
Decrement f
Syntax:
[ label ] DECF f,d
f,d
Status Affected:
None
Description:
Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the contents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a two-cycle
instruction.
CLRF
Clear f
Syntax:
[ label ] CLRF
Operands:
0  f  127
Operands:
Operation:
00h  (f)
1Z
0  f  127
d  [0,1]
Operation:
(f) - 1  (destination)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register ‘f’ are cleared
and the Z bit is set.
Description:
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
CLRW
Clear W
Syntax:
[ label ] CLRW
f
Operands:
None
Operation:
00h  (W)
1Z
Status Affected:
Z
Description:
W register is cleared. Zero bit (Z) is
set.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 187
PIC16LF1902/3
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operands:
0  f  127
d  [0,1]
Operation:
(f) - 1  (destination);
skip if result = 0
Operation:
(f) + 1  (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a
NOP is executed instead, making it a
2-cycle instruction.
Description:
The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, a NOP is
executed instead, making it a 2-cycle
instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ]
Syntax:
[ label ]
GOTO k
INCFSZ f,d
IORLW k
Operands:
0  k  2047
Operands:
0  k  255
Operation:
k  PC<10:0>
PCLATH<6:3>  PC<14:11>
Operation:
(W) .OR. k  (W)
Status Affected:
Z
Status Affected:
None
Description:
Description:
GOTO is an unconditional branch. The
eleven-bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two-cycle instruction.
The contents of the W register are
OR’ed with the eight-bit literal ‘k’. The
result is placed in the W register.
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operands:
0  f  127
d  [0,1]
Operation:
(f) + 1  (destination)
Operation:
(W) .OR. (f)  (destination)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
Description:
Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
DS41455A-page 188
INCF f,d
Preliminary
IORWF
f,d
 2011 Microchip Technology Inc.
PIC16LF1902/3
LSLF
Logical Left Shift
MOVF
Syntax:
[ label ] LSLF
Syntax:
[ label ]
Operands:
0  f  127
d [0,1]
Operands:
0  f  127
d  [0,1]
Operation:
(f<7>)  C
(f<6:0>)  dest<7:1>
0  dest<0>
Operation:
(f)  (dest)
f {,d}
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the left through the Carry flag.
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
C
register f
0
Z
Description:
The contents of register f is moved to
a destination dependent upon the
status of d. If d = 0,
destination is W register. If d = 1, the
destination is file register f itself. d = 1
is useful to test a file register since
status flag Z is affected.
Words:
1
Cycles:
1
Logical Right Shift
Syntax:
[ label ] LSLF
Operands:
0  f  127
d [0,1]
Operation:
0  dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
 2011 Microchip Technology Inc.
MOVF
FSR, 0
After Instruction
W = value in FSR register
Z = 1
LSRF
f {,d}
register f
MOVF f,d
Status Affected:
Example:
0
Move f
C
Preliminary
DS41455A-page 189
PIC16LF1902/3
MOVIW
Move INDFn to W
MOVLP
Syntax:
[ label ] MOVIW ++FSRn
[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn]
Syntax:
[ label ] MOVLP k
Operands:
0  k  127
Operands:
n  [0,1]
mm  [00,01, 10, 11]
-32  k  31
Operation:
INDFn  W
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
• Unchanged
Status Affected:
Operation:
k  PCLATH
Status Affected:
None
Description:
The seven-bit literal ‘k’ is loaded into the
PCLATH register.
MOVLW
Move literal to W
Syntax:
[ label ]
0  k  255
Operation:
k  (W)
Status Affected:
None
Description:
The eight-bit literal ‘k’ is loaded into W
register. The “don’t cares” will assemble as ‘0’s.
Words:
1
1
Mode
Syntax
mm
Cycles:
Preincrement
++FSRn
00
Example:
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
Syntax:
[ label ] MOVLB k
Operands:
0  k  15
Operation:
k  BSR
Status Affected:
None
Description:
The five-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
DS41455A-page 190
0x5A
MOVWF
Move W to f
Syntax:
[ label ]
MOVWF
Operands:
0  f  127
Operation:
(W)  (f)
0x5A
f
Status Affected:
None
Description:
Move data from W register to register
‘f’.
Words:
1
Cycles:
1
Example:
FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to
wrap-around.
Move literal to BSR
MOVLW
After Instruction
W =
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
MOVLB
MOVLW k
Operands:
Z
Predecrement
Move literal to PCLATH
Preliminary
MOVWF
OPTION_REG
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
 2011 Microchip Technology Inc.
PIC16LF1902/3
MOVWI
Move W to INDFn
NOP
No Operation
Syntax:
[ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn]
Syntax:
[ label ]
Operands:
None
n  [0,1]
mm  [00,01, 10, 11]
-32  k  31
Description:
No operation.
Words:
1
Cycles:
1
Operands:
Operation:
Status Affected:
W  INDFn
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
Unchanged
None
Operation:
No operation
Status Affected:
None
Example:
NOP
OPTION
Load OPTION_REG Register
with W
Syntax:
[ label ] OPTION
Operands:
None
Operation:
(W)  OPTION_REG
Status Affected:
None
Description:
Move data from W register to
OPTION_REG register.
Mode
Syntax
Preincrement
++FSRn
00
Predecrement
--FSRn
01
Postincrement
FSRn++
10
Words:
1
Postdecrement
FSRn--
11
Cycles:
1
Example:
OPTION
Description:
mm
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to
wrap-around.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
 2011 Microchip Technology Inc.
NOP
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
None
Operation:
Execute a device Reset. Resets the
nRI flag of the PCON register.
Status Affected:
None
Description:
This instruction provides a way to
execute a hardware Reset by software.
Preliminary
DS41455A-page 191
PIC16LF1902/3
RETFIE
Return from Interrupt
RETURN
Return from Subroutine
Syntax:
[ label ]
Syntax:
[ label ]
None
RETFIE k
RETURN
Operands:
None
Operands:
Operation:
TOS  PC,
1  GIE
Operation:
TOS  PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Return from Interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a two-cycle
instruction.
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two-cycle instruction.
Words:
1
Cycles:
2
Example:
RETFIE
After Interrupt
PC =
GIE =
TOS
1
Return with literal in W
RLF
Rotate Left f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0  k  255
Operands:
Operation:
k  (W);
TOS  PC
0  f  127
d  [0,1]
Operation:
See description below
Status Affected:
None
Status Affected:
C
Description:
The W register is loaded with the eight
bit literal ‘k’. The program counter is
loaded from the top of the stack (the
return address). This is a two-cycle
instruction.
Description:
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words:
1
Cycles:
2
RETLW
Example:
TABLE
RETLW k
C
CALL TABLE;W contains table
;offset value
•
;W now has table value
•
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ; End of table
Before Instruction
W =
After Instruction
W =
DS41455A-page 192
RLF
Words:
1
Cycles:
1
Example:
RLF
f,d
Register f
REG1,0
Before Instruction
REG1
C
After Instruction
REG1
W
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
0x07
value of k8
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
SUBLW
Subtract W from literal
Syntax:
[ label ]
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operation:
See description below
Status Affected:
C, DC, Z
Status Affected:
C
Description:
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
The W register is subtracted (2’s complement method) from the eight-bit
literal ‘k’. The result is placed in the W
register.
RRF f,d
C
SUBLW k
Operands:
0 k 255
Operation:
k - (W) W)
Register f
C=0
Wk
C=1
Wk
DC = 0
W<3:0>  k<3:0>
DC = 1
W<3:0>  k<3:0>
SLEEP
Enter Sleep mode
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d  [0,1]
Operation:
(f) - (W) destination)
Status Affected:
C, DC, Z
Description:
Subtract (2’s complement method) W
register from register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f.
SLEEP
Operands:
None
Operation:
00h  WDT,
0  WDT prescaler,
1  TO,
0  PD
Status Affected:
TO, PD
Description:
The power-down Status bit, PD is
cleared. Time-out Status bit, TO is
set. Watchdog Timer and its prescaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
 2011 Microchip Technology Inc.
SUBWF f,d
C=0
Wf
C=1
Wf
DC = 0
W<3:0>  f<3:0>
DC = 1
W<3:0>  f<3:0>
SUBWFB
Subtract W from f with Borrow
Syntax:
SUBWFB
Operands:
0  f  127
d  [0,1]
Operation:
(f) – (W) – (B) dest
f {,d}
Status Affected:
C, DC, Z
Description:
Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Preliminary
DS41455A-page 193
PIC16LF1902/3
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR literal with W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operands:
0 k 255
(f<3:0>)  (destination<7:4>),
(f<7:4>)  (destination<3:0>)
Operation:
(W) .XOR. k W)
Status Affected:
Z
Description:
The contents of the W register are
XOR’ed with the eight-bit
literal ‘k’. The result is placed in the
W register.
Operation:
SWAPF f,d
XORLW k
Status Affected:
None
Description:
The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the
result is placed in the W register. If ‘d’
is ‘1’, the result is placed in register ‘f’.
TRIS
Load TRIS Register with W
XORWF
Exclusive OR W with f
Syntax:
[ label ] TRIS f
Syntax:
[ label ]
Operands:
5f7
Operands:
Operation:
(W)  TRIS register ‘f’
0  f  127
d  [0,1]
Status Affected:
None
Operation:
(W) .XOR. (f) destination)
Status Affected:
Z
Description:
Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in register ‘f’.
Description:
DS41455A-page 194
Move data from W register to TRIS
register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.
Preliminary
XORWF
f,d
 2011 Microchip Technology Inc.
PIC16LF1902/3
21.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)
Ambient temperature under bias....................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +4.0V
Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ............................................................................................................................... 800 mW
Maximum current out of VSS pin, -40°C  TA  +85°C for industrial............................................................... 300 mA
Maximum current out of VSS pin, -40°C  TA  +125°C for extended .............................................................. 95 mA
Maximum current into VDD pin, -40°C  TA  +85°C for industrial.................................................................. 250 mA
Maximum current into VDD pin, -40°C  TA  +125°C for extended ................................................................. 70 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA
Maximum output current sunk by any I/O pin.................................................................................................... 25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Maximum current sunk by all ports(2), -40°C  TA  +85°C for industrial ........................................................ 200 mA
Maximum current sunk by all ports(2), -40°C  TA  +125°C for extended...................................................... 120 mA
Maximum current sourced by all ports(2), 40°C  TA  +85°C for industrial ................................................... 200 mA
Maximum current sourced by all ports(2), -40°C  TA  +125°C for extended................................................. 120 mA
Note 1:
Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 195
PIC16LF1902/3
VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C
VDD (V)
FIGURE 21-1:
3.6
EC Mode
Only
2.5
Internal Oscillator
or EC Mode
2.3
2.0
1.8
0
10
4
20
16
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 21-1 for each Oscillator mode’s supported frequencies.
FIGURE 21-2:
HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
125
+ 15%
Temperature (°C)
85
60
± 10%
25
0
-20
-40
1.8
+ 15%
2.0
2.5
3.0
3.5
3.6
VDD (V)
DS41455A-page 196
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
21.1
DC Characteristics: PIC16LF1902/3-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16LF1902/3
Param.
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
Supply Voltage
D001
VDD
1.8
—
3.6
V
FOSC  16 MHz:
D002*
VDR
RAM Data Retention Voltage(1)
1.5
—
—
V
Device in Sleep mode
D002A*
VPOR*
Power-on Reset Release Voltage
—
1.6
—
V
D002B*
VPORR*
Power-on Reset Rearm Voltage
—
1.7
—
V
Device in Sleep mode
D003
VADFVR
Fixed Voltage Reference Voltage for
ADC, Initial Accuracy
6
7
7
8
—
—
—
—
4
4
6
6
%
1.024V, VDD  1.8V, 85°C
1.024V, VDD  1.8V, 125°C
2.048V, VDD  2.5V, 85°C
2.048V, VDD  2.5V, 125°C
D003A
VCDAFVR
Fixed Voltage Reference Voltage for
Comparator and DAC, Initial Accuracy
7
8
8
9
—
—
—
—
5
5
7
7
%
1.024V, VDD  1.8V, 85°C
1.024V, VDD  1.8V, 125°C
2.048V, VDD  2.5V, 85°C
2.048V, VDD  2.5V, 125°C
D003B
VLCDFVR
Fixed Voltage Reference Voltage for
LCD Bias, Initial Accuracy
9
9.5
—
—
9
9
%
3.072V, VDD  3.6V, 85°C
3.072V, VDD  3.6V, 125°C
D003C*
TCVFVR
Temperature Coefficient, Fixed Voltage Reference
—
-130
—
ppm/°C
D003D*
VFVR/
VIN
Line Regulation, Fixed Voltage Reference
—
0.270
—
%/V
D004*
SVDD
VDD Rise Rate to ensure internal
Power-on Reset signal
0.05
—
—
V/ms
See Section 5.1 “Power-on Reset
(POR)” for details.
*
These parameters are characterized but not tested.
† Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1:
This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
FIGURE 21-3:
POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
TVLOW(2)
Note 1:
2:
3:
TPOR(3)
When NPOR is low, the device is held in Reset.
TPOR 1 s typical.
TVLOW 2.7 s typical.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 197
PIC16LF1902/3
21.2
DC Characteristics: PIC16LF1902/3-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16LF1902/3
Param
No.
Conditions
Device
Characteristics
Supply Current (IDD)
LDO Regulator
Min.
Typ†
Max.
Units
VDD
Note
(1, 2)
—
350
—
A
—
EC OR INTOSC/INTOSCIO (8-16 MHZ)
—
5
—
A
—
LP Clock mode and Sleep (requires FVR and
BOR to be disabled)
—
23
38
A
1.8
—
28
43
A
3.0
FOSC = 32 kHz
LP Oscillator mode (Note 3),
-40°C  TA  +85°C
—
24
42
A
1.8
—
30
44
A
3.0
—
156
—
A
1.8
—
336
—
A
3.0
—
250
425
A
1.8
—
500
725
A
3.0
D016
—
21
35
A
1.8
—
27
40
A
3.0
D017
—
150
250
A
1.8
—
210
345
A
3.0
D018
—
0.85
1.2
mA
1.8
—
1.4
1.9
mA
3.0
D019
—
1.4
2.0
mA
1.8
—
2.2
2.8
mA
3.0
—
2.4
3.0
mA
5.0
—
350
600
A
1.8
—
550
900
A
3.0
—
620
1000
A
5.0
D009
D010
D010A
D013
D014
D020
Note 1:
2:
3:
FOSC = 32 kHz
LP Oscillator mode (Note 3)
-40°C  TA  +125°C
FOSC = 500 kHz
EC Oscillator Low-Power mode
FOSC = 4 MHz
EC Oscillator mode
Medium Power mode
FOSC = 32 kHz
LFINTOSC mode, 85°C
FOSC = 500 kHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
FOSC = 16 MHz
HFINTOSC mode
FOSC = 4 MHz
EXTRC mode
The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
FVR and BOR are disabled.
DS41455A-page 198
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
21.3
DC Characteristics: PIC16LF1902/3-I/E (Power-Down)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16LF1902
Param
No.
Device Characteristics
Power-down Base Current
D023
D024
D025
Min.
Typ†
Conditions
Max.
+85°C
Max.
+125°C
Units
VDD
—
15
35
—
A
1.8
—
18
40
—
A
3.0
—
19
45
—
A
5.0
—
16
35
—
A
1.8
—
19
40
—
A
3.0
—
20
45
—
A
5.0
—
32
50
—
A
1.8
—
39
72
—
A
3.0
—
70
120
—
A
5.0
D026
—
34
57
—
A
3.0
—
67
100
—
A
5.0
D027
—
16
35
—
A
1.8
—
21
40
—
A
3.0
—
25
45
—
A
5.0
—
16
35
—
A
1.8
—
21
40
—
A
3.0
D028
D029
D031
*
†
Legend:
Note 1:
2:
3:
Note
(IPD)(2)
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
LPWDT Current (Note 1)
FVR current
BOR Current (Note 1)
T1OSC Current (Note 1)
A/D Current (Note 1, Note 3), no
conversion in progress
—
25
50
—
A
5.0
—
280
—
—
A
1.8
—
280
—
—
A
3.0
—
280
—
—
A
5.0
—
1
—
—
A
5.0
LCD Bias Ladder, Low power
—
10
—
—
A
5.0
LCD Bias Ladder, Medium power
—
100
—
—
A
5.0
LCD Bias Ladder, High power
A/D Current (Note 1, Note 3),
conversion in progress
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
TBD = To Be Determined
The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
A/D oscillator source is FRC.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 199
PIC16LF1902/3
21.4
DC Characteristics: PIC16LF1902/3-I/E
DC CHARACTERISTICS
Param
No.
Sym.
VIL
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
Min.
Typ†
Max.
Units
Conditions
Input Low Voltage
I/O PORT:
D032
with TTL buffer
—
—
0.15 VDD
V
1.8V  VDD  3.6V
D033
with Schmitt Trigger buffer
—
—
0.2 VDD
V
1.8V  VDD  3.6V
—
—
0.2 VDD
V
0.25 VDD +
0.8
—
—
V
1.8V  VDD  3.6V
0.8 VDD
—
—
V
1.8V  VDD  3.6V
0.8 VDD
—
—
V
MCLR, OSC1
D034
VIH
Input High Voltage
I/O ports:
D040
with TTL buffer
D041
with Schmitt Trigger buffer
D042
MCLR
IIL
Input Leakage Current(2)
D060
I/O ports
—
±5
± 125
nA
±5
± 1000
nA
VSS  VPIN  VDD, Pin at highimpedance @ 85°C
125°C
D061
MCLR(3)
—
± 50
± 200
nA
VSS  VPIN  VDD @ 85°C
25
100
200
A
VDD = 3.3V, VPIN = VSS
—
0.6
V
IOL = 6mA, VDD = 3.3V
IOL = 1.8mA, VDD = 1.8V
—
—
V
IOH = 3mA, VDD = 3.3V
IOH = 1mA, VDD = 1.8V
—
50
pF
IPUR
Weak Pull-up Current
VOL
Output Low Voltage
D070*
D080
I/O ports
—
VOH
D090
Output High Voltage
I/O ports
VDD - 0.7
Capacitive Loading Specs on Output Pins
D101*
CIO
All I/O pins
—
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Negative current is defined as current sourced by the pin.
DS41455A-page 200
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
21.5
Memory Programming Requirements
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
DC CHARACTERISTICS
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
Program Memory
Programming Specifications
D110
VIHH
Voltage on MCLR/VPP/RE3 pin
8.0
—
9.0
V
D111
IDDP
Supply Current during
Programming
—
—
10
mA
VDD for Bulk Erase
2.7
—
VDD
max.
V
D112
D113
VPEW
VDD for Write or Row Erase
VDD
min.
—
VDD
max.
V
D114
IPPPGM Current on MCLR/VPP during Erase/
Write
—
—
1.0
mA
D115
IDDPGM Current on VDD during Erase/Write
—
5.0
mA
D121
EP
Cell Endurance
10K
—
—
E/W
D122
VPR
VDD for Read
VDD
min.
—
VDD
max.
V
D123
TIW
Self-timed Write Cycle Time
—
2
2.5
ms
D124
TRETD Characteristic Retention
40
—
—
Year
(Note 2, Note 3)
Program Flash Memory
-40C to +85C (Note 1)
Provided no other
specifications are violated
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Self-write and Block Erase.
2: Required only if single-supply programming is disabled.
3: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be
placed between the ICD 2 and target system when programming or debugging with the ICD 2.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 201
PIC16LF1902/3
21.6
Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
Param
No.
TH01
TH02
Sym.
Characteristic
JA
Thermal Resistance Junction to Ambient
JC
TH03
TJMAX
TH04
PD
TH05
Thermal Resistance Junction to Case
Maximum Junction Temperature
Power Dissipation
PINTERNAL Internal Power Dissipation
Typ.
Units
Conditions
60
C/W
28-pin SPDIP package
80
C/W
28-pin SOIC package
90
C/W
28-pin SSOP package
27.5
C/W
28-pin UQFN 4x4mm package
31.4
C/W
28-pin SPDIP package
24
C/W
28-pin SOIC package
24
C/W
28-pin SSOP package
24
C/W
28-pin UQFN 4x4mm package
150
C
—
W
PD = PINTERNAL + PI/O
—
W
PINTERNAL = IDD x VDD(1)
TH06
PI/O
I/O Power Dissipation
—
W
PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))
TH07
PDER
Derated Power
—
W
PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
DS41455A-page 202
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
21.7
Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O PORT
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-Impedance)
L
Low
FIGURE 21-4:
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-Impedance
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL = 50 pF for all pins, 15 pF for
OSC2 output
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 203
PIC16LF1902/3
21.8
AC Characteristics: PIC16LF1902/3-I/E
TABLE 21-1:
CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +125°C
Param
No.
OS01
Sym.
FOSC
Characteristic
External CLKIN Frequency(1)
Min.
Typ†
Max.
Units
Conditions
DC
—
0.5
MHz
EC Oscillator mode (low)
DC
—
4
MHz
EC Oscillator mode (medium)
EC Oscillator mode (high)
DC
—
32
MHz
OS02
TOSC
External CLKIN Period(1)
31.25
—

ns
EC Oscillator mode
OS03
TCY
Instruction Cycle Time(1)
200
TCY
DC
ns
TCY = 4/FOSC
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
TABLE 21-2:
OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param
No.
OS08
Sym.
HFOSC
OS08A MFOSC
OS10*
Characteristic
Internal Calibrated HFINTOSC
Frequency(2)
Internal Calibrated MFINTOSC
Frequency(2)
TIOSC ST HFINTOSC
Wake-up from Sleep Start-up Time
MFINTOSC
Wake-up from Sleep Start-up Time
Freq.
Tolerance
Min.
Typ†
Max.
Units
10%
—
16.0
—
MHz
0°C  TA  +85°C, VDD 
2.5V
15%
—
16.0
—
MHz
-40°C  TA  +125°C, VDD 
2.5V
Conditions
10%
—
500
—
kHz
0°C  TA  +85°C
15%
—
500
—
kHz
-40°C  TA  +125°C
—
—
5
8
s
—
—
20
30
s
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
DS41455A-page 204
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
FIGURE 21-5:
CLKOUT AND I/O TIMING
Cycle
Write
Fetch
Read
Execute
Q4
Q1
Q2
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS18
OS16
OS13
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
TABLE 21-3:
CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
FOSC to CLKOUT (1)
OS11
TosH2ckL
OS12
TosH2ckH FOSC to CLKOUT
(1)
(1)
OS13
TckL2ioV
CLKOUT to Port out valid
OS14
OS15
OS16
TioV2ckH
TosH2ioV
TosH2ioI
OS17
TioV2osH
OS18
TioR
Port input valid before CLKOUT(1)
FOSC (Q1 cycle) to Port out valid
FOSC (Q2 cycle) to Port input invalid
(I/O in hold time)
Port input valid to FOSC(Q2 cycle)
(I/O in setup time)
Port output rise time
OS19
TioF
Port output fall time
Min.
Typ†
Max.
Units
Conditions
—
—
70
ns
VDD = 3.3-5.0V
—
—
72
ns
VDD = 3.3-5.0V
—
—
20
ns
TOSC + 200 ns
—
50
—
50
—
—
70*
—
ns
ns
ns
20
—
—
ns
—
—
—
—
25
25
40
15
28
15
—
—
72
32
55
30
—
—
ns
OS20* Tinp
OS21* Tioc
INT pin input high or low time
Interrupt-on-change new input level
time
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in EC mode where CLKOUT output is 4 x TOSC.
 2011 Microchip Technology Inc.
Preliminary
ns
VDD = 3.3-5.0V
VDD = 3.3-5.0V
VDD = 1.8V
VDD = 3.3-5.0V
VDD = 1.8V
VDD = 3.3-5.0V
ns
ns
DS41455A-page 205
PIC16LF1902/3
FIGURE 21-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note 1: Asserted low.
FIGURE 21-7:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
2 ms delay if PWRTE = 0 and VREGEN = 1.
DS41455A-page 206
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
FIGURE 21-8:
MINIMUM PULSE WIDTH FOR ULPBOR DETECTION
VDDIO
(Monitored Voltage)
VULPBOR
VBPW < 10 nVs
Pulse Rejected
 2011 Microchip Technology Inc.
10 nVs < VBPW < 500 nVs
500 nVs < VBPW
Maybe Detected
Preliminary
DS41455A-page 207
PIC16LF1902/3
TABLE 21-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
2
5
—
—
—
—
s
s
VDD = 3.3-5V, -40°C to +85°C
VDD = 3.3-5V
10
18
27
ms
VDD = 3.3V-5V
30
TMCL
MCLR Pulse Width (low)
31
TWDTLP Low-Power Watchdog Timer
Time-out Period (No Prescaler)
32
TOST
Oscillator Start-up Timer Period(1)
—
1024
—
Tosc (Note 2)
33*
TPWRT
Power-up Timer Period, PWRTE = 0
40
65
140
ms
34*
TIOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—
—
2.0
s
35
VBOR
Brown-out Reset Voltage
2.38
1.80
2.5
1.9
2.73
2.11
V
36*
VHYST
Brown-out Reset Hysteresis
0
25
50
mV
-40°C to +85°C
37*
TBORDC Brown-out Reset DC Response
Time
1
3
5
s
VDD  VBOR
BORV=2.5V
BORV=1.9V
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no
clock) for all devices.
2: Period of the slower clock.
3: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
FIGURE 21-9:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
47
49
TMR0 or
TMR1
DS41455A-page 208
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
TABLE 21-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
40*
Sym.
TT0H
Characteristic
T0CKI High Pulse Width
Min.
No Prescaler
TT0L
T0CKI Low Pulse Width
No Prescaler
TT0P
T0CKI Period
45*
TT1H
T1CKI High Synchronous, No Prescaler
Time
Synchronous,
with Prescaler
—
—
ns
—
—
ns
0.5 TCY + 20
—
—
ns
10
—
—
ns
Greater of:
20 or TCY + 40
N
—
—
ns
0.5 TCY + 20
—
—
ns
15
—
—
ns
Asynchronous
TT1L
46*
T1CKI Low
Time
30
—
—
ns
Synchronous, No Prescaler
0.5 TCY + 20
—
—
ns
Synchronous, with Prescaler
15
—
—
ns
Asynchronous
30
—
—
ns
Greater of:
30 or TCY + 40
N
—
—
ns
47*
TT1P
T1CKI Input Synchronous
Period
48
FT1
Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
49*
TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
Asynchronous
*
†
Units
10
With Prescaler
42*
Max.
0.5 TCY + 20
With Prescaler
41*
Typ†
60
—
—
ns
32.4
32.768
33.1
kHz
2 TOSC
—
7 TOSC
—
Conditions
N = prescale value
(2, 4, ..., 256)
N = prescale value
(1, 2, 4, 8)
Timers in Sync
mode
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 209
PIC16LF1902/3
TABLE 21-6:
PIC16LF1902/3 A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
Param
Sym.
No.
Characteristic
Min.
Typ†
Max.
Units
Conditions
AD01
NR
Resolution
—
—
10
AD02
EIL
Integral Error
—
—
±1.7
AD03
EDL
Differential Error
—
—
±1
LSb No missing codes
VREF = 3.0V
AD04
EOFF Offset Error
—
—
±2
LSb VREF = 3.0V
AD05
EGN
LSb VREF = 3.0V
AD06
VREF Reference Voltage(3)
AD07
VAIN
Full-Scale Range
AD08
ZAIN
Recommended Impedance of
Analog Voltage Source
*
†
Note 1:
2:
3:
4:
Gain Error
bit
LSb VREF = 3.0V
—
—
±1.5
1.8
—
VDD
VSS
—
VREF
—
—
50
V
V
k Can go higher if external 0.01F capacitor is
present on input pin.
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Total Absolute Error includes integral, differential, offset and gain errors.
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
ADC VREF is from external VREF, VDD pin or FVREF, whichever is selected as reference input.
When ADC is off, it will not consume any current other than leakage current. The power-down current specification
includes any such leakage from the ADC module.
TABLE 21-7:
PIC16LF1902/3 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +125°C
Param
No.
Sym.
AD130* TAD
AD131
TCNV
AD132* TACQ
Characteristic
Min.
Typ†
Max.
Units
Conditions
A/D Clock Period
1.0
—
9.0
s
TOSC-based
A/D Internal RC Oscillator
Period
1.0
1.6
6.0
s
ADCS<1:0> = 11 (ADRC mode)
Conversion Time (not including
Acquisition Time)(1)
—
11
—
TAD
Set GO/DONE bit to conversion
complete.
Acquisition Time
—
5.0
—
s
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The ADRES register may be read on the following TCY cycle.
DS41455A-page 210
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
FIGURE 21-10:
PIC16LF1902/3 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
AD134
1 TCY
(TOSC/2(1))
AD131
Q4
AD130
A/D CLK
7
A/D Data
6
5
4
3
2
1
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
Sample
DONE
Sampling Stopped
AD132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
FIGURE 21-11:
PIC16LF1902/3 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134
(TOSC/2 + TCY(1))
1 TCY
AD131
Q4
AD130
A/D CLK
7
A/D Data
6
5
4
OLD_DATA
ADRES
3
2
1
0
NEW_DATA
ADIF
1 TCY
GO
DONE
Sample
AD132
Sampling Stopped
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 211
PIC16LF1902/3
NOTES:
DS41455A-page 212
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
22.0
DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
Graphs and charts are not available at this time.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 213
PIC16LF1902/3
NOTES:
DS41455A-page 214
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
23.0
DEVELOPMENT SUPPORT
23.1
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 215
PIC16LF1902/3
23.2
MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
23.3
HI-TECH C for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple
platforms.
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
23.4
23.5
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
23.6
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS41455A-page 216
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
23.7
MPLAB SIM Software Simulator
23.9
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
23.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
 2011 Microchip Technology Inc.
MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
23.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer’s PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
Preliminary
DS41455A-page 217
PIC16LF1902/3
23.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
23.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a breakpoint, the file registers can be examined and modified.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
23.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
DS41455A-page 218
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
24.0
PACKAGING INFORMATION
24.1
Package Marking Information
28-Lead PDIP
Example
PIC16LF1902-I/P
1048017
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
YYWWNNN
28-Lead SOIC (.300”)
Example
PIC16LF1902-E/SOe3
1048017
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SSOP (.209”)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC16LF1902
-E/SS e3
1048017
28-Lead UQFN (4x4x0.5 mm)
Example
XXXXX
XXXXXX
XXXXXX
YWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
PIC16
LF1903
E/MV e3
048017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 219
PIC16LF1902/3
24.2
Package Details
The following sections give the technical details of the packages.
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DS41455A-page 220
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
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 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 221
PIC16LF1902/3
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41455A-page 222
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
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 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 223
PIC16LF1902/3
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41455A-page 224
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 225
PIC16LF1902/3
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41455A-page 226
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A
Original release (01/2011)
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 227
PIC16LF1902/3
NOTES:
DS41455A-page 228
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
INDEX
A
C
A/D
C Compilers
MPLAB C18.............................................................. 216
CALL................................................................................. 187
CALLW ............................................................................. 187
Clock Sources
External Modes........................................................... 53
EC ...................................................................... 53
Internal Modes............................................................ 54
HFINTOSC ......................................................... 54
Internal Oscillator Clock Switch Timing .............. 55
LFINTOSC.......................................................... 55
Clock Switching .................................................................. 57
Code Examples
A/D Conversion ........................................................ 118
Initializing PORTA ...................................................... 93
Writing to Flash Program Memory.............................. 86
Comparators
C2OUT as T1 Gate................................................... 133
CONFIG1 Register ............................................................. 38
CONFIG2 Register ............................................................. 39
Core Function Register....................................................... 24
Customer Change Notification Service............................. 233
Customer Notification Service .......................................... 233
Customer Support............................................................. 233
Specifications............................................................ 210
Absolute Maximum Ratings .............................................. 195
AC Characteristics
Industrial and Extended (PIC16LF1902/3-I/E) .......... 204
Load Conditions ........................................................ 203
ADC .................................................................................. 113
Acquisition Requirements ......................................... 123
Associated registers.................................................. 125
Block Diagram........................................................... 113
Calculating Acquisition Time..................................... 123
Channel Selection..................................................... 114
Configuration............................................................. 114
Configuring Interrupt ................................................. 118
Conversion Clock...................................................... 114
Conversion Procedure .............................................. 118
Internal Sampling Switch (RSS) Impedance.............. 123
Interrupts................................................................... 116
Operation .................................................................. 117
Operation During Sleep ............................................ 117
Port Configuration ..................................................... 114
Reference Voltage (VREF)......................................... 114
Source Impedance.................................................... 123
Starting an A/D Conversion ...................................... 116
ADCON0 Register....................................................... 25, 119
ADCON1 Register....................................................... 25, 120
ADDFSR ........................................................................... 185
ADDWFC .......................................................................... 185
ADRESH Register............................................................... 25
ADRESH Register (ADFM = 0) ......................................... 121
ADRESH Register (ADFM = 1) ......................................... 122
ADRESL Register (ADFM = 0).......................................... 121
ADRESL Register (ADFM = 1).......................................... 122
Analog-to-Digital Converter. See ADC
ANSELA Register ............................................................... 96
ANSELB Register ............................................................... 99
Assembler
MPASM Assembler................................................... 216
D
Data Memory ................................................................ 18, 21
DC and AC Characteristics............................................... 213
DC Characteristics
Extended and Industrial............................................ 200
Industrial and Extended............................................ 197
Development Support ....................................................... 215
Device Configuration .......................................................... 37
Code Protection.......................................................... 40
Configuration Word..................................................... 37
User ID ................................................................. 40, 41
Device ID Register.............................................................. 41
Device Overview............................................................. 9, 75
B
E
Block Diagrams ................................................................. 4, 5
ADC .......................................................................... 113
ADC Transfer Function ............................................. 124
Analog Input Model ................................................... 124
Clock Source............................................................... 52
Crystal Operation ........................................................ 54
Generic I/O Port .......................................................... 93
Interrupt Logic ............................................................. 61
LCD Bias Voltage Generation................................... 151
LCD Clock Generation .............................................. 150
On-Chip Reset Circuit ................................................. 43
PIC16LF1902/3............................................. 4, 5, 10, 14
Timer0....................................................................... 127
Timer1....................................................................... 131
Timer1 Gate .............................................. 136, 137, 138
Voltage Reference .................................................... 109
BORCON Register .............................................................. 45
BRA................................................................................... 186
Brown-out Reset (BOR) ...................................................... 45
Specifications............................................................ 208
Timing and Characteristics ....................................... 206
EEDATL Register ............................................................... 89
Electrical Specifications .................................................... 195
Enhanced Mid-Range CPU ................................................ 13
Errata .................................................................................... 8
Extended Instruction Set
ADDFSR................................................................... 185
 2011 Microchip Technology Inc.
F
Firmware Instructions ....................................................... 181
Fixed Voltage Reference (FVR)
Associated Registers................................................ 110
Flash Program Memory ...................................................... 79
Associated Registers.................................................. 91
Configuration Word w/ Flash Program Memory ......... 91
Erasing ....................................................................... 82
Modifying .................................................................... 87
Write Verify ................................................................. 88
Writing ........................................................................ 83
FSR Register ...................................................................... 24
FVRCON (Fixed Voltage Reference Control) Register..... 110
Preliminary
DS41455A-page 229
PIC16LF1902/3
I
INDF Register ..................................................................... 24
Indirect Addressing ............................................................. 32
Instruction Format ............................................................. 182
Instruction Set ................................................................... 181
ADDLW ..................................................................... 185
ADDWF ..................................................................... 185
ADDWFC .................................................................. 185
ANDLW ..................................................................... 185
ANDWF ..................................................................... 185
BRA........................................................................... 186
CALL ......................................................................... 187
CALLW...................................................................... 187
LSLF ......................................................................... 189
LSRF ......................................................................... 189
MOVF........................................................................ 189
MOVIW ..................................................................... 190
MOVLB ..................................................................... 190
MOVWI ..................................................................... 191
OPTION .................................................................... 191
RESET ...................................................................... 191
SUBWFB................................................................... 193
TRIS .......................................................................... 194
BCF ........................................................................... 186
BSF ........................................................................... 186
BTFSC ...................................................................... 186
BTFSS ...................................................................... 186
CALL ......................................................................... 187
CLRF......................................................................... 187
CLRW ....................................................................... 187
CLRWDT................................................................... 187
COMF ....................................................................... 187
DECF ........................................................................ 187
DECFSZ.................................................................... 188
GOTO ....................................................................... 188
INCF.......................................................................... 188
INCFSZ ..................................................................... 188
IORLW ...................................................................... 188
IORWF ...................................................................... 188
MOVLW .................................................................... 190
MOVWF .................................................................... 190
NOP .......................................................................... 191
RETFIE ..................................................................... 192
RETLW ..................................................................... 192
RETURN ................................................................... 192
RLF ........................................................................... 192
RRF........................................................................... 193
SLEEP ...................................................................... 193
SUBLW ..................................................................... 193
SUBWF ..................................................................... 193
SWAPF ..................................................................... 194
XORLW ..................................................................... 194
XORWF..................................................................... 194
INTCON Register ................................................................ 66
Internal Oscillator Block
INTOSC
Specifications.................................................... 204
Internal Sampling Switch (RSS) Impedance ...................... 123
Internet Address................................................................ 233
Interrupt-On-Change ......................................................... 105
Associated Registers ................................................ 107
Interrupts ............................................................................. 61
ADC .......................................................................... 118
Associated registers w/ Interrupts ............................... 71
Configuration Word w/ Clock Sources ........................ 59
DS41455A-page 230
TMR1 ........................................................................ 135
INTOSC Specifications ..................................................... 204
IOCBF Register ................................................................ 106
IOCBN Register ................................................................ 106
IOCBP Register ................................................................ 106
L
LATA Register .................................................................... 95
LATB Register .................................................................... 98
LATC Register .................................................................. 101
LCD
Associated Registers ................................................ 176
Bias Voltage Generation................................... 151, 152
Clock Source Selection............................................. 150
Configuring the Module............................................. 175
Disabling the Module ................................................ 175
Frame Frequency ..................................................... 158
Interrupts .................................................................. 171
LCDCON Register .................................................... 143
LCDPS Register ....................................................... 143
Multiplex Types......................................................... 158
Operation During Sleep ............................................ 173
Pixel Control ............................................................. 158
Prescaler .................................................................. 150
Segment Enables ..................................................... 158
Waveform Generation............................................... 160
LCDCON Register .................................................... 143, 145
LCDCST Register ............................................................. 148
LCDDATAx Registers ............................................... 149, 156
LCDPS Register ....................................................... 143, 146
LP Bits ...................................................................... 150
LCDREF Register ............................................................. 147
LCDRL Register................................................................ 156
LCDSEn Registers............................................................ 149
Liquid Crystal Display (LCD) Driver .................................. 143
Load Conditions................................................................ 203
LSLF ................................................................................. 189
LSRF................................................................................. 189
M
MCLR.................................................................................. 46
Internal........................................................................ 46
Memory Organization
Data ...................................................................... 18, 21
Program ...................................................................... 15
Microchip Internet Web Site.............................................. 233
MOVIW ............................................................................. 190
MOVLB ............................................................................. 190
MOVWI ............................................................................. 191
MPLAB ASM30 Assembler, Linker, Librarian ................... 216
MPLAB Integrated Development Environment Software.. 215
MPLAB PM3 Device Programmer .................................... 218
MPLAB REAL ICE In-Circuit Emulator System ................ 217
MPLINK Object Linker/MPLIB Object Librarian ................ 216
O
OPCODE Field Descriptions............................................. 181
OPTION ............................................................................ 191
OPTION_REG Register.................................................... 129
OSCCON Register.............................................................. 58
Oscillator
Associated Registers .................................................. 59
Oscillator Module ................................................................ 51
ECH ............................................................................ 51
ECL............................................................................. 51
ECM............................................................................ 51
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
INTOSC ...................................................................... 51
Oscillator Parameters ....................................................... 204
Oscillator Specifications .................................................... 204
Oscillator Start-up Timer (OST)
Specifications............................................................ 208
OSCSTAT Register............................................................. 59
P
Packaging ......................................................................... 219
Marking ..................................................................... 219
PDIP Details.............................................................. 220
PCL and PCLATH ............................................................... 14
PCL Register....................................................................... 24
PCLATH Register ............................................................... 24
PCON Register ............................................................. 25, 49
PIE1 Register ...................................................................... 67
PIE2 Register ................................................................ 25, 68
Pinout Descriptions
PIC16LF1902/3........................................................... 11
PIR1 Register...................................................................... 69
PIR2 Register................................................................ 25, 70
PMADR Registers ............................................................... 79
PMADRH Registers ............................................................ 79
PMADRL Register............................................................... 89
PMADRL Registers ............................................................. 79
PMCON1 Register ........................................................ 79, 90
PMCON2 Register ........................................................ 79, 91
PMDATH Register .............................................................. 89
PORTA................................................................................ 94
ANSELA Register ....................................................... 94
Associated Registers .................................................. 96
Configuration Word w/ PORTA ................................... 96
PORTA Register ................................................... 25, 26
Specifications............................................................ 205
PORTA Register ................................................................. 95
PORTB................................................................................ 97
ANSELB Register ....................................................... 97
Associated Registers .................................................. 99
PORTB Register ................................................... 25, 26
PORTB Register ................................................................. 98
PORTC ............................................................................. 100
Associated Registers ................................................ 102
PORTC Register ................................................... 25, 26
Specifications............................................................ 205
PORTC Register ............................................................... 101
PORTE.............................................................................. 103
Associated Registers ................................................ 104
PORTE Register ......................................................... 25
PORTE Register ............................................................... 103
Power-Down Mode (Sleep) ................................................. 73
Associated Registers .................................................. 74
Power-on Reset .................................................................. 44
Power-up Time-out Sequence ............................................ 46
Power-up Timer (PWRT) .................................................... 44
Specifications............................................................ 208
Precision Internal Oscillator Parameters........................... 204
Program Memory ................................................................ 15
Map and Stack ................................................ 15, 17, 21
Map and Stack (PIC16LF1902) .................................. 16
Programming, Device Instructions .................................... 181
R
Reader Response ............................................................. 234
Read-Modify-Write Operations ......................................... 181
Registers
ADCON0 (ADC Control 0) ........................................ 119
 2011 Microchip Technology Inc.
ADCON1 (ADC Control 1) ........................................ 120
ADRESH (ADC Result High) with ADFM = 0) .......... 121
ADRESH (ADC Result High) with ADFM = 1) .......... 122
ADRESL (ADC Result Low) with ADFM = 0)............ 121
ADRESL (ADC Result Low) with ADFM = 1)............ 122
ANSELA (PORTA Analog Select) .............................. 96
ANSELB (PORTB Analog Select) .............................. 99
BORCON Brown-out Reset Control) .......................... 45
Configuration Word 1.................................................. 38
Configuration Word 2.................................................. 39
Core Function, Summary............................................ 24
Device ID .................................................................... 41
EEDATL (EEPROM Data) .......................................... 89
FVRCON .................................................................. 110
INTCON (Interrupt Control) ........................................ 66
IOCBF (Interrupt-on-Change Flag)........................... 106
IOCBN (Interrupt-on-Change Negative Edge).......... 106
IOCBP (Interrupt-on-Change Positive Edge)............ 106
LATA (Data Latch PORTA) ........................................ 95
LATB (Data Latch PORTB) ........................................ 98
LATC (Data Latch PORTC) ...................................... 101
LCDCON (LCD Control) ........................................... 145
LCDCST (LCD Contrast Control) ............................. 148
LCDDATAx (LCD Data) .................................... 149, 156
LCDPS (LCD Phase)................................................ 146
LCDREF (LCD Reference Voltage Control) ............. 147
LCDRL (LCD Reference Voltage Control)................ 156
LCDSEn (LCD Segment Enable) ............................. 149
OPTION_REG (OPTION)......................................... 129
OSCCON (Oscillator Control)..................................... 58
OSCSTAT (Oscillator Status) ..................................... 59
PCON (Power Control Register)................................. 49
PCON (Power Control) ............................................... 49
PIE1 (Peripheral Interrupt Enable 1) .......................... 67
PIE2 (Peripheral Interrupt Enable 2) .......................... 68
PIR1 (Peripheral Interrupt Register 1) ........................ 69
PIR2 (Peripheral Interrupt Request 2) ........................ 70
PMADRL (Program Memory Address) ....................... 89
PMCON1 (Program Memory Control 1) ..................... 90
PMCON2 (Program Memory Control 2) ..................... 91
PMDATH (Program Memory Data)............................. 89
PORTA ....................................................................... 95
PORTB ....................................................................... 98
PORTC ..................................................................... 101
PORTE ..................................................................... 103
Special Function, Summary........................................ 25
STATUS ..................................................................... 19
T1CON (Timer1 Control) .......................................... 139
T1GCON (Timer1 Gate Control)............................... 140
TRISA (Tri-State PORTA) .......................................... 95
TRISB (Tri-State PORTB) .......................................... 98
TRISC (Tri-State PORTC) ........................................ 101
TRISE (Tri-State PORTE) ........................................ 103
WDTCON (Watchdog Timer Control) ......................... 77
WPUB (Weak Pull-up PORTB)................................... 99
RESET.............................................................................. 191
Reset .................................................................................. 43
Reset Instruction................................................................. 46
Resets ................................................................................ 43
Associated Registers.................................................. 50
Revision History................................................................ 227
S
Software Simulator (MPLAB SIM) .................................... 217
Special Function Registers (SFRs)..................................... 25
Stack................................................................................... 30
Preliminary
DS41455A-page 231
PIC16LF1902/3
Accessing.................................................................... 30
Reset........................................................................... 32
Stack Overflow/Underflow................................................... 46
STATUS Register................................................................ 19
SUBWFB........................................................................... 193
T
T1CON Register.......................................................... 25, 139
T1GCON Register............................................................. 140
Temperature Indicator Module .......................................... 111
Thermal Considerations .................................................... 202
Timer0 ............................................................................... 127
Associated Registers ................................................ 129
Operation .................................................................. 127
Specifications ............................................................ 209
Timer1 ............................................................................... 131
Associated registers.................................................. 141
Asynchronous Counter Mode ................................... 133
Reading and Writing ......................................... 133
Clock Source Selection ............................................. 132
Interrupt..................................................................... 135
Operation .................................................................. 132
Operation During Sleep ............................................ 135
Oscillator ................................................................... 133
Prescaler ................................................................... 133
Specifications ............................................................ 209
Timer1 Gate
Selecting Source............................................... 133
TMR1H Register ....................................................... 131
TMR1L Register ........................................................ 131
Timers
Timer1
T1CON.............................................................. 139
T1GCON ........................................................... 140
Timing Diagrams
A/D Conversion ......................................................... 211
A/D Conversion (Sleep Mode) .................................. 211
Brown-out Reset (BOR) ............................................ 206
Brown-out Reset Situations ........................................ 45
CLKOUT and I/O....................................................... 205
INT Pin Interrupt.......................................................... 64
Internal Oscillator Switch Timing................................. 56
LCD Interrupt Timing in Quarter-Duty Cycle Drive.... 172
LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 174
Reset Start-up Sequence............................................ 47
Reset, WDT, OST and Power-up Timer ................... 206
SPI Slave Mode (CKE = 0) ....................................... 212
Timer0 and Timer1 External Clock ........................... 208
Timer1 Incrementing Edge........................................ 135
Type-A in 1/2 MUX, 1/2 Bias Drive ........................... 161
Type-A in 1/2 MUX, 1/3 Bias Drive ........................... 163
Type-A in 1/3 MUX, 1/2 Bias Drive ........................... 165
Type-A in 1/3 MUX, 1/3 Bias Drive ........................... 167
Type-A in 1/4 MUX, 1/3 Bias Drive ........................... 169
Type-A/Type-B in Static Drive................................... 160
Type-B in 1/2 MUX, 1/2 Bias Drive ........................... 162
Type-B in 1/2 MUX, 1/3 Bias Drive ........................... 164
Type-B in 1/3 MUX, 1/2 Bias Drive ........................... 166
Type-B in 1/3 MUX, 1/3 Bias Drive ........................... 168
Type-B in 1/4 MUX, 1/3 Bias Drive ........................... 170
Wake-up from Interrupt ............................................... 74
Timing Parameter Symbology........................................... 203
TMR0 Register .................................................................... 25
TMR1H Register ................................................................. 25
TMR1L Register .................................................................. 25
TRIS .................................................................................. 194
DS41455A-page 232
TRISA Register............................................................. 25, 95
TRISB ................................................................................. 97
TRISB Register............................................................. 25, 98
TRISC ............................................................................... 100
TRISC Register........................................................... 25, 101
TRISE ............................................................................... 103
TRISE Register........................................................... 25, 103
U
USART
Synchronous Master Mode
Requirements, Synchronous Transmission...... 212
V
VREF. SEE ADC Reference Voltage
W
Wake-up Using Interrupts ................................................... 74
Watchdog Timer (WDT)...................................................... 46
Modes ......................................................................... 76
Specifications ........................................................... 208
WDTCON Register ............................................................. 77
WPUB Register................................................................... 99
Write Protection .................................................................. 40
WWW Address ................................................................. 233
WWW, On-Line Support ....................................................... 8
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
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Users of Microchip products can receive assistance
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Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
 2011 Microchip Technology Inc.
Preliminary
DS41455A-page 233
PIC16LF1902/3
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: PIC16LF1902/3
Literature Number: DS41455A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41455A-page 234
Preliminary
 2011 Microchip Technology Inc.
PIC16LF1902/3
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](1)
PART NO.
Device
-
X
Tape and Reel Temperature
Option
Range
/XX
XXX
Package
Pattern
Examples:
a)
Device:
PIC16LF1902, PIC16LF1903
b)
Tape and Reel
Option:
Blank
T
= Standard packaging (tube or tray)
= Tape and Reel(1)
c)
Temperature
Range:
I
E
= -40C to +85C
= -40C to +125C
Package:
MV
P
SO
SS
=
=
=
=
Pattern:
(Industrial)
(Extended)
UQFN (4x4)
PDIP
SOIC
SSOP
Note 1:
QTP, SQTP, Code or Special Requirements
(blank otherwise)
 2011 Microchip Technology Inc.
PIC16LF1902T - I/MV 301
Tape and Reel,
Industrial temperature,
UQFN package,
QTP pattern #301
PIC16LF1903 - I/P
Industrial temperature
PDIP package
PIC16LF1903 - E/SS
Extended temperature,
SSOP package
Preliminary
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
DS41455A-page 235
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
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Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
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Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
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Tel: 81-45-471- 6166
Fax: 81-45-471-6122
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Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
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Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
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Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
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Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
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Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
08/04/10
DS41455A-page 236
Preliminary
 2011 Microchip Technology Inc.