Data Sheet

INTEGRATED CIRCUITS
GTL2000
22-bit bi-directional low voltage translator
Product data
Supersedes data of 2000 Jan 25
Philips
Semiconductors
2003 Apr 01
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
FEATURES
DESCRIPTION
• 22-bit bi-directional low voltage translator
• Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V,
The Gunning Transceiver Logic — Transceiver Voltage Clamps
(GTL-TVC) provide high-speed voltage translation with low
ON-state resistance and minimal propagation delay. The GTL2000
provides 22 NMOS pass transistors (Sn and Dn) with a common
gate (GREF) and a reference transistor (SREF and DREF). The device
allows bi-directional voltage translations between 1.0 V and 5.0 V
without use of a direction pin.
2.5 V, 3.3 V, and 5 V busses which allows direct interface with
GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
• Provides bi-directional voltage translation with no direction pin
• Low 6.5 Ω RDSON resistance between input and output pins
When the Sn or Dn port is low the clamp is in the ON-state and a
low resistance connection exists between the Sn and Dn ports.
Assuming the higher voltage is on the Dn port, when the Dn port is
high, the voltage on the Sn port is limited to the voltage set by the
reference transistor (SREF). When the Sn port is high, the Dn port is
pulled to VCC by the pull up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by
the user, without the need for directional control.
(Sn/Dn)
• Supports hot insertion
• No power supply required - Will not latch up
• 5 V tolerant inputs
• Low stand-by current
• Flow-through pinout for ease of printed circuit board trace routing
• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V
All transistors have the same electrical characteristics and there is
minimal deviation from one output to another in voltage or
propagation delay. This is a benefit over discrete transistor voltage
translation solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are identical,
SREF and DREF can be located on any of the other twenty-two
matched Sn/Dn transistors, allowing for easier board layout. The
translator’s transistors provides excellent ESD protection to lower
voltage devices and at the same time protect less ESD resistant
devices.
MM per JESD22-A115, and 1000 V per JESD22-C101
• Package offer: SSOP48, TSSOP48
APPLICATIONS
• Any application that requires bi-directional or unidirectional
voltage level translation from any voltage between 1.0 V & 5.0 V
to any voltage between 1.0 V & 5.0 V
• The open drain construction with no direction pin is ideal for
bi-directional low voltage (e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V)
processor I2C port translation to the normal 3.3 V and/or 5.0 V I2C
bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal
levels.
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP
TEMPERATURE RANGE
ORDER CODE
TOPSIDE MARK
DWG NUMBER
-40 to +85 °C
GTL2000DL
GTL2000DL
SOT370-1
48-Pin Plastic TSSOP
-40 to +85 °C
GTL2000DGG
GTL2000DGG
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2003 Apr 01
2
SOT362-1
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
PIN CONFIGURATION
GTL2000
FUNCTION TABLE
HIGH to LOW translation assuming Dn is at the higher voltage level
GND 1
48
GREF
SREF 2
47
DREF
S1 3
46
D1
S2 4
45
D2
S3 5
44
D3
S4 6
43
D4
S5 7
42
D5
S6 8
41
D6
S7 9
40
D7
S8 10
39
D8
S9 11
38
D9
S10 12
37
D10
S11 13
36
D11
S12 14
35
D12
S13 15
34
D13
S14 16
33
D14
S15 17
32
D15
S16 18
31
D16
S17 19
30
D17
S18 20
29
D18
S19 21
28
D19
S20 22
27
D20
S21 23
26
D21
S22 24
25
D22
SREF
In-Dn
Out-Sn
Transistor
H
0V
X
X
Off
H
H
VTT
H
VTT1
On
On
Off
H
H
VTT
L
L2
L
L
0 - VTT
X
X
NOTES:
1. Sn is not pulled up or pulled down.
2. Sn follows the Dn input low.
3. GREF should be at least 1.5 V higher than SREF for best
translator operation.
4. VTT is equal to the SREF voltage.
FUNCTION TABLE
LOW to HIGH translation assuming Dn is at the higher voltage level
GREF
DREF
SREF
In-Sn
Out-Dn
Transistor
H
H
0V
X
X
Off
nearly off
H
H
VTT
VTT
H1
H
H
VTT
L
L2
On
L
L
X
X
Off
0 - VTT
H = High voltage level
L = Low voltage level
X = Don’t Care
NOTES:
1. Dn is pulled up to VCC through an external resistor.
2. Dn follows the Sn input low.
3. GREF should be at least 1.5 V higher than SREF for best
translator operation.
4. VTT is equal to the SREF voltage.
CLAMP SCHEMATIC
PIN DESCRIPTION
SYMBOL
DREF
H
H = High voltage level
L = Low voltage level
X = Don’t Care
SA00521
PIN
NUMBER
GREF
DREF
GREF
D1
D22
S1
S22
NAME AND FUNCTION
1
GND
Ground (0 V)
2
SREF
Source of reference transistor
3 - 24
Sn
Port S1 to Port S22
25 - 46
Dn
Port D1 to Port D22
47
DREF
Drain of reference transistor
48
GREF
Gate of reference transistor
SREF
SA00522
2003 Apr 01
3
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
APPLICATIONS
Bi-directional translation
For the bi-directional clamping configuration, higher voltage to lower voltage or lower voltage to higher voltage, the GREF input must be
connected to DREF and both pins pulled to high side VCC through a pull-up resistor (typically 200 kΩ). A filter capacitor on DREF is
recommended. The processor output can be totem pole or open drain (pull up resistors may be required) and the chipset output can be totem
pole or open drain (pull up resistors are required to pull the Dn outputs to VCC). However, if either output is totem pole, data must be
uni-directional or the outputs must be 3-statable and the outputs must be controlled by some direction control mechanism to prevent high to low
contentions in either direction. If both outputs are open drain, no direction control is needed. The opposite side of the reference transistor (SREF)
is connected to the processor core power supply voltage. When DREF is connected through a 200 kΩ resistor to a 3.3 V to 5.5 V VCC supply
and SREF is set between1.0 V to VCC - 1.5 V, the output of each Sn has a maximum output voltage equal to SREF and the output of each Dn
has a maximum output voltage equal to VCC.
TYPICAL BI-DIRECTIONAL VOLTAGE TRANSLATION
1.8 V
5V
1.5 V
GTL2002
1.2 V
1.0 V
VCORE
CPU I/O
GND
GREF
SREF
DREF
S1
D1
S2
D2
200 KΩ
TOTEM POLE OR
OPEN DRAIN I/O
VCC
CHIPSET I/O
3.3 V
INCREASE BIT
SIZE BY USING
10 BIT GTL2010 OR
22 BIT GTL2000
VCC
S3
D3
S4
D4
S5
D5
Sn
Dn
CHIPSET I/O
SA00642
Figure 1. Bi-directional translation to multiple higher voltage levels such as an I2C bus application
2003 Apr 01
4
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
Uni-directional down translation
For uni-directional clamping, higher voltage to lower voltage, the GREF input must be connected to DREFand both pins pulled to the higher side
VCC through a pull-up resistor (typically 200 kΩ). A filter capacitor on DREF is recommended. Pull up resistors are required if the chipset I/O are
open drain. The opposite side of the reference transistor (SREF) is connected to the processor core supply voltage. When DREF is connected
through a 200 kΩ resistor to a 3.3 V to 5.5 V VCC supply and SREF is set between 1.0 V to VCC - 1.5 V, the output of each Sn has a maximum
output voltage equal to SREF.
TYPICAL UNI-DIRECTIONAL - HIGH TO LOW VOLTAGE TRANSLATION
1.8 V
5V
1.5 V
GTL2002
1.2 V
200 KΩ
1.0 V
EASY MIGRATION TO
LOWER VOLTAGE AS
PROCESSOR GEOMETRY
SHRINKS.
VCORE
CPU I/O
GND
GREF
SREF
DREF
S1
D1
S2
D2
VCC
CHIPSET I/O
TOTEM POLE I/O
SA00643
Figure 2. Uni-directional down translation, to protect low voltage processor pins
Uni-directional up translation
For uni-directional up translation, lower voltage to higher voltage, the reference transistor is connected the same as for a down translation. A
pull-up resistor is required on the higher voltage side (Dn or Sn) to get the full high level, since the GTL-TVC device will only pass the reference
source (SREF) voltage as a high when doing an up translation. The driver on the lower voltage side only needs pull-up resistors if it is open
drain.
TYPICAL UNI-DIRECTIONAL - LOW TO HIGH VOLTAGE TRANSLATION
1.8 V
5V
1.5 V
GTL2002
1.2 V
200 KΩ
1.0 V
EASY MIGRATION TO
LOWER VOLTAGE AS
PROCESSOR GEOMETRY
SHRINKS.
VCORE
CPU I/O
GND
GREF
SREF
DREF
S1
D1
S2
D2
VCC
CHIPSET I/O
TOTEM POLE I/O
OR OPEN DRAIN
SA00644
Figure 3. Uni-directional up translation, to higher voltage chip sets
2003 Apr 01
5
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
Sizing pull-up resistor
The pull-up resistor value needs to limit the current through the pass transistor when it is in the “on” state to about 15 mA. This will guarantee a
pass voltage of 260 to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage will also be higher in the “on”
state. To set the current through each pass transistor at 15 mA, the pull-up resistor value is calculated as follows:
Resistor value (W) +
Pull-u p voltage (V)*0.35 V
0.015 A
The table below summarizes resistor values for various reference voltages and currents at 15 mA and also at 10 mA and 3 mA. The resistor
value shown in the +10% column or a larger value should be used to ensure that the pass voltage of the transistor would be 350 mV or less.
The external driver must be able to sink the total current from the resistors on both sides of the GTL-TVC device at 0.175 V, although the 15 mA
only applies to current flowing through the GTL-TVC device. See Application Note AN10145-01 Bi-Directional Voltage Translators for more
information.
PULL UP RESISTOR VALUES
PULL UP RESISTOR VALUE (OHMS)
VOLTAGE
15 mA
10 mA
3 mA
NOMINAL
+ 10 %
NOMINAL
+ 10 %
NOMINAL
+ 10 %
5.0 V
310
341
465
512
1550
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
85
94
283
312
1.2 V
57
63
NOTES:
1. Calculated for VOL = 0.35 V
2. Assumes output driver VOL = 0.175 V at stated current
3. +10% to compensate for VDD range and resistor tolerance.
ABSOLUTE MAXIMUM RATINGS1, 2, 3
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
VSREF
DC source reference voltage
-0.5 to +7.0
V
VDREF
DC drain reference voltage
-0.5 to +7.0
V
VGREF
DC gate reference voltage
-0.5 to +7.0
V
VSn
DC voltage Port Sn
-0.5 to +7.0
V
VDn
DC voltage Port Dn
-0.5 to +7.0
V
IREFK
DC diode current on reference pins
VI < 0
-50
mA
ISK
DC diode current Port Sn
VI < 0
-50
mA
IDK
DC diode current Port Dn
VI < 0
-50
mA
±128
mA
-65 to +150
°C
IMAX
DC clamp current per channel
Tstg
Storage temperature range
Channel in ON-state
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2003 Apr 01
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Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
CONDITIONS
Min
Max
UNIT
VI/O
Input/output voltage (Sn, Dn)
0
5.5
V
VSREF
DC source reference voltage1
0
5.5
V
VDREF
DC drain reference voltage
0
5.5
V
VGREF
DC gate reference voltage
0
5.5
V
IPASS
Pass transistor current
—
64
mA
Tamb
Operating ambient temperature range
-40
+85
°C
In free air
NOTE:
1. VSREF ≤ VDREF - 1.5 V for best results in level shifting applications.
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE
(unless otherwise noted)
SYMBOL
PARAMETER
LIMITS
TEST CONDITIONS
MIN
TYP1
MAX
UNIT
VOL
Low level output voltage
VDD = 3.0 V; VSREF = 1.365 V; VSn or VDn = 0.175 V;
Iclamp = 15.2 mA
—
260
350
VIK
Input clamp voltage
II = -18 mA
VGREF = 0
—
—
-1.2
V
IIH
Gate input leakage
VI = 5 V
VGREF = 0
—
—
5
µA
CI(GREF)
Gate capacitance
VI = 3 V or 0
—
97.4
—
pF
CIO(OFF)
Off capacitance
VO = 3 V or 0
VGREF = 0
—
7.4
—
pF
CIO(ON)
On capacitance
VO = 3 V or 0
VGREF = 3 V
—
18.6
—
pF
VGREF = 4.5 V
—
3.5
5
—
4.4
7
—
5.5
9
—
67
105
—
9
15
—
7
10
—
58
80
—
50
70
VGREF = 3 V
VI = 0
ron2
VGREF = 2.3 V
IO = 64 mA
VGREF = 1.5 V
On-resistance
VGREF = 1.5 V
VI = 2.4 V
VI = 1.7 V
IO = 30 mA
VGREF = 4.5 V
VGREF = 3 V
VGREF = 2.3 V
IO = 15 mA
NOTES:
1. All typical values are measured at Tamb = 25 °C
2. Measured by the voltage drop between the Sn and the Dn terminals at the indicated current through the switch.
On-state resistance is determined by the lowest voltage of the two (Sn or Dn) terminals.
2003 Apr 01
7
mV
Ω
Ω
Ω
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
AC CHARACTERISTICS FOR TRANSLATOR TYPE APPLICATIONS
VREF = 1.365 to 1.635 V; VDD1 = 3.0 to 3.6 V; VDD2 = 2.36 to 2.64 V; GND = 0 V; tr = tf ≤ 3.0 ns. Refer to the Test Circuit diagram.
LIMITS
SYMBOL
PARAMETER
Tamb = -40 to +85°C
WAVEFORM
Propagation delay
Sn to Dn; Dn to Sn
tPLH2
MIN
TYP1
MAX
0.5
1.5
5.5
UNIT
ns
NOTES:
1. All typical values are measured at VDD1 = 3.3 V, VDD2 = 2.5 V, VREF = 1.5 V and Tamb = 25°C.
2. Propagation delay guaranteed by characterization.
3. CON(max) of 30 pF and a COFF(max) of 15 pF is guaranteed by design.
AC WAVEFORMS
Vm = 1.5 V; VIN = GND to 3.0 V
TEST CIRCUIT
VI
INPUT
VDD1
VM
VDD2
VDD2
VDD2
VM
150Ω
200KΩ
150Ω
150Ω
GND
tPLH
tPHL
VDD2
TEST JIG OUTPUT
HIGH-to-LOW
LOW-to-HIGH
VOL
VDD2
DUT OUTPUT
HIGH-to-LOW
LOW-to-HIGH
0
0
DUT
VM
VM
tPHL
DREF
GREF
D1
D22
S1
S22
tPLH
tPHL
tPLH
1
1
VM
VM
SREF
VOL
SA00524
Waveform 1. The Input (Sn) to Output (Dn) Propagation Delays
VREF
TEST
JIG
PULSE
GENERATOR
SA00523
Waveform 2. Load circuit
2003 Apr 01
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Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
AC CHARACTERISTICS FOR CBT TYPE APPLICATION
GND = 0 V; tR; CL = 50 pF
SYMBOL
tpd
LIMITS
-40 °C to +85°C GREF = 5 V ± 0.5 V
PARAMETER DESCRIPTION
Propagation delay1
Min
Mean
Max
—
—
250
UNITS
ps
NOTES:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
AC WAVEFORMS
TEST CIRCUIT AND WAVEFORMS
VM = 1.5 V, VIN = GND to 3.0 V
7V
3V
1.5 V
500 Ω
From Output
Under Test
S1
Open
2.5 V
GND
INPUT
500 Ω
CL = 50 pF
0V
tPLH
tPHL
Load Circuit
VOH
1.5 V
1.5 V
OUTPUT
VOL
SA00639
Waveform 1. Input (Sn) to Output (Dn) Propagation Delays
TEST
S1
tpd
open
tPLZ/tPZL
7V
tPHZ/tPZH
open
DEFINITIONS
Load capacitance includes jig and probe capacitance;
CL =
see AC CHARACTERISTICS for value.
SA00012
Waveform 2. Load circuit
2003 Apr 01
9
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
2003 Apr 01
10
GTL2000
SOT370-1
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
2003 Apr 01
11
GTL2000
SOT362-1
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
REVISION HISTORY
Rev
Date
_3
20030401
GTL2000
Description
Product data (9397 750 11347); ECN 853-2154 29441 Dated 30 January
2003. Supersedes data dated 2000 Jan 25 (9397 750 06818).
Modifications:
• New package release (TSSOP). The die was not changed.
• Added and modified specifications as data sheet was updated.
_2
2003 Apr 01
20000125
Product data (9397 750 06818); ECN 853-2153 23030 dated 2000 Jan 25.
12
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
Data sheet status
Level
Data sheet status[1]
Product
status[2] [3]
Definitions
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
 Koninklijke Philips Electronics N.V. 2003
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 04-03
For sales offices addresses send e-mail to:
[email protected].
Document order number:
Philips
Semiconductors
2003 Apr 01
13
9397 750 11347