GTL2002 2-bit bidirectional low voltage translator Rev. 07 — 2 July 2009 Product data sheet 1. General description The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2002 provides 2 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The device allows bidirectional voltage translations between 1.0 V and 5.0 V without use of a direction pin. When the Sn or Dn port is LOW the clamp is in the ON-state and a low resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by the pull-up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user, without the need for directional control. All transistors have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the transistors is symmetrical. Because all transistors in the device are identical, SREF and DREF can be located on any of the other two matched Sn/Dn transistors, allowing for easier board layout. The translator's transistors provide excellent ESD protection to lower voltage devices and at the same time protect less ESD-resistant devices. 2. Features n 2-bit bidirectional low voltage translator n Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5 V buses, which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels n Provides bidirectional voltage translation with no direction pin n Low 6.5 Ω ON-state resistance (Ron) between input and output pins (Sn/Dn) n Supports hot insertion n No power supply required; will not latch up n 5 V tolerant inputs n Low standby current n Flow-through pinout for ease of printed-circuit board trace routing n ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 n Packages offered: SO8, TSSOP8 (MSOP8), VSSOP8, XQFN8U GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 3. Applications n Any application that requires bidirectional or unidirectional voltage level translation from any voltage between 1.0 V and 5.0 V to any voltage between 1.0 V and 5.0 V n The open-drain construction with no direction pin is ideal for bidirectional low voltage (e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I2C-bus port translation to the normal 3.3 V or 5.0 V I2C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels. 4. Ordering information Table 1. Ordering information Type number Package Name Description Version GTL2002D SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 GTL2002DP TSSOP8[1] plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 GTL2002DP/Q900[2] TSSOP8[1] plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 GTL2002DC VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 GTL2002GM XQFN8U plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm SOT902-1 [1] Also known as MSOP8. [2] GTL2002DP/Q900 is AEC-Q100 compliant. Contact [email protected] for PPAP. 4.1 Ordering options Table 2. Ordering options Type number Topside mark Temperature range GTL2002D GTL2002 Tamb = −40 °C to +85 °C GTL2002DP 2002 Tamb = −40 °C to +85 °C GTL2002DP/Q900 2002 Tamb = −40 °C to +85 °C GTL2002DC 2002 Tamb = −40 °C to +85 °C GTL2002GM G2X[1] Tamb = −40 °C to +85 °C [1] ‘X’ will change based on date code. GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 2 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 5. Functional diagram DREF GREF SREF D2 D1 S2 S1 002aac784 Fig 1. Functional diagram 6. Pinning information 6.1 Pinning GTL2002DP GTL2002DP/Q900 GND 1 8 GREF SREF 2 7 DREF S1 3 6 S2 4 5 GND 1 8 GREF SREF 2 7 DREF D1 S1 3 6 D1 D2 S2 4 5 D2 GTL2002D 002aac778 002aac777 Fig 3. Pin configuration for TSSOP8 (MSOP8) GREF Pin configuration for SO8 terminal 1 index area GND 1 8 Fig 2. 7 DREF GTL2002GM 8 GREF 2 7 DREF S2 3 6 D1 GND 4 5 D2 GTL2002DC Pin configuration for VSSOP8 GTL2002_7 Product data sheet D1 S1 3 5 D2 002aac780 Transparent top view 002aac779 Fig 4. 6 4 1 S1 2 S2 SREF SREF Fig 5. Pin configuration for XQFN8U © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 3 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 6.2 Pin description Table 3. Symbol Pin description Pin Description SO8, TSSOP8, VSSOP8 XQFN8U GND 1 4 ground (0 V) SREF 2 1 source of reference transistor S1 3 2 port S1 S2 4 3 port S2 D2 5 5 port D2 D1 6 6 port D1 DREF 7 7 drain of reference transistor GREF 8 8 gate of reference transistor 7. Functional description Refer to Figure 1 “Functional diagram”. 7.1 Function selection Table 4. Function selection, HIGH to LOW translation Assuming Dn is at the higher voltage level. H = HIGH voltage level; L = LOW voltage level; X = Don’t care. GREF[1] DREF SREF Input Dn Output Sn Transistor H H 0V X X off H H VTT [4] [4] H H VTT L L 0 V − VTT[4] [2][4] H VTT L L[3] on X X off [1] GREF should be at least 1.5 V higher than SREF for best translator operation. [2] Sn is not pulled up or pulled down. [3] Sn follows the Dn input LOW. [4] VTT is equal to the SREF voltage. on Table 5. Function selection, LOW to HIGH translation Assuming Dn is at the higher voltage level. H = HIGH voltage level; L = LOW voltage level; X = Don’t care. GREF[1] DREF SREF Input Sn Output Dn Transistor H H 0V X X off H H VTT[4] VTT[4] H[2] nearly off H VTT [4] L L[3] on L 0 V − VTT X X off H L [4] [1] GREF should be at least 1.5 V higher than SREF for best translator operation. [2] Dn is pulled up to VCC through an external resistor. [3] Dn follows the Sn input LOW. [4] VTT is equal to the SREF voltage. GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 4 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 8. Application design-in information 8.1 Bidirectional translation For the bidirectional clamping configuration, higher voltage to lower voltage or lower voltage to higher voltage, the GREF input must be connected to DREF and both pins pulled to HIGH side VCC through a pull-up resistor (typically 200 kΩ). A filter capacitor on DREF is recommended. The processor output can be totem pole or open-drain (pull-up resistors may be required) and the chip set output can be totem pole or open-drain (pull-up resistors are required to pull the Dn outputs to VCC). However, if either output is totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs must be controlled by some direction control mechanism to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no direction control is needed. The opposite side of the reference transistor (SREF) is connected to the processor core power supply voltage. When DREF is connected through a 200 kΩ resistor to a 3.3 V to 5.5 V VCC supply and SREF is set between 1.0 V to (VCC − 1.5 V), the output of each Sn has a maximum output voltage equal to SREF and the output of each Dn has a maximum output voltage equal to VCC. 1.8 V 1.5 V 1.2 V 1.0 V 5V 200 kΩ totem pole or open-drain I/O VCORE GND GREF SREF DREF S1 D1 S2 D2 CPU I/O VCC CHIPSET I/O increase bit size by using 10-bit GTL2010 or 22-bit GTL2000 3.3 V VCC S3 D3 S4 D4 S5 D5 Sn Dn CHIPSET I/O 002aac060 Typical bidirectional voltage translation. Fig 6. Bidirectional translation to multiple higher voltage levels such as an I2C-bus application GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 5 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 8.2 Unidirectional down translation For unidirectional clamping, higher voltage to lower voltage, the GREF input must be connected to DREF and both pins pulled to the higher side VCC through a pull-up resistor (typically 200 kΩ). A filter capacitor on DREF is recommended. Pull-up resistors are required if the chip set I/O are open-drain. The opposite side of the reference transistor (SREF) is connected to the processor core supply voltage. When DREF is connected through a 200 kΩ resistor to a 3.3 V to 5.5 V VCC supply and SREF is set between 1.0 V to (VCC − 1.5 V), the output of each Sn has a maximum output voltage equal to SREF. 1.8 V 1.5 V 1.2 V 1.0 V 5V 200 kΩ easy migration to lower voltage as processor geometry shrinks VCORE GND GREF SREF DREF S1 D1 S2 D2 CPU I/O VCC CHIPSET I/O totem pole I/O 002aac061 Typical unidirectional HIGH-to-LOW voltage translation. Fig 7. Unidirectional down translation to protect low voltage processor pins 8.3 Unidirectional up translation For unidirectional up translation, lower voltage to higher voltage, the reference transistor is connected the same as for a down translation. A pull-up resistor is required on the higher voltage side (Dn or Sn) to get the full HIGH level, since the GTL-TVC device will only pass the reference source (SREF) voltage as a HIGH when doing an up translation. The driver on the lower voltage side only needs pull-up resistors if it is open-drain. 1.8 V 1.5 V 1.2 V 1.0 V 5V 200 kΩ easy migration to lower voltage as processor geometry shrinks VCORE GND GREF SREF DREF S1 D1 S2 D2 CPU I/O VCC CHIPSET I/O totem pole I/O or open-drain 002aac062 Typical unidirectional LOW-to-HIGH voltage translation. Fig 8. Unidirectional up translation to higher voltage chip sets GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 6 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 8.4 Sizing pull-up resistor The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about 15 mA. This will guarantee a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage will also be higher in the ON state. To set the current through each pass transistor at 15 mA, the pull-up resistor value is calculated as shown in Equation 1: pull-up voltage ( V ) – 0.35 V resistor value ( Ω ) = ---------------------------------------------------------------------------0.015 A (1) Table 6 summarizes resistor values for various reference voltages and currents at 15 mA and also at 10 mA and 3 mA. The resistor value shown in the +10 % column or a larger value should be used to ensure that the pass voltage of the transistor would be 350 mV or less. The external driver must be able to sink the total current from the resistors on both sides of the GTL-TVC device at 0.175 V, although the 15 mA only applies to current flowing through the GTL-TVC device. See application note AN10145, “Bidirectional low voltage translators” for more information. Table 6. Pull-up resistor values Pull-up resistor value (Ω)[1] 15 mA[2] Voltage Nominal + 10 10 mA[2] %[3] Nominal Nominal + 10 %[3] 5.0 V 310 341 465 512 1550 1705 3.3 V 197 217 295 325 983 1082 2.5 V 143 158 215 237 717 788 1.8 V 97 106 145 160 483 532 1.5 V 77 85 115 127 383 422 1.2 V 57 63 85 94 283 312 [1] Calculated for VOL = 0.35 V. [2] Assumes output driver VOL = 0.175 V at stated current. [3] + 10 % to compensate for VDD range and resistor tolerance. GTL2002_7 Product data sheet + 10 3 mA[2] %[3] © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 7 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 9. Limiting values Table 7. Limiting values[1] In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Min Max Unit voltage on pin SREF [2] −0.5 +7.0 V VDREF voltage on pin DREF [2] −0.5 +7.0 V VGREF voltage on pin GREF [2] −0.5 +7.0 V voltage on port Sn [2] −0.5 +7.0 V VDn voltage on port Dn [2] −0.5 +7.0 V IREFK diode current on reference pins VI < 0 V - −50 mA ISK diode current port Sn VI < 0 V - −50 mA IDK diode current port Dn VI < 0 V - −50 mA Imax clamp current per channel channel in ON state - ±128 mA Tstg storage temperature −65 +150 °C VSREF VSn Parameter Conditions [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperature which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. [2] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 10. Recommended operating conditions Table 8. Recommended operating conditions Symbol Parameter Conditions VI/O voltage on an input/output pin Sn, Dn [1] Max Unit 0 5.5 V VSREF voltage on pin SREF 0 5.5 V VDREF voltage on pin DREF 0 5.5 V VGREF voltage on pin GREF 0 5.5 V IPASS pass transistor current - 64 mA Tamb ambient temperature −40 +85 °C [1] operating in free air VSREF ≤ VDREF − 1.5 V for best results in level shifting applications. GTL2002_7 Product data sheet Min © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 8 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 11. Static characteristics Table 9. Static characteristics Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VOL LOW-level output voltage VDD = 3.0 V; VSREF = 1.365 V; VSn or VDn = 0.175 V; Iclamp = 15.2 mA - 260 350 mV VIK input clamping voltage II = −18 mA; VGREF = 0 V - - −1.2 V ILI(gate) gate input leakage current VI = 5 V; VGREF = 0 V - - 5 µA Cig input capacitance at gate pin GREF; VI = 3 V or 0 V - 19.4 - pF Cio(off) off-state input/output capacitance VO = 3 V or 0 V; VGREF = 0 V [2] - 7.4 - pF VO = 3 V or 0 V; VGREF = 3 V [2] - 18.6 - pF VI = 0 V; IO = 64 mA [3] Cio(on) on-state input/output capacitance ON-state resistance Ron VGREF = 4.5 V - 3.5 5 Ω VGREF = 3 V - 4.4 7 Ω VGREF = 2.3 V - 5.5 9 Ω - 67 105 Ω VI = 0 V; IO = 30 mA; VGREF = 1.5 V [3] - 9 15 Ω VI = 2.4 V; IO = 15 mA; VGREF = 4.5 V [3] - 7 10 Ω VI = 2.4 V; IO = 15 mA; VGREF = 3 V [3] - 58 80 Ω VI = 1.7 V; IO = 15 mA; VGREF = 2.3 V [3] - 50 70 Ω VGREF = 1.5 V [1] All typical values are measured at Tamb = 25 °C. [2] Cio(on) maximum of 30 pF and Cio(off) maximum of 15 pF is guaranteed by design. [3] Measured by the voltage drop between the Sn and the Dn terminals at the indicated current through the switch. ON-state resistance is determined by the lowest voltage of the two (Sn or Dn) terminals. GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 9 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 12. Dynamic characteristics 12.1 Dynamic characteristics for translator-type application Table 10. Dynamic characteristics for translator-type application Tamb = −40 °C to +85 °C; Vref = 1.365 V to 1.635 V; VDD1 = 3.0 V to 3.6 V; VDD2 = 2.36 V to 2.64 V; GND = 0 V; tr = tf ≤ 3.0 ns. Refer to Figure 11. Symbol Parameter Conditions tPLH LOW to HIGH propagation delay Sn to Dn; Dn to Sn tPHL HIGH to LOW propagation delay Sn to Dn; Dn to Sn Min Typ[1] Max Unit [2] 0.5 1.5 5.5 ns [2] 0.5 1.5 5.5 ns [1] All typical values are measured at VDD1 = 3.3 V, VDD2 = 2.5 V; Vref = 1.5 V and Tamb = 25 °C. [2] Propagation delay guaranteed by characterization. VI input VM VM GND test jig output HIGH-to-LOW, LOW-to-HIGH tPHL0 tPLH0 VM VM VDD2 tPHL tPHL1 DUT output HIGH-to-LOW, LOW-to-HIGH tPLH tPLH1 VM VOL VDD2 VM VOL 002aac789 VM = 1.5 V; VI = GND to 3.0 V. Fig 9. The input (Sn) to output (Dn) propagation delays GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 10 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 12.2 Dynamic characteristics for CBT-type application Table 11. Dynamic characteristics for CBT-type application Tamb = −40 °C to +85 °C; VGREF = 5 V ± 0.5 V; GND = 0 V; tr = tf ≤ 3.0 ns; CL = 50 pF. Symbol tPD [1] Parameter Conditions [1] propagation delay Min Typ Max Unit - - 250 ps This parameter is warranted by the ON-state resistance at GREF = 4.5 V, but is not directly production tested. The propagation delay is based on the RC time constant of the typical ON-state resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance). 3.0 V input 1.5 V 1.5 V tPLH tPHL 0V VOH output 1.5 V 1.5 V VOL 002aab664 tPD = the maximum of tPLH or tPHL. VM = 1.5 V; VI = GND to 3.0 V. Fig 10. Input (Sn) to output (Dn) propagation delays GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 11 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 13. Test information VDD1 VDD2 200 kΩ DREF VDD2 150 kΩ GREF VDD2 150 kΩ 150 kΩ D1 D2 DUT SREF S1 S2 test jig Vref pulse generator 002aac790 Fig 11. Load circuit for translator-type applications RL from output under test 500 Ω CL 50 pF S1 7V open GND RL 500 Ω 002aab667 Test data are given in Table 12. CL = load capacitance; includes jig and probe capacitance. RL = load resistance. Fig 12. Load circuit for CBT-type application Table 12. Test tPD Test data Load CL RL 50 pF 500 Ω GTL2002_7 Product data sheet Switch open © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 12 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 14. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 13. Package outline SOT96-1 (SO8) GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 13 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm D E SOT505-1 A X c y HE v M A Z 5 8 A2 pin 1 index (A3) A1 A θ Lp L 1 4 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.94 0.7 0.4 0.1 0.1 0.1 0.70 0.35 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 SOT505-1 Fig 14. Package outline SOT505-1 (TSSOP8) GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 14 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 Fig 15. Package outline SOT765-1 (VSSOP8) GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 15 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm B D SOT902-1 A terminal 1 index area E A A1 detail X L1 e e C ∅v M C A B ∅w M C L 4 y1 C y 5 3 metal area not for soldering e1 b 2 6 e1 7 1 terminal 1 index area 8 X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 v w y y1 mm 0.5 0.05 0.00 0.25 0.15 1.65 1.55 1.65 1.55 0.55 0.5 0.35 0.25 0.15 0.05 0.1 0.05 0.05 0.05 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT902-1 --- MO-255 --- EUROPEAN PROJECTION ISSUE DATE 05-11-25 07-11-14 Fig 16. Package outline SOT902-1 (XQFN8U) GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 16 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 17 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 17) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 13 and 14 Table 13. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 14. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 17. GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 18 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 17. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Abbreviations Table 15. Abbreviations Acronym Description CBT Cross Bar Technology CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor CPU Central Processing Unit ESD ElectroStatic Discharge GTL Gunning Transceiver Logic HBM Human Body Model I/O Input/Output I2C-bus Inter-Integrated Circuit bus LVTTL Low Voltage Transistor-Transistor Logic MM Machine Model NMOS Negative-channel Metal-Oxide Semiconductor RC Resistor Capacitor network TTL Transistor-Transistor Logic TVC Transceiver Voltage Clamps GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 19 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 17. Revision history Table 16. Revision history Document ID Release date Data sheet status Change notice Supersedes GTL2002_7 20090702 Product data sheet - GTL2002_6 Modifications: • • • • • Table 1 “Ordering information”: added type number GTL2002DP/Q900 Table 2 “Ordering options”: added type number GTL2002DP/Q900 Figure 3 “Pin configuration for TSSOP8 (MSOP8)”: added type number GTL2002DP/Q900 Table 8 “Recommended operating conditions”: deleted (empty) Typ column updated soldering information GTL2002_6 20071221 Product data sheet - GTL2002_5 GTL2002_5 20070813 Product data sheet - GTL2002_4 GTL2002_4 20060829 Product data sheet - GTL2002_3 GTL2002_3 (9397 750 13058) 20040929 Product data sheet - GTL2002_2 GTL2002_2 (9397 750 11349) 20030401 Product data ECN 853-2214 29603 dated 2003 Feb 28 GTL2002_1 GTL2002_1 (9397 750 07417) 20000216 Product specification ECN 853-2214 24367 dated 2000 Aug 16 - GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 20 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] GTL2002_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 2 July 2009 21 of 22 GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 20. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 8 8.1 8.2 8.3 8.4 9 10 11 12 12.1 12.2 13 14 15 15.1 15.2 15.3 15.4 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Function selection. . . . . . . . . . . . . . . . . . . . . . . 4 Application design-in information . . . . . . . . . . 5 Bidirectional translation. . . . . . . . . . . . . . . . . . . 5 Unidirectional down translation. . . . . . . . . . . . . 6 Unidirectional up translation . . . . . . . . . . . . . . . 6 Sizing pull-up resistor . . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Dynamic characteristics for translator-type application. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Dynamic characteristics for CBT-type application. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Soldering of SMD packages . . . . . . . . . . . . . . 17 Introduction to soldering . . . . . . . . . . . . . . . . . 17 Wave and reflow soldering . . . . . . . . . . . . . . . 17 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 2 July 2009 Document identifier: GTL2002_7