REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV 18 PAGE 19 REV STATUS OF PAGES 20 REV 1 PAGE PMIC N/A PREPARED BY RICK OFFICER Original date of drawing YY MM DD CHECKED BY TOM HESS 03-03-20 2 3 4 A REV 6 7 8 9 10 11 12 13 14 15 16 17 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO TITLE MICROCIRCUIT, DIGITAL-LINEAR, 3.3 V DUAL UNIVERSAL ASYNCHRONOUS RECEIVER / TRANSMITTER WITH 64 BYTE FIFO, MONOLITHIC SILICON APPROVED BY RAYMOND MONNIN SIZE 5 CODE IDENT. NO. DWG NO. V62/03626 16236 PAGE AMSC N/A DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 1 OF 20 5962-V026-03 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 3.3 V dual universal asynchronous receiver / transmitter with 64-byte FIFO microcircuit, with an operating temperature range of -40°C to +110°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03626 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 TL16C752B-EP Circuit function 3.3 V dual universal asynchronous receiver / transmitter with 64-byte FIFO 1.2.2 Case outline(s). The case outlines shall be as specified herein. Outline letter Number of pins X 48 JEDEC PUB 95 Package style MS-026 Plastic quad flat pack 1.2.3 Lead finishes. The lead finishes shall be as specified below or other lead finishes as provided by the device manufacture: Finish designator A B C D E Z DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 2 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) ......................................................................................... -0.5 V to 3.6 V Input voltage range (VI) ................................................................................................ -0.5 V to VCC + 0.5 V Output voltage range (VO) ............................................................................................ -0.5 V to VCC + 0.5 V Storage temperature range (TSTG) .............................................................................. -65°C to +150°C 1.4 Recommended operating conditions. 2/ Supply voltage range (VCC) .......................................................................................... 2.7 V to 3.6 V Input voltage range (VI) ................................................................................................. 0 V to VCC High level input voltage (VIH) ....................................................................................... 0.7 VCC to VCC 3/ Low level input voltage (VIL) ......................................................................................... 0.3 VCC 3/ Output voltage (VO)....................................................................................................... 0 V to VCC 4/ High level output current (VOH) : with IOH = -8 mA ....................................................................................................... VCC – 0.8 V minimum 5/ with IOH = -4 mA ....................................................................................................... VCC – 0.8 V minimum 6/ Low level output current (VOL) : with IOH = -8 mA ....................................................................................................... 0.5 V maximum 5/ with IOH = 4 mA ......................................................................................................... 0.5 V maximum 6/ Input capacitance (CI) .................................................................................................. 18 pF maximum Virtual junction temperature range (TJ) ........................................................................ Oscillator / clock speed ................................................................................................ Clock duty cycle ........................................................................................................... Supply current (ICC) : 9/ with 36 MHz, 3.6 V .................................................................................................... with 5 MHz, 3.6 V ...................................................................................................... with sleep mode, 3.6 V .............................................................................................. Operating free-air temperature range (TA) .................................................................... 1/ 2/ 3/ 4/ 5/ 6/ 7/ 8/ 9/ +25°C to +125°C 7/ 48 MHz 8/ 50 % nominal 20 mA nominal 6 mA nominal 1.2 mA nominal -40°C to +110°C Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “ recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Meets TTL levels, VIO(min) = 2 V and VIH(max) = 0.8 V on nonhysteresis inputs. Applies for external output buffers. These parameters apply for D7 D0. These parameters apply for DTRA , DTRB , INIA , INTB, RTSA , RTSB , RXRDYA , RXRDYB , TXRDYA , TXRDYB , TXA, TXB. These junction temperatures reflect simulated condition. Absolute maximum junction temperature is +150°C. The customer is responsible for verifying junction temperature. The internal oscillator cell can only support up to 24 MHz clock frequency to make the crystal oscillating when crystal is used. If external oscillator or other on board clock source is used, the device can work for input clock frequency up to 48 MHz. Measurement condition: a) Normal operation other than sleep mode: VCC = 3.3 V, TA = 25°C. Full duplex serial activity on all serial (UART) channels at the clock frequency specified in the recommended operating conditions with divisor of one. b) Sleep mode: VCC = 3.3 V, TA = 25°C. After enabling the sleep mode for all four channels, all serial and host activity is kept idle. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 3 2. APPLICABLE DOCUMENTS JEDEC PUB 95 – Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industry Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or at http://www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as shown in figure 3. 3.5.4 Timing waveforms. The timing waveforms shall be as shown in figure 4. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 4 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ Device type Temperature, TA Limits Min -40°C to +110°C 01 Unit Max 0 ns 2 input clock periods ns IOR delay from chip select td1 Read cycle delay td2 Delay from IOR to data td3 28.5 ns Data disable time td4 15 ns IOW delay from chip select td5 10 ns Write cycle delay td6 2 input clock periods ns Delay from IOW to output td7 100 pF load 50 ns Delay to set interrupt from MODEM input td8 100 pF load 70 ns Delay to reset td9 100 pF load 70 ns 1RCLK Baud rate 70 ns 100 ns 24 Baud rate interrupt from IOR Delay from stop to set interrupt td10 Delay from IOR to reset interrupt td11 Delay from stop to interrupt td12 Delay from initial INT reset to transmit start td13 Delay from IOW to reset interrupt td14 70 ns Delay from stop to td15 1 Clock 100 pF load 8 set RXRDY See footnote at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 5 TABLE I. Electrical performance characteristics – continued. Test Symbol Conditions 1/ Device type Temperature, TA Limits Min Delay from IOR to Unit Max 1 µs td17 70 ns td18 16 Baud rate td19 4 input clock periods Baud rate -40°C to +110°C td16 01 reset RXRDY Delay from IOW to set TXRDY Delay from start to reset TXRDY Delay between successive assertion of IOW and IOR Chip select hold th1 0 ns th2 0 ns Data hold time th3 15 ns Address hold time th4 0 ns Hold time from XTAL1 th5 20 ns Clock cycle period tp1, tp2 20 ns Oscillator / clock speed tp3 Reset pulse width t(RESET) Address setup time Data setup time time from IOR Chip select hold time from IOW clock ↓ IOW or IOR release 48 VCC = 3 V MHz 200 ns tsu1 0 ns tsu2 16 ns See footnote at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 6 TABLE I. Electrical performance characteristics – continued. Test Symbol Conditions 1/ Temperature, TA Device type Limits Min Setup time from IOW -40°C to +110°C tsu3 01 Unit Max 20 ns or IOR assertion to XTAL1 clock ↑ IOR strobe width tw1 2 input clock period ns IOR strobe width tw2 2 input clock period ns 1/ VCC = 3.3 V ±10 % unless otherwise specified. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 7 Case X FIGURE 1. Case outline. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 8 Case X Dimensions Symbol Millimeters Min Max A 1.60 A1 1.35 1.45 A2 0.25 --- A3 0.05 --- b 0.17 0.27 C 0.13 nominal D 8.80 9.20 D1 6.80 7.20 D2 5.50 typical E 8.80 9.20 E1 6.80 7.20 E2 5.50 typical e 0.50 --- L1 0.45 0.75 NOTES: 1. The package thermal performance may be enhanced by bonding the thermal pad to an thermal plate. This pad is electrically and thermally connected to the backside of the die and possible selected leads. 2. Body dimensions do not include mold flash or protrusion. FIGURE 1. Case outline – Continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 9 Device types Case outline Terminal number 1 2 3 4 5 6 All X Terminal symbol D5 D6 D7 RXB RXA Device types Case outline Terminal number 25 26 27 28 29 30 All X Terminal symbol NC A2 A1 A0 INTB INTA 31 RXRDYA 7 TXRDYB TXA 8 TXB 32 OPA 9 OPB 33 RTSA 10 CSA 34 DTRA 11 CSB 35 DTRB 12 13 14 NC XTAL1 XTAL2 36 37 38 RESET NC 15 IOW 39 DSRA 16 CDB 40 CDA 17 GND 41 RIA RXRDYB 42 VCC TXRDYA 18 19 CTSA IOR 43 20 DSRB 44 D0 21 RIB 45 D1 22 RTSB 46 D2 23 CTSB 47 D3 24 NC 48 D4 NC = No internal connection FIGURE 2. Terminal connections. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 10 Terminal I/O A0 I Address 0 select bit. Internal registers address selection. A1 I Address 1 select bit. Internal registers address selection. A2 I Address 2 select bit. Internal registers address selection. CDA , CDB I CSA , CSB I Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected in the modem status register (MSR). Chip select A and B (active low). These pins enable data transfers between the user CPU and the device for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a low on the CTSA , CTSB I D0 – D7 I/O DSRA , DSRB I DTRA , DTRB O GND Pwr INTA, INTB O Description respective CSA and CSB pins. Clear to send (active low). These inputs are associated with individual UART channels A and B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit data from the device. Status can be tested by reading MSR bit 4. These pins only affect the transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation. Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information to or from the controlling CPU. Do is the least significant bit and the first data bit in a transmit or receive serial data stream. Data set ready (active low). These inputs are associated with individual UART channels A and B. A logic low on these pins indicates the modem or data set is powered on and is ready for data exchange with UART. The state of these inputs is reflected in the modem status register (MSR). Data terminal ready (active low). These outputs are associated with individual UART channels A and B. A logic low on these pins indicates that the device is powered on and ready. These pins can be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low, enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset. Signal and power ground. Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B. INT A and B are enabled when MCR bit 3 is set to a logic 1, interrupt sources are enabled in the interrupt enable register (IER). Interrupt conditions include: receiver errors, available receiver buffer data, available transmit buffer space or when a modem states flag is detected. INTA-B are in the high-impedance state after reset. FIGURE 2. Terminal connections – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 11 Terminal I/O Description IOR I Read input (active low strobe). A high to low transition on IOR loads the contents of an internal register defined by address bits A0-A2 onto the device data bus (D0-D7) for access by an external CPU. IOW I Write input (active low strobe). A low to high transition on IOW transfers the contents of the data bus (D0-D7) from the external CPU to an internal register OPA , OPB O that is defined be address bits A0-A2 and CSA and CSB . User defined outputs. This function is associated with individual channels A and B. The state of these pins is defined by the user through the software settings of the MCR register, bit 3. INTA-B are set to active mode and OP to a logic 0 when the MCR-3 is set to logic 1. INTA-B are set to the 3-state RESET I RIA , RIB I RTSA , RTSB O mode and OP to a logic 1 when the MCR-3 is set to a logic 0. See bit 3, modem control register (MCR bit 3). The output of these two pins is high after reset. Reset. RESET resets the internal registers and all the outputs. The UART transmitter output and the receiver input is disabled during reset time. See device external reset conditions for initialization details. RESET is an active high input. Ring indicator (active low). These inputs are associated with individual UART channels A and B. A logic low on these pins indicates the modem has received a ringing signal from the telephone line. A low to high transition on these input pins generates a modem status interrupt, if enabled. The state of these inputs is reflected in the modem status register (MSR). Request to send (active low). These outputs are associated with individual UART channels A and B. A low on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is available. After a reset, these pins are set to high. These pins only affect the transmit and receive RXA, RXB I RXRDYA , O RXRDYB operation when auto RTS function is enabled through the enhanced feature register (EFR) bit 6, for hardware flow control operation. Receive data input. These inputs are associated with individual serial channel data to the device. During the local loop back mode, these RX input pins are disabled and TX data is internally connected to the UART RX input internally. Receive ready (active low). RXRDY A and B goes low when the trigger level has been reached or a timeout interrupt occurs. They go high when the RX FIFO is empty or there is an error in RX FIFO. FIGURE 2. Terminal connections – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 12 Terminal I/O TXA, TXB O Transmit data. These outputs are associated with individual serial transmit channel data from the device. During the local loopback mode, the TX input pin is disabled and TX data is internally connected to the UART RX input. TXRDYA , O Transmit ready (active low). TXRDY A and B go low when there are at least a trigger level number of spaces available. They go high when the TX buffer is full. Power supply inputs. TXRDYB VCC XTAL 1 I XTAL 2 O I Description Crystal or external clock input. XTAL 1 functions as a crystal input or as an external clock input. A crystal can be connected between XTAL 1 and XTAL 2 to form an internal oscillator circuit. Alternatively, an external clock can be connected to XTAL 1 to provide custom data rates. Output of the crystal oscillator or buffered clock. See also XTAL 1. XTAL 2 is used as a crystal oscillator output or buffered a clock output. FIGURE 2. Terminal connections – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 13 FIGURE 3. Block diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 14 FIGURE 4. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 15 FIGURE 4. Timing waveforms – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 16 FIGURE 4. Timing waveforms – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 17 FIGURE 4. Timing waveforms – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 18 FIGURE 4. Timing waveforms – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 19 4.0 QUALITY ASSURANCE PROVISIONS 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5.0 PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6.0 NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/03626-01XE 01295 TL16C752BTPTREP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 01295 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE CODE IDENT NO. DWG NO. A 16236 V62/03626 REV PAGE 20