ICL7106 / ICL7107 ICL7106 / ICL7107 3½ Digit LCD/LED Display A/D Converter PRODUCT DESCRIPTION The ICL7106 and ICL7107 are high performance, low power, 3½ digit A/D converters. Included are seven segment decoders, display drivers, a reference, and a clock. The ICL7106 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed backplane drive; the ICL7107 will directly drive an instrument size light emitting diode (LED) display. The ICL7106 and ICL7107 bring together a combination of high accuracy, versatility, and true economy. True differential inputs and reference are useful in all systems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge type transducers. Finally, the true economy of single power supply operation (ICL7106), enables a high performance panel meter to be built with the addition of only 10 passive components and a display. Display-hold, low-battery flag, integration and de-integration status flags are four additional features which are available in the 44-pin package. APPLICATIONS FEATURES These devices can be used in a wide range of digital panel meter applications. Most applications, however, involve the measurement and display of analog data: Pressure Conductance Voltage Current Resistance Speed Temperature Material Thickness Guaranteed Zero Reading for 0V Input on All Scales True Polarity at Zero for Precise Null Detection True Differential Input and Reference, Direct Display Drive -LCD ICL7106 -LED lCL7107 Low Noise - Less Than 15 µVP-P On Chip Clock and Reference Low Power Dissipation - Typically Less Than 10mW No Additional Active Circuits Required New Small Outline Surface Mount Package Available Four additional features are available for 44 pin PQFP package: – Display – Hold – Low - Battery indication – Integration Status indication – De-integration Status Indication Ordering Information PART NO. ICL7106CPL ICL7106CM44 ICL7106CX ICL7107CPL ICL7107CM44 ICL7107CX TEMP. RANGE (°C) 0 – 70 °C 0 – 70 °C 0 – 70 °C 0 – 70 °C 0 – 70 °C 0 – 70 °C PACKAGE 40 Ld. PDIP 44 Ld. PQFP Dice 40 Ld. PDIP 44 Ld. PQFP Dice 1 ICL7106 / ICL7107 ABSOLUTE MAXIMUM RATINGS THERMAL INFORMATION Supply Voltage ICL7106, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . 15V ICL7107, V+ to GND . . . . . . . . . . . . . . . . . . . . . . . 6V ICL7107, V- to GND . . . . . . . . . . . . . . . . . . . . . . . .-9V Analog Input Voltage (Either Input) (Note 1) . . . . . V+ to VReference Input Voltage (Either Input). . . . . . . . . . V+ to VClock Input ICL7106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEST to V+ ICL7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND to V+ Thermal Resistance (Typical, Note 2) șJA (°C/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . .50 MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . .75 Maximum Junction Temperature . . . . . . . . . . . .150°C Maximum Storage Temperature Range . . .-65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . .300°C (MQFP - Lead Tips Only) ELECTRICAL SPECIFICATIONS (Note 3) PARAMETERS SYSTEM PERFORMANCE TEST CONDITIONS Zero Input Reading VIN = 0.0V, Full Scale = 200mV Ratiometric Reading VlN = VREF, VREF = 100mV Rollover Error Linearity Common Mode Rejection Ratio End Power Supply Character V+ Supply Current End Power Supply Character V- Supply Current -VIN = +VlN 200mV Difference in Reading for Equal Positive and Negative Inputs Near Full Scale Full Scale = 200mV or Full Scale = 2V Maximum Deviation from Best Straight Line Fit (Note 5) VCM = 1V, VIN = 0V, Full Scale = 200mV (Note 5) VIN = 0 (Does Not Include LED Current for ICL7107) ICL7107 Only 25 kȍ Between Common and Positive Supply (With Respect to + Supply) DISPLAY DRIVER ICL7106 ONLY Pk-Pk Segment Drive Voltage V+ = to V- = 9V (Note 4) Pk-Pk Backplane Drive Voltage DISPLAY DRIVER ICL7107 ONLY Segment Sinking Current Except Pins 19 and 20 V+ = 5V, Segment Voltage = 3V Pin 19 Only Pin 20 Only COMMON Pin Analog Common Voltage MIN TYP MAX UNIT -000.0 r000.0 +000.0 999 999/1000 1000 -1 - +1 Counts -1 - +1 Counts - 50 - µV/V - - 1.8 mA - - 1.8 mA 2.4 - 3.2 V 4 5 6 V 5 8 - mA 10 4 16 7 - mA mA Digital Reading Digital Reading NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to r100µA. 2. șJA is measured with the component mounted on a low effective thermal conductivity test board in free air. 3. Unless otherwise noted, specifications apply to both the ICL7106 and ICL7107 at TA = 25°C, fCLOCK = 48kHz. ICL7106 is tested in the circuit of Figure 1. ICL7107 is tested in the circuit of Figure 2. 4. Back plane drive is in phase with segment drive for “off ” segment, 180 degrees out of phase for “on “ segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 5. Not tested, guaranteed by design. 2 ICL7106 / ICL7107 PINOUTS ICL7106,ICL7107 (PDIP) TOP VIEW V+ 1 40 OSC 1 D1 2 39 OSC 2 C1 3 38 OSC 3 B1 4 37 TEST A1 5 36 REF HI F1 6 35 REF LO G1 7 34 CREF+ E1 8 33 CREF- D2 9 32 COMMON C2 10 31 IN HI B2 11 30 IN LO A2 12 29 A-Z F2 13 28 BUFF E2 14 27 INT D3 15 26 V- B3 16 25 G2 (10’s) F3 17 24 C3 E3 18 23 A3 (1000) AB4 19 22 G3 POL 20 21 BP/GND (1’s) (10’s) (100’s) (MINUS) (100’s) ICL7106, ICL7107 (PQFP) V- INT BUFF A-Z IN LO COMMON IN HI CREF- CREF+ REF LO REF HI TOP VIEW 44 43 42 41 40 39 38 37 36 35 34 33 2 32 LB* TEST 3 31 C3 OSC 3 4 30 A3 HOLD* 5 29 G3 OSC 2 6 28 BP/GND OSC 1 7 27 POL V+ 8 26 AB4 D1 9 25 E3 C1 10 24 F3 B1 11 23 12 13 14 15 16 17 18 19 20 21 22 B3 DEEN* INTEN* 1 A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 3 G2 ICL7106 / ICL7107 Typical Applications and Test Circuits IN A3 23 G3 22 BP 21 19 AB4 20 POL C3 24 18 E3 17 F3 V- 26 G2 25 16 B3 INT 27 DISPLAY 15 D3 14 E2 A-Z 29 BUFF 28 C3 13 F2 IN HI 31 C2 R2 IN LO 30 COM 32 CREF- 33 CREF+ 34 REF LO 35 TEST 37 C5 C1 R4 REF HI 36 OSC 3 38 OSC 2 39 OSC 1 40 C4 + R5 R1 R3 9V - - + 12 A2 11 B2 D2 9 10 C2 E1 8 5 F1 A1 4 G1 B1 3 7 C1 2 6 V+ D1 1 ICL7106 C1 = 0.1µF C2 = 0.47µF C3 = 0.22µF C4 = 100pF C5 = 0.02µF R1 = 24kΩ R2 = 47kΩ R3 = 100kΩ R4 = 1kΩ R5 = 1MΩ DISPLAY FIGURE 1. ICL7106 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE +5V + IN C3 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 GND 21 15 D3 16 B3 17 F3 18 E3 19 AB4 20 POL DISPLAY 14 E2 A-Z 29 BUFF 28 C2 R2 IN LO 30 COM 32 CREF- 33 CREF+ 34 REF LO 35 IN HI 31 C5 C1 R4 REF HI 36 TEST 37 OSC 3 38 OSC 2 39 OSC 1 40 C4 -5V R5 R1 R3 - 13 F2 12 A2 11 B2 D2 9 10 C2 E1 8 A1 5 F1 B1 4 G1 C1 3 7 D1 2 6 V+ 1 ICL7107 C1 = 0.1µF C2 = 0.47µF C3 = 0.22µF C4 = 100pF C5 = 0.02µF R1 = 24kΩ R2 = 47kΩ R3 = 100kΩ R4 = 1kΩ R5 = 1MΩ DISPLAY FIGURE 2. ICL7107 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE 4 ICL7106 / ICL7107 Design Information Summary Sheet • DISPLAY COUNT • OSCILLATOR FREQUENCY V IN COUNT = 1000 × --------------V REF fOSC = 0.45/RC COSC > 50pF; ROSC > 50kΩ fOSC (Typ) = 48kHz • CONVERSION CYCLE • OSCILLATOR PERIOD tCYC = tCL0CK x 4000 tCYC = tOSC x 16,000 when fOSC = 48kHz; tCYC = 333ms tOSC = RC/0.45 • INTEGRATION CLOCK FREQUENCY • COMMON MODE INPUT VOLTAGE fCLOCK = fOSC/4 (V- + 1V) < VlN < (V+ - 0.5V) • INTEGRATION PERIOD • AUTO-ZERO CAPACITOR tINT = 1000 x (4/fOSC) 0.01µF < CAZ < 1µF • 60/50Hz REJECTION CRITERION • REFERENCE CAPACITOR tINT/t60Hz or tlNT/t60Hz = Integer 0.1µF < CREF < 1µF • OPTIMUM INTEGRATION CURRENT • VCOM Biased between Vi and V-. IINT = 4µA • VCOM ≅ V+ - 2.8V • FULL SCALE ANALOG INPUT VOLTAGE Regulation lost when V+ to V- < ≅6.8V If VCOM is externally pulled down to (V+ to V-)/2, the VCOM circuit will turn off. VlNFS (Typ) = 200mV or 2V • INTEGRATE RESISTOR V INFS R INT = ----------------I INT • ICL7106 POWER SUPPLY: SINGLE 9V V+ - V- = 9V Digital supply is generated internally VGND ≅ V+ - 4.5V • INTEGRATE CAPACITOR ( t INT ) ( I INT ) C INT = -------------------------------V INT • ICL7106 DISPLAY: LCD Type: Direct drive with digital logic supply amplitude. • INTEGRATOR OUTPUT VOLTAGE SWING • ICL7107 POWER SUPPLY: DUAL ±5.0V ( t INT ) ( I INT ) V INT = -------------------------------C INT V+ = +5V to GND V- = -5V to GND Digital Logic and LED driver supply V+ to GND • VINT MAXIMUM SWING: • ICL7107 DISPLAY: LED (V- + 0.5V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V Type: Non-Multiplexed Common Anode Typical Integrator Amplifier Output Waveform (INT Pin) AUTO ZERO PHASE (COUNTS) 2999 - 1000 SIGNAL INTEGRATE PHASE FIXED 1000 COUNTS DE-INTEGRATE PHASE 0 - 1999 COUNTS TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC 5 ICL7106 / ICL7107 Detailed Description output to return to zero is proportional to the input signal. Specifically the digital reading displayed is: Analog Section V IN DISPLAY COUNT = 1000 --------------- . V REF Figure 3 shows the Analog Section for the ICL7106 and ICL7107. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE). Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the AZ accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10µV. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection.) De-Integrate Phase The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the STRAY STRAY CREF CREF+ REF HI 34 36 V+ RINT REF LO 35 CREF - CAZ BUFFER V+ 33 28 1 CINT A-Z INT 29 27 INTEGRATOR A-Z A-Z - - 10µA + + 31 - + 2.8V IN HI INT DE- DE+ 6.2V INPUT HIGH A-Z A-Z DE+ 32 COMPARATOR - N + DE- COMMON INT 30 INPUT LOW A-Z AND DE(±) IN LO V- FIGURE 3. ANALOG SECTION OF ICL7106 AND ICL7107 6 TO DIGITAL SECTION ICL7106 / ICL7107 Analog COMMON V+ This pin is included primarily to set the common mode voltage for battery operation (ICL7106) or for any system where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (>7V), the COMMON voltage will have a low voltage coefficient (0.001%/V), low output impedance (≅15Ω), and a temperature coefficient typically less than 80ppm/oC. V REF HI 6.8V ZENER REF LO IZ ICL7106 ICL7107 V- FIGURE 4A. The limitations of the on chip reference should also be recognized, however. With the ICL7107, the internal heating which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastic parts are poorer in this respect than ceramic. The combination of reference Temperature Coefficient (TC), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25µV to 80µVP-P. Also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a low dissipation count such as 1111(8 segments on) can suffer by a count or more. Devices with a positive TC reference may require several counts to pull out of an over-range condition. This is because over-range is a low dissipation mode, with the three least significant digits blanked. Similarly, units with a negative TC may cycle between over-range and a non-overrange count as the die alternately heats and cools. All these problems are of course eliminated if an external reference is used. V+ V 6.8kΩ 20kΩ ICL7106 ICL7107 ICL8069 1.2V REFERENCE REF HI REF LO COMMON FIGURE 4B. FIGURE 4. USING AN EXTERNAL REFERENCE TEST The TEST pin serves two functions. On the ICL7106 it is coupled to the internally generated digital supply through a 500Ω resistor. Thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the LCD display. Figures 5 and 6 show such an application. No more than a 1mA load should be applied. The ICL7106, with its negligible dissipation, suffers from none of these problems. In either case, an external reference can easily be added, as shown in Figure 4. Analog COMMON is also used as the input low return during auto-zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it should be since this removes the common mode voltage from the reference system. V+ 1MΩ TO LCD DECIMAL POINT ICL7106 BP TEST 21 37 TO LCD BACKPLANE FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT The second function is a “lamp test”. When TEST is pulled high (to V+) all segments will be turned on and the display should read “1888”. The TEST pin will sink about 15mA under these conditions. Within the lC, analog COMMON is tied to an N-Channel FET that can sink approximately 30mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is only 10µA of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference. CAUTION: In the lamp test mode, the segments have a constant DC voltage (no square-wave). This may burn the LCD display if maintained for extended periods. 7 ICL7106 / ICL7107 absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/sec., this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. V+ V+ BP ICL7106 TO LCD DECIMAL POINTS DECIMAL POINT SELECT Figure 8 is the Digital Section of the ICL7107. It is identical to the ICL7106 except that the regulated supply and back plane drive have been eliminated and the segment drive has been increased from 2mA to 8mA, typical for instrument size common anode LED displays. Since the 1000 output (pin 19) must sink current from two LED segments, it has twice the drive capability or 16mA. TEST CD4030 GND FIGURE 6. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE Digital Section In both devices, the polarity indication is “on” for negative analog inputs. If IN LO and IN HI are reversed, this indication can be reversed also, if desired. Figures 7 and 8 show the digital section for the ICL7106 and ICL7107, respectively. In the ICL7106, an internal digital ground is generated from a 6V Zener diode and a large P-Channel source follower. This supply is made stiff to a a f a g b e a f b b f g c e c d b g c d e c d BACKPLANE 21 LCD PHASE DRIVER 7 SEGMENT DECODE TYPICAL SEGMENT OUTPUT V+ 7 SEGMENT DECODE 7 SEGMENT DECODE ÷200 0.5mA LATCH SEGMENT OUTPUT 2mA 1000’s COUNTER 100’s COUNTER 10’s COUNTER 1’s COUNTER INTERNAL DIGITAL GROUND TO SWITCH DRIVERS FROM COMPARATOR OUTPUT 1 V+ CLOCK ÷4 † LOGIC CONTROL 6.2V 500Ω † THREE INVERTERS INTERNAL DIGITAL GROUND ONE INVERTER SHOWN FOR CLARITY TEST VTH = 1V 37 26 40 OSC 1 39 OSC 2 38 OSC 3 FIGURE 7. ICL7106 DIGITAL SECTION 8 V- ICL7106 / ICL7107 a a a f g b f b e a f b g c e c d e c d 7 SEGMENT DECODE TYPICAL SEGMENT OUTPUT V+ b g c d 7 SEGMENT DECODE 7 SEGMENT DECODE LATCH 0.5mA TO SEGMENT 1000’s COUNTER 100’s COUNTER 10’s COUNTER 1’s COUNTER 8mA TO SWITCH DRIVERS FROM COMPARATOR OUTPUT DIGITAL GROUND V+ 1 V+ CLOCK ÷4 † 37 LOGIC CONTROL 500Ω † THREE INVERTERS 27 ONE INVERTER SHOWN FOR CLARITY 40 OSC 1 39 OSC 2 TEST DIGITAL GROUND 38 OSC 3 FIGURE 8. ICL7107 DIGITAL SECTION System Timing INTERNAL TO PART Figure 9 shows the clocking arrangement used in the ICL7106 and ICL7107. Two basic clocking arrangements can be used: ÷4 CLOCK ÷4 CLOCK 1. Figure 9A. An external oscillator connected to pin 40. 2. Figure 9B. An R-C oscillator using all three pins. 40 The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto-zero (1000 to 3000 counts). For signals less than full scale, auto-zero gets the unused portion of reference de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used. 39 38 GND ICL7107 TEST ICL7106 FIGURE 9A. INTERNAL TO PART To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 331/3kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 662/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz). 40 39 38 R C RC OSCILLATOR FIGURE 9B. FIGURE 9. CLOCK CIRCUITS 9 ICL7106 / ICL7107 Component Value Selection Reference Voltage The analog input required to generate full scale output (2000 counts) is: VlN = 2VREF. Thus, for the 200mV and 2V scale, VREF should equal 100mV and 1V, respectively. However, in many applications where the A/D is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the transducer is 0.662V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly and select VREF = 0.341V. Suitable values for integrating resistor and capacitor would be 120kΩ and 0.22µF. This makes the system slightly quieter and also avoids a divider network on the input. The ICL7107 with ±5V supplies can accept input signals up to ±4V. Another advantage of this system occurs when a digital reading of zero is desired for VIN ≠ 0. Temperature and weighing systems with a variable fare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset voltage between COMMON and IN LO. Integrating Resistor Both the buffer amplifier and the integrator have a class A output stage with 100µA of quiescent current. They can supply 4µA of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full scale, 470kΩ is near optimum and similarly a 47kΩ for a 200mV scale. Integrating Capacitor The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing (approximately. 0.3V from either supply). In the ICL7106 or the ICL7107, when the analog COMMON is used as a reference, a nominal +2V fullscale integrator swing is fine. For the ICL7107 with +5V supplies and analog COMMON tied to supply ground, a ±3.5V to +4V swing is nominal. For three readings/second (48kHz clock) nominal values for ClNT are 0.22µF and 0.10µF, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. ICL7107 Power Supplies The ICL7107 is designed to work from ±5V supplies. However, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors, and an inexpensive lC. Figure 10 shows this application. See ICL7660 data sheet for an alternative. An additional requirement of the integrating capacitor is that it must have a low dielectric absorption to prevent roll-over errors. While other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. In fact, in selected applications no negative supply is required. The conditions to use a single +5V supply are: Auto-Zero Capacitor The size of the auto-zero capacitor has some influence on the noise of the system. For 200mV full scale where noise is very important, a 0.47µF capacitor is recommended. On the 2V scale, a 0.047µF capacitor increases the speed of recovery from overload and is adequate for noise on this scale. 1. The input signal can be referenced to the center of the common mode range of the converter. 2. The signal is less than ±1.5V. 3. An external reference is used. Reference Capacitor V+ A 0.1µF capacitor gives good results in most applications. However, where a large common mode voltage exists (i.e., the REF LO pin is not at analog COMMON) and a 200mV scale is used, a larger value is required to prevent roll-over error. Generally 1µF will hold the roll-over error to 0.5 count in this instance. CD4009 V+ OSC 1 1N914 OSC 2 OSC 3 Oscillator Components 0.047 µF ICL7107 For all ranges of frequency a 100kΩ resistor is recommended and the capacitor is selected from the equation: + 10 µF - 1N914 GND V- 0.45 f = ----------- For 48kHz Clock (3 Readings/sec), RC V- = 3.3V C = 100pF. FIGURE 10. GENERATING NEGATIVE SUPPLY FROM +5V 10