Data Sheet

PTN3365
Enhanced performance HDMI/DVI level shifter with active DDC
buffer, supporting 3 Gbit/s operation
Rev. 1.1 — 28 July 2015
Product data sheet
1. General description
PTN3365 is a high-speed level shifter device which converts four lanes of low-swing
AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain
current-steering differential output signals, up to 3.0 Gbit/s per lane to support 36-bit
deep color mode, 4K  2K video format or 3D video data transport. Each of these lanes
provides a level-shifting differential buffer to translate from low-swing AC-coupled
differential signaling on the source side, to TMDS-type DC-coupled differential
current-mode signaling terminated into 50  to 3.3 V on the sink side. Additionally,
PTN3365 provides a single-ended active buffer for voltage translation of the HPD signal
from 5 V on the sink side to 3.3 V on the source side and provides a channel with active
buffering and level shifting of the DDC channel (consisting of a clock and a data line)
between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using
active I2C-bus buffer technology providing capacitive isolation, redriving and level shifting
as well as disablement (isolation between source and sink) of the clock and data lines.
The low-swing AC-coupled differential input signals to PTN3365 typically come from a
display source with multi-mode I/O, which supports multiple display standards, for
example, DisplayPort, HDMI and DVI. While the input differential signals are configured to
carry DVI or HDMI coded data, they do not comply with the electrical requirements of the
DVI v1.0 or HDMI v1.4b specification. By using PTN3365, chip set vendors are able to
implement such reconfigurable I/Os on multi-mode display source devices, allowing the
support of multiple display standards while keeping the number of chip set I/O pins low.
See Figure 1.
PTN3365 features low-swing self-biasing differential inputs which are compliant to the
electrical specifications of DisplayPort Standard v1.2 and/or PCI Express Standard v1.1,
and open-drain current-steering differential outputs compliant to DVI v1.0 and HDMI v1.4b
electrical specifications. The I2C-bus channel actively buffers as well as level-translates
the DDC signals for optimal capacitive isolation. PTN3365 also supports power-saving
modes in order to minimize current consumption when no display is active or connected.
PTN3365 is a full-featured HDMI and DVI level shifter.
PTN3365 is powered from a single 3.3 V power supply consuming a small amount of
power (230 mW typical) and is offered in a 32-terminal HVQFN32 package.
PTN3365
NXP Semiconductors
HDMI/DVI level shifter supporting 3 Gbit/s operation
MULTI-MODE DISPLAY SOURCE
OE_N
reconfigurable I/Os
PCIe PHY ELECTRICAL
TMDS
coded
data
PCIe
output buffer
TX
FF
OUT_D4+
OUT_D4-
AC-coupled
differential pair
TMDS data
IN_D4+
DATA LANE
IN_D4-
TX
TMDS
coded
data
PCIe
output buffer
TX
FF
AC-coupled
differential pair
TMDS data
OUT_D3+
OUT_D3IN_D3+
DATA LANE
IN_D3-
TX
TMDS
coded
data
PCIe
output buffer
TX
FF
AC-coupled
differential pair
TMDS data
DATA LANE
OUT_D2+
OUT_D2IN_D2+
IN_D2-
TX
TMDS
clock
pattern
DVI/HDMI
CONNECTOR
PTN3365
PCIe
output buffer
TX
FF
OUT_D1+
OUT_D1-
AC-coupled
differential pair
clock
CLOCK LANE
IN_D1+
IN_D1-
TX
0 V to 3.3 V
quinary input
3.3 V
HPD_SOURCE
HPD_SINK
0 V to 5 V
EQ5
DDC_EN
(0 V to 3.3 V)
3.3 V
5V
SCL_SOURCE
SCL_SINK
3.3 V
5V
DDC I/O
(I2C-bus)
CONFIGURATION
SDA_SOURCE
SDA_SINK
aaa-013693
Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].
Fig 1.
Typical application system diagram
PTN3365
Product data sheet
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Rev. 1.1 — 28 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PTN3365
NXP Semiconductors
HDMI/DVI level shifter supporting 3 Gbit/s operation
2. Features and benefits
2.1 High-speed TMDS level shifting
 Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.4b compliant open-drain current-steering differential output signals
 TMDS level shifting operation up to 3.0 Gbit/s per lane supporting 4K  2K and 3D
video formats
 Programmable equalizer
 Integrated 50  termination resistors for self-biasing differential inputs
 Back-current safe outputs to disallow current when device power is off and monitor is
on
 Disable feature to turn off TMDS inputs and outputs and to enter low-power state
2.2 DDC level shifting




Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side)
Rise time accelerator on sink-side DDC ports
0 Hz to 400 kHz I2C-bus clock frequency
Back-power safe sink-side terminals to disallow backdrive current when power is off or
when DDC is not enabled
2.3 HPD level shifting
 HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or
from 5 V on the sink side to 3.3 V on the source side
 Integrated 200 k pull-down resistor on HPD sink input guarantees ‘input LOW’ when
no display is plugged in
 Back-power safe design on HPD_SINK to disallow backdrive current when power is off
2.4 General






Power supply 3.0 V to 3.6 V
ESD resilience to 6 kV HBM, 1 kV CDM
Power-saving modes (using output enable)
Back-current-safe design on all sink-side main link, DDC and HPD terminals
Transparent operation: no re-timing or software configuration required
32-terminal HVQFN32 package
3. Applications




PTN3365
Product data sheet
PC motherboard/graphics card
Docking station
DisplayPort to HDMI adapters supporting 4K  2K and 3D video formats
DisplayPort to DVI adapters required to drive long cables
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Rev. 1.1 — 28 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 25
PTN3365
NXP Semiconductors
HDMI/DVI level shifter supporting 3 Gbit/s operation
4. Ordering information
Table 1.
Ordering information
Type number
PTN3365BS
Topside mark
P3365
Package
Name
Description
Version
HVQFN32
plastic thermal enhanced very thin quad flat package; no
leads; 32 terminals; body 5 x 5 x 0.85 mm
SOT617-3
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order
quantity
Temperature range
PTN3365BS
PTN3365BSMP
HVQFN32
Reel 13” Q2/T3
*standard mark SMD dry pack
6000
Tamb = 40 C to +85 C
PTN3365
Product data sheet
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Rev. 1.1 — 28 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PTN3365
NXP Semiconductors
HDMI/DVI level shifter supporting 3 Gbit/s operation
5. Functional diagram
OE_N
input bias
PTN3365
enable
50 W
OUT_D4+
OUT_D4-
50 W
IN_D4+
IN_D4-
EQ
enable
input bias
enable
50 W
OUT_D3+
OUT_D3-
50 W
IN_D3+
IN_D3-
EQ
enable
input bias
enable
50 W
OUT_D2+
OUT_D2-
50 W
IN_D2+
IN_D2-
EQ
enable
input bias
enable
50 W
OUT_D1+
OUT_D1-
50 W
IN_D1+
IN_D1-
EQ
enable
EQ5
HPD level shifter
HPD_SOURCE
(0 V to 3.3 V)
200 kW
HPD_SINK
(0 V to 5 V)
DDC_EN (0 V to 3.3 V)
SCL_SOURCE
SDA_SOURCE
DDC BUFFER
AND
LEVEL SHIFTER
SCL_SINK
SDA_SINK
aaa-013694
Fig 2.
PTN3365
Product data sheet
Functional diagram of PTN3365
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Rev. 1.1 — 28 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PTN3365
NXP Semiconductors
HDMI/DVI level shifter supporting 3 Gbit/s operation
6. Pinning information
25 IN_D1-
26 IN_D1+
27 IN_D2-
28 IN_D2+
29 IN_D3-
30 IN_D3+
terminal 1
index area
31 IN_D4-
32 IN_D4+
6.1 Pinning
VDD
1
24 VDD
EQ5
2
23 DDC_EN
TEST
3
22 GND
REXT
4
HPD_SOURCE
5
SDA_SOURCE
6
19 SCL_SINK
SCL_SOURCE
7
18 VDD
VDD
8
17 OE_N
21 HPD_SINK
OUT_D1- 16
20 SDA_SINK
OUT_D1+ 15
OUT_D2- 14
OUT_D2+ 13
OUT_D3- 12
OUT_D3+ 11
9
OUT_D4+
OUT_D4- 10
PTN3365
aaa-013695
Transparent top view
HVQFN32 package supply ground is connected to both GND pins and exposed center pad.
GND pins and the exposed center pad must be connected to supply ground for proper device
operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs
to be soldered to the board using a corresponding thermal pad on the board and for proper heat
conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad
region.
Fig 3.
Pin configuration for HVQFN32
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type
Description
OE_N, IN_Dx and OUT_Dx signals
OE_N
17
3.3 V low-voltage
Output Enable and power saving function for
CMOS single-ended high-speed differential level shifter path.
input
When OE_N = HIGH:
IN_Dx termination = high-impedance
OUT_Dx outputs = high-impedance; zero
output current
When OE_N = LOW:
IN_Dx termination = 50 
OUT_Dx outputs = active
IN_D4+
PTN3365
Product data sheet
32
Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D4+ makes a differential pair with IN_D4.
The input to this pin must be AC coupled
externally.
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© NXP Semiconductors N.V. 2015. All rights reserved.
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PTN3365
NXP Semiconductors
HDMI/DVI level shifter supporting 3 Gbit/s operation
Table 3.
PTN3365
Product data sheet
Pin description …continued
Symbol
Pin
Type
Description
IN_D4
31
Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D4 makes a differential pair with IN_D4+.
The input to this pin must be AC coupled
externally.
IN_D3+
30
Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D3+ makes a differential pair with IN_D3.
The input to this pin must be AC coupled
externally.
IN_D3
29
Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D3 makes a differential pair with IN_D3+.
The input to this pin must be AC coupled
externally.
IN_D2+
28
Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D2+ makes a differential pair with IN_D2.
The input to this pin must be AC coupled
externally.
IN_D2
27
Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D2 makes a differential pair with IN_D2+.
The input to this pin must be AC coupled
externally.
IN_D1+
26
Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D1+ makes a differential pair with IN_D1.
The input to this pin must be AC coupled
externally.
IN_D1
25
Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D1 makes a differential pair with IN_D1+.
The input to this pin must be AC coupled
externally.
OUT_D4+
9
TMDS differential
output
HDMI compliant TMDS output. OUT_D4+ makes
a differential pair with OUT_D4. OUT_D4+ is in
phase with IN_D4+.
OUT_D4
10
TMDS differential
output
HDMI compliant TMDS output. OUT_D4 makes
a differential pair with OUT_D4+. OUT_D4 is in
phase with IN_D4.
OUT_D3+
11
TMDS differential
output
HDMI compliant TMDS output. OUT_D3+ makes
a differential pair with OUT_D3. OUT_D3+ is in
phase with IN_D3+.
OUT_D3
12
TMDS differential
output
HDMI compliant TMDS output. OUT_D3 makes
a differential pair with OUT_D3+. OUT_D3 is in
phase with IN_D3.
OUT_D2+
13
TMDS differential
output
HDMI compliant TMDS output. OUT_D2+ makes
a differential pair with OUT_D2. OUT_D2+ is in
phase with IN_D2+.
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Rev. 1.1 — 28 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PTN3365
NXP Semiconductors
HDMI/DVI level shifter supporting 3 Gbit/s operation
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
OUT_D2
14
TMDS differential
output
HDMI compliant TMDS output. OUT_D2 makes
a differential pair with OUT_D2+. OUT_D2 is in
phase with IN_D2.
OUT_D1+
15
TMDS differential
output
HDMI compliant TMDS output. OUT_D1+ makes
a differential pair with OUT_D1. OUT_D1+ is in
phase with IN_D1+.
OUT_D1
16
TMDS differential
output
HDMI compliant TMDS output. OUT_D1 makes
a differential pair with OUT_D1+. OUT_D1 is in
phase with IN_D1.
5 V CMOS
single-ended input
0 V to 5 V (nominal) input signal. This signal
comes from the DVI or HDMI sink. A HIGH value
indicates that the sink is connected; a LOW value
indicates that the sink is disconnected.
HPD_SINK is pulled down by an integrated
200 k pull-down resistor.
HPD_SOURCE 5
3.3 V CMOS
single-ended output
0 V to 3.3 V (nominal) output signal. This is
level-shifted version of the HPD_SINK signal.
SCL_SOURCE 7
single-ended 3.3 V 3.3 V source-side DDC clock I/O. Pulled up by
open-drain DDC I/O external termination to 3.3 V. 5 V tolerant I/O.
SDA_SOURCE 6
single-ended 3.3 V 3.3 V source-side DDC data I/O. Pulled up by
open-drain DDC I/O external termination to 3.3 V. 5 V tolerant I/O.
SCL_SINK
19
single-ended 5 V
5 V sink-side DDC clock I/O. Pulled up by
open-drain DDC I/O external termination to 5 V. Provides rise time
acceleration for LOW-to-HIGH transitions.
SDA_SINK
20
single-ended 5 V
5 V sink-side DDC data I/O. Pulled up by
open-drain DDC I/O external termination to 5 V. Provides rise time
acceleration for LOW-to-HIGH transitions.
DDC_EN
23
3.3 V CMOS input
HPD and DDC signals
HPD_SINK
21
Enables the DDC buffer and level shifter.
When DDC_EN = LOW, buffer/level shifter is
disabled.
When DDC_EN = HIGH, buffer and level shifter
are enabled.
TEST
3
3.3 V CMOS input
This is a test pin and it shall always be connected
to GND in the system applications.
Supply and ground
PTN3365
Product data sheet
VDD
1, 8,
18, 24
3.3 V DC supply
Supply voltage; 3.3 V  10 %.
GND[1]
22
ground
Supply ground. All GND pins must be connected
to ground for proper operation.
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Rev. 1.1 — 28 July 2015
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PTN3365
NXP Semiconductors
HDMI/DVI level shifter supporting 3 Gbit/s operation
Table 3.
Symbol
Pin description …continued
Pin
Type
Description
Current sense port used to provide an accurate
current reference for the differential outputs
OUT_Dx. For best output voltage swing
accuracy, use of a 10 k resistor (1 % tolerance)
from this terminal to GND is recommended. May
also be tied to either VDD or GND directly (0 ).
See Section 7.2 for details.
Feature control signals
REXT
4
analog I/O
EQ5
2
3.3 V low-voltage
Equalizer setting input pin. This pin can be
CMOS quinary input board-strapped to one of five decode values:
short to GND, resistor to GND, open-circuit,
resistor to VDD, short to VDD. See Table 5 for
truth table.
[1]
PTN3365
Product data sheet
HVQFN32 package supply ground is connected to both GND pins and exposed center pad. GND pins and
the exposed center pad must be connected to supply ground for proper device operation. For enhanced
thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 28 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 25
PTN3365
NXP Semiconductors
HDMI/DVI level shifter supporting 3 Gbit/s operation
7. Functional description
Refer to Figure 2 “Functional diagram of PTN3365”.
PTN3365 level shifts four lanes of low-swing AC-coupled differential input signals to DVI
and HDMI compliant open-drain current-steering differential output signals, up to
3.0 Gbit/s per lane to support 36-bit deep color mode. It has integrated 50  termination
resistors for AC-coupled differential input signals. An enable signal OE_N can be used to
turn off the TMDS inputs and outputs, thereby minimizing power consumption. The TMDS
outputs are back-power safe to disallow current flow from a powered sink while PTN3365
is unpowered.
PTN3365's DDC channel provides active level shifting and buffering, allowing 3.3 V
source-side termination and 5 V sink-side termination. The sink-side DDC ports are
equipped with a rise time accelerator enabling drive of long cables or high bus
capacitance. This enables the system designer to isolate bus capacitance to meet/exceed
HDMI DDC specification. PTN3365 offers back-power safe sink-side I/Os to disallow
backdrive current from the DDC clock and data lines when power is off or when DDC is
not enabled. An enable signal DCC_EN enables the DDC level shifter block.
PTN3365 also provides voltage translation for the Hot Plug Detect (HPD) signal from 0 V
to 5 V on the sink side to 0 V to 3.3 V on the source side.
PTN3365 does not re-time any data. It contains no state machines. No inputs or outputs of
the device are latched or clocked. Because PTN3365 acts as a transparent level shifter,
no reset is required.
7.1 Enable and disable features
PTN3365 offers different ways to enable or disable functionality, using the Output Enable
(OE_N), and DDC Enable (DDC_EN) inputs. Whenever PTN3365 is disabled, the device
will be in Standby mode and power consumption will be minimal; otherwise PTN3365 will
be in active mode and power consumption will be nominal. These two inputs each affect
the operation of PTN3365 differently: OE_N controls the TMDS channels, DDC_EN
affects only the DDC channel, and HPD_SINK does not affect either of the channels. The
following sections and truth table describe their detailed operation.
7.1.1 Hot plug detect
The HPD channel of PTN3365 functions as a level-shifting buffer to pass the HPD logic
signal from the display sink device (via input HPD_SINK) on to the display source device
(via output HPD_SOURCE).
The output logic state of HPD_SOURCE output always follows the logic state of input
HPD_SINK, regardless of whether the device is in Active mode or Standby mode.
PTN3365
Product data sheet
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Rev. 1.1 — 28 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PTN3365
NXP Semiconductors
HDMI/DVI level shifter supporting 3 Gbit/s operation
7.1.2 Output Enable function (OE_N)
When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully
functional. Input termination resistors are enabled and the internal bias circuits are turned
on.
When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a
high-impedance state and drive zero output current. The IN_Dx input buffers are disabled
and IN_Dx termination is disabled. Power consumption is minimized.
Remark: Note that OE_N signal level has no influence on the HPD_SINK input,
HPD_SOURCE output, or the SCL and SDA level shifters. A transition from HIGH to LOW
at OE_N may disable the DDC channel for up to 20 s.
7.1.3 DDC channel enable function (DDC_EN)
The DDC_EN pin is active HIGH and can be used to isolate a badly behaved slave. When
DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should never
change state during an I2C-bus operation. Note that disabling DDC_EN during a bus
operation may hang the bus, while enabling DDC_EN during bus traffic would corrupt the
I2C-bus operation. Hence, DDC_EN should only be toggled while the bus is idle. (See
I2C-bus specification).
PTN3365
Product data sheet
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Rev. 1.1 — 28 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PTN3365
NXP Semiconductors
HDMI/DVI level shifter supporting 3 Gbit/s operation
7.1.4 Enable/disable truth table
Table 4.
HPD_SINK, OE_N and DDC_EN enabling truth table
Inputs
Channels
HPD_SINK OE_N
Mode
OUT_Dx[3]
DDC_EN IN_Dx
DDC[4]
HPD_SOURCE[5]
[1]
[2]
LOW
LOW
LOW
50  termination enabled
to VRX(bias)
high-impedance
LOW
Active; DDC
disabled
LOW
LOW
HIGH
50  termination enabled
to VRX(bias)
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
LOW
Active; DDC
enabled
LOW
HIGH
LOW
high-impedance
high-impedance;
zero output current
high-impedance
LOW
Standby
LOW
HIGH
HIGH
high-impedance
high-impedance;
zero output current
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
LOW
Standby;
DDC
enabled
HIGH
LOW
LOW
50  termination enabled
to VRX(bias)
high-impedance
HIGH
Active; DDC
disabled
HIGH
LOW
HIGH
50  termination enabled
to VRX(bias)
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
HIGH
Active; DDC
enabled
HIGH
HIGH
LOW
high-impedance
high-impedance;
zero output current
high-impedance
HIGH
Standby
HIGH
HIGH
HIGH
high-impedance
high-impedance;
zero output current
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
HIGH
Standby;
DDC
enabled
[1]
A HIGH level on input OE_N disables only the TMDS channels. A transition from HIGH to LOW at OE_N may disable the DDC channel
for up to 20 s.
[2]
A LOW level on input DDC_EN disables only the DDC channel.
[3]
OUT_Dx channels ‘enabled’ means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching.
[4]
DDC channel ‘enabled’ means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE.
[5]
The HPD_SOURCE output logic state always follows the HPD_SINK input logic state.
PTN3365
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 28 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
12 of 25
PTN3365
NXP Semiconductors
HDMI/DVI level shifter supporting 3 Gbit/s operation
7.2 Analog current reference
The REXT pin (pin 6) is an analog current sense port used to provide an accurate current
reference for the differential outputs OUT_Dx. For best output voltage swing accuracy,
use of a 10 k resistor (1 % tolerance) connected between this terminal and GND is
recommended.
If an external 10 k  1 % resistor is not used, this pin can be connected to GND or VDD
directly (0 ). In any of these cases, the output will function normally but at reduced
accuracy over voltage and temperature of the following parameters: output levels (VOL),
differential output voltage swing, and rise and fall time accuracy.
7.3 Equalizer
PTN3365 supports 5 level equalization setting by the quinary input pin EQ5.
Table 5.
Equalizer settings
Inputs
Quinary notation
Equalizer mode
short to GND
05
0 dB
10 k resistor to GND
15
2 dB
open-circuit
25
3.5 dB
10 k resistor to VDD
35
9 dB
short to VDD
45
7 dB
EQ5
7.4 Backdrive current protection
PTN3365 is designed for backdrive prevention on all sink-side TMDS outputs, sink-side
DDC I/Os and the HPD_SINK input. This supports user scenarios where the display is
connected and powered, but PTN3365 is unpowered. In these cases, PTN3365 will sink
no more than a negligible amount of leakage current, and will block the display (sink)
termination network from driving the power supply of PTN3365 or that of the inactive DVI
or HDMI source.
7.5 Active DDC buffer with rise time accelerator
PTN3365 DDC channel, besides providing 3.3 V to 5 V level shifting, includes active
buffering and rise time acceleration which allows up to 18 meters bus extension for
reliable DDC applications. While retaining all the operating modes and features of the
I2C-bus system during the level shifts, it permits extension of the I2C-bus by providing
bidirectional buffering for both the data (SDA) and the clock (SCL) line as well as the
rise time accelerator on the sink-side port (SCL_SINK and SDA_SINK) enabling the bus
to drive a load up to 1400 pF or distance of 18 m on the sink-side port, and 400 pF on the
source-side port (SCL_SOURCE and SCA_SOURCE). Using PTN3365 for DVI or HDMI
level shifting enables the system designer to isolate bus capacitance to meet/exceed
HDMI DDC specification. The SDA and SCL pins are overvoltage tolerant and are
high-impedance when PTN3365 is unpowered or when DDC_EN is LOW.
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PTN3365 has rise time accelerators on the sink-side port (SCL_SINK and SDA_SINK)
only. During positive bus transitions on the sink-side port, a current source is switched on
to quickly slew the SCL_SINK and SDA_SINK lines HIGH once the 5 V DDC bus VIL
threshold level of around 1.5 V is exceeded, and turns off as the 5 V DDC bus VIH
threshold voltage of approximately 3.5 V is approached.
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDD
supply voltage
VI
input voltage
Tstg
storage temperature
VESD
electrostatic discharge
voltage
Min
Max
Unit
0.3
+4.6
V
3.3 V CMOS inputs
0.3
VDD + 0.5
V
5.0 V CMOS inputs
0.3
6.0
V
65
+150
C
HBM
[1]
-
6000
V
CDM
[2]
-
1000
V
[1]
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2]
Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device
Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
9. Recommended operating conditions
Table 7.
Recommended operating conditions
Symbol
Parameter
VDD
supply voltage
VI
input voltage
Conditions
Min
3.0
3.3
3.6
V
3.3 V CMOS inputs
0
-
3.6
V
5.0 V CMOS inputs
VI(AV)
average input
voltage
IN_Dn+, IN_Dn inputs
[1]
Rref(ext)
external reference
resistance
connected between pin
REXT (pin 6) and GND
[2]
Tamb
ambient temperature operating in free air
Typ
Max
Unit
0
-
5.5
V
-
0
-
V
-
10  1 %
-
k
40
-
+85
C
[1]
Input signals to these pins must be AC-coupled.
[2]
Operation without external reference resistor is possible but will result in reduced output voltage swing
accuracy. For details, see Section 7.2.
9.1 Current consumption
PTN3365
Product data sheet
Table 8.
Current consumption
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDD
supply current
OE_N = 0; Active mode
-
70
100
mA
OE_N = 1 and DDC_EN = 0;
Standby mode
-
-
5
mA
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10. Characteristics
10.1 Differential inputs
Table 9.
Symbol
UI
Differential input characteristics for IN_Dx signals
Parameter
unit
Conditions
interval[1]
[2]
[3]
VRX_DIFFp-p
differential input peak-to-peak voltage
tRX_EYE
receiver eye time
minimum eye width at
IN_Dx input pair
Vi(cm)M(AC)
peak common-mode input voltage (AC)
includes all frequencies
above 30 kHz
ZRX_DC
DC input impedance
VRX(bias)
bias receiver voltage
ZI(se)
single-ended input impedance
[4]
[5]
inputs in
high-impedance state
Min
Typ
Max
Unit
333
-
4000
ps
0.175
-
1.200
V
0.8
-
-
UI
-
-
100
mV
40
50
60

1.0
1.2
1.4
V
100
-
-
k
[1]
UI (unit interval) = tbit (bit time).
[2]
UI is determined by the display mode. Nominal bit rate ranges from 250 Mbit/s to 3.0 Gbit/s per lane.
[3]
VRX_DIFFp-p = 2  VRX_D+  VRX_D. Applies to IN_Dx signals.
[4]
Vi(cm)M(AC) = VRX_D+ + VRX_D / 2  VRX(cm).
VRX(cm) = DC (avg) of VRX_D+ + VRX_D / 2.
[5]
Differential inputs will switch to a high-impedance state when OE_N is HIGH.
10.2 Differential outputs
The level shifter’s differential outputs are designed to meet HDMI version 1.4a and
DVI version 1.0 specifications.
Table 10.
Symbol
Differential output characteristics for OUT_Dx signals
Parameter
Conditions
Min
Typ
VTT  0.01 VTT
Max
Unit
VOH(se)
single-ended HIGH-level
output voltage
[1]
VOL(se)
single-ended LOW-level
output voltage
[2]
VTT  0.60 VTT  0.50 VTT  0.40 V
VO(se)
single-ended output
voltage variation
logic 1 and logic 0 state applied
respectively to differential inputs
IN_Dn; Rref(ext) connected;
see Table 7
[3]
400
500
600
mV
IOZ
OFF-state output current
single-ended
-
-
10
A
VTT + 0.01 V
tr
rise time
20 % to 80 %
75
-
240
ps
tf
fall time
80 % to 20 %
75
-
240
ps
tsk
skew time
intra-pair
[4]
-
-
10
ps
inter-pair
[5]
-
-
250
ps
jitter contribution
[6]
-
10
-
ps
tjit(add)
added jitter time
[1]
VTT is the DC termination voltage in the HDMI or DVI sink. VTT is nominally 3.3 V.
[2]
The open-drain output pulls down from VTT.
[3]
Swing down from TMDS termination voltage (3.3 V  10 %).
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[4]
This differential skew budget is in addition to the skew presented between IN_D+ and IN_D paired input pins.
[5]
This lane-to-lane skew budget is in addition to skew between differential input pairs.
[6]
Jitter budget for differential signals as they pass through the level shifter.
10.3 HPD_SINK input, HPD_SOURCE output
Table 11.
HPD characteristics
Symbol
Parameter
Conditions
VIH
HIGH-level input voltage
HPD_SINK
Min
Typ
Max
Unit
2.0
5.0
5.3
V
VIL
LOW-level input voltage
HPD_SINK
0
-
0.8
V
ILI
input leakage current
HPD_SINK
-
-
15
A
[1]
VOH
HIGH-level output voltage
HPD_SOURCE
2.5
-
VDD
V
VOL
LOW-level output voltage
HPD_SOURCE
0
-
0.2
V
tPD
propagation delay
from HPD_SINK to HPD_SOURCE;
50 % to 50 %
[2]
-
-
200
ns
tt
transition time
HPD_SOURCE rise/fall; 10 % to 90 %
[3]
1
-
20
ns
Rpd
pull-down resistance
HPD_SINK input pull-down resistor
[4]
100
200
300
k
[1]
Low-speed input changes state on cable plug/unplug.
[2]
Time from HPD_SINK changing state to HPD_SOURCE changing state. Includes HPD_SOURCE rise/fall time.
[3]
Time required to transition from VOH to VOL or from VOL to VOH.
[4]
Guarantees HPD_SINK is LOW when no display is plugged in.
10.4 OE_N, DDC_EN and test inputs
Table 12.
OE_N, DDC_EN input characteristics
Symbol
Parameter
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
ILI
input leakage current
[1]
Conditions
Min
2.0
OE_N pin
[1]
-
Typ
Max
Unit
-
0.8
V
-
10
A
-
V
Measured with input at VIH maximum and VIL minimum.
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10.5 DDC characteristics
Table 13.
Symbol
DDC characteristics
Parameter
Conditions
Input and output SCL_SOURCE and SDA_SOURCE, VCC1 = 3.0 V to 3.6
Min
Typ
Max
Unit
0.7VCC1
-
3.6
V
V[1]
VIH
HIGH-level input voltage
VILc
contention LOW-level input voltage
guaranteed by design
0.5
-
0.4
V
ILI
input leakage current
VI = 3.6 V
-
-
10
A
IIL
LOW-level input current
VI = 0.2 V
-
-
10
A
0.47
0.52
0.6
V
[2]
VOL
LOW-level output voltage
IOL = 6 mA
VOLVILc
difference between LOW-level output
and LOW-level input voltage
contention
guaranteed by design
-
-
70
mV
Cio
input/output capacitance
VI = 3 V or 0 V; VDD = 3.3 V
-
6
7
pF
VI = 3 V or 0 V; VDD = 0 V
-
6
7
pF
Input and output SDA_SINK and SCL_SINK, VCC2 = 4.5 V to 5.5 V[3]
VIH
HIGH-level input voltage
0.7VCC2
-
5.5
V
VIL
LOW-level input voltage
0.5
-
+1.2
V
ILI
input leakage current
VI = 5.5 V
-
-
10
A
IIL
LOW-level input current
VI = 0.2 V
-
-
10
A
VOL
LOW-level output voltage
IOL = 6 mA
-
0.1
0.2
V
Cio
input/output capacitance
VI = 3 V or 0 V; VDD = 3.3 V
-
-
7
pF
VI = 3 V or 0 V; VDD = 0 V
-
6
7
pF
Itrt(pu)
transient boosted pull-up current
VCC2 = 4.5 V;
slew rate = 1.25 V/s
-
6
-
mA
[1]
VCC1 is the pull-up voltage for DDC source.
[2]
IOL between 100 A and 6 mA guaranteed by design (3 mA typical application)
[3]
VCC2 is the pull-up voltage for DDC sink.
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11. Package outline
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
D
B
SOT617-3
A
terminal 1
index area
A
A1
E
detail X
C
e1
e
9
y1 C
C A B
C
v
w
1/2 e b
y
16
L
17
8
e
e2
Eh
1/2 e
24
1
terminal 1
index area
32
25
X
Dh
0
2.5
Dimensions
Unit(1)
mm
5 mm
scale
A(1)
A1
b
max
0.05 0.30
nom 0.85
min
0.00 0.18
c
D(1)
Dh
E(1)
Eh
5.1
3.75
5.1
3.75
0.2
4.9
3.45
4.9
e
e1
e2
0.5
3.5
3.5
L
v
w
y
y1
0.5
0.1
0.05 0.05
0.1
0.3
3.45
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline
version
SOT617-3
Fig 4.
References
IEC
JEDEC
JEITA
sot617-3_po
European
projection
Issue date
11-06-14
11-06-21
MO-220
Package outline SOT617-3 (HVQFN32)
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12. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
12.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
12.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
12.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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12.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 5) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 14 and 15
Table 14.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 15.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 5.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 5.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
13. Abbreviations
Table 16.
PTN3365
Product data sheet
Abbreviations
Acronym
Description
CDM
Charged-Device Model
CEC
Consumer Electronics Control
DDC
Data Display Channel
DVI
Digital Visual Interface
EMI
ElectroMagnetic Interference
ESD
ElectroStatic Discharge
HBM
Human Body Model
HDMI
High-Definition Multimedia Interface
HPD
Hot Plug Detect
I2C-bus
Inter-IC bus
I/O
Input/Output
NMOS
Negative-channel Metal-Oxide Semiconductor
TMDS
Transition Minimized Differential Signaling
VESA
Video Electronic Standards Association
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14. Revision history
Table 17.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PTN3365 v.1.1
20150728
Product data sheet
-
PTN3365 v.1
-
-
Modifications:
PTN3365 v.1
PTN3365
Product data sheet
•
Changed document status to Company Public.
20141203
Product data sheet
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PTN3365
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 28 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
23 of 25
PTN3365
NXP Semiconductors
HDMI/DVI level shifter supporting 3 Gbit/s operation
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Licenses
Purchase of NXP ICs with HDMI technology
Use of an NXP IC with HDMI technology in equipment that complies with
the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.
Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:
[email protected].
15.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PTN3365
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 28 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
24 of 25
PTN3365
NXP Semiconductors
HDMI/DVI level shifter supporting 3 Gbit/s operation
17. Contents
1
2
2.1
2.2
2.3
2.4
3
4
4.1
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.3
7.4
7.5
8
9
9.1
10
10.1
10.2
10.3
10.4
10.5
11
12
12.1
12.2
12.3
12.4
13
14
15
15.1
15.2
15.3
15.4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 3
High-speed TMDS level shifting . . . . . . . . . . . . 3
DDC level shifting . . . . . . . . . . . . . . . . . . . . . . . 3
HPD level shifting . . . . . . . . . . . . . . . . . . . . . . . 3
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . 10
Enable and disable features . . . . . . . . . . . . . . 10
Hot plug detect . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable function (OE_N) . . . . . . . . . . . 11
DDC channel enable function (DDC_EN). . . . 11
Enable/disable truth table . . . . . . . . . . . . . . . . 12
Analog current reference . . . . . . . . . . . . . . . . 13
Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Backdrive current protection . . . . . . . . . . . . . . 13
Active DDC buffer with rise time accelerator . 13
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14
Recommended operating conditions. . . . . . . 14
Current consumption . . . . . . . . . . . . . . . . . . . 14
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 15
Differential inputs . . . . . . . . . . . . . . . . . . . . . . 15
Differential outputs . . . . . . . . . . . . . . . . . . . . . 15
HPD_SINK input, HPD_SOURCE output . . . . 16
OE_N, DDC_EN and test inputs. . . . . . . . . . . 16
DDC characteristics . . . . . . . . . . . . . . . . . . . . 17
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Soldering of SMD packages . . . . . . . . . . . . . . 19
Introduction to soldering . . . . . . . . . . . . . . . . . 19
Wave and reflow soldering . . . . . . . . . . . . . . . 19
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 20
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22
Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
15.5
16
17
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Contact information . . . . . . . . . . . . . . . . . . . . 24
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 28 July 2015
Document identifier: PTN3365