PI3VDP411LST

PI3VDP411LST
Digital Video Level Shifter for dual mode DP signals
w/ inverting buffer for HPD signal
Description
Features
•
•
•
•
•
•
•
•
•
•
•
•
Converts low-swing AC coupled differential input to HDMI
rev 1.3 compliant open-drain current steering Rx terminated
differential output
HDMI level shifting operation up to 2.5Gbps per lane
(250MHz pixel clock)
Integrated 50-ohm termination resistors for AC-coupled differential inputs.
Enable/Disable feature to turn off TMDS outputs to enter
low-power state.
Output slew rate control on TMDS outputs to minimize EMI.
Transparent operation: no re-timing or configuration required.
3.3 Power supply required.
Integrated ESD protection up to 8kV contact on all high
speed I/O pins (IN_x and OUT_x) per IEC61000-4-2 specification, level 4
DDC level shifters from 5V down to 3.3V
Inverting level shifter for HPD signal from HDMI/DVI
connector
Integrated pull-down on HPD_sink input guarantees "input
low" when no display is plugged in
Packaging (Pb-Free & Green available)
– 48 TQFN, 7mm × 7mm (ZD)
– 42 TQFN, 9mm × 3.5mm (ZH)
– 48 TQFN, 7mm × 7mm (ZB)
Pericom Semiconductor’s PI3VDP411LST provides the ability
to use a Dual-mode Display Port transmitter in HDMI mode.
This flexibility provides the user a choice of how to connect to
their favorite display. All signal paths accept AC coupled video
signals. The PI3VDP411LST converts this AC coupled signal
into an HDMI rev 1.3 compliant signal with proper signal swing.
This conversion is automatic and transparent to the user.
The PI3VDP411LST supports up to 2.5Gbps, which provides
12-bits of color depth per channel, as indicated in HDMI rev 1.3.
Pin Configuration
08-0294
1
VDD
OE#
30
GND
31
SDA_SINK
32
SCL_SINK
HPD_SINK
VDD
DDC_EN
EQ_1
33
29
28
27
26
25
24
IN_D1-
38
23
OUT_D1-
IN_D1+
39
22
OUT_D1+
VDD
VDD
GND
40
21
IN_D2-
41
20
OUT_D2-
IN_D2+
42
19
OUT_D2+
GND
43
18
GND
IN_D3-
44
17
OUT_D3-
IN_D3+
45
16
OUT_D3+
VDD
46
15
VDD
IN_D4-
47
14
OUT_D4-
IN_D4+
48
OUT_D4+
1
2
3
4
5
6
7
8
9
10
11
13
12
GND
OC_2(REXT )
HPD_SOURCE#
SDA_SOURCE
SCL_SOURCE
OC_3
VDD
GND
GND
OC_1
SCL_Source
34
37
VDD
VDD
SDA_Source
33
32
31
GND
30
29
28
27
26
25
24
23
18 19 20 21 22
35
GND
OC_0
34
VDD
OE#
GND
OUT_D1OUT_D1+
VDD
OUT_D2OUT_D2+
GND
OUT_D3OUT_D3+
VDD
OUT_D4OUT_D4+
GND
GND
38
37
36
35
EQ_0
GND
36
GND
SCL_SINK
42 41 40 39
HPD_Source#
9
10
11
12
13
14
15
16
17
SDA_SINK
HPD_SINK
1
2
3
4
5
6
7
8
OC_S1
OC_S2
DDC_EN
EQ_0
GND
IN_D1IN_D1+
VDD
IN_D2IN_D2+
GND
IN_D3IN_D3+
VDD
IN_D4IN_D4+
GND
VDD
OC_S0
GND
48-Pin TQFN (ZD/ZB)
42-Pin TQFN (ZH)
PS8906F
11/06/08
PI3VDP411LST
Digital Video Level Shifter for dual mode DP signals
w/ inverting buffer for HPD signal
Block Diagram
OE#
OUT_D4+
OUT_D4-
0V
IN_D4+
IN_D4-
Rx
OUT_D3+
OUT_D3-
0V
IN_D3+
IN_D3-
Rx
OUT_D2+
OUT_D2-
0V
IN_D2+
IN_D2-
Rx
OUT_D1+
OUT_D1-
0V
IN_D1+
IN_D1-
HPD_SOURCE#
08-0294
2
Rx
HPD_SINK
HPD
SCL_SOURCE
SCL_SINK
SDA_SOURCE
SDA_SINK
PS8906F
11/06/08
PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .....................................–65°C to +150°C
Supply Voltage to Ground Potential .............–0.5V to +5V
DC Input Voltage ..........................................–0.5V to VDD
DC Output Current .......................................120mA
Power Dissipation .........................................1.0W
Table 2: Signal Descriptions
Pin Name
Type
OE#
5.5V tolerant low-voltage
single-ended input
IN_D4+
Differential input
IN_D4–
Differential input
IN_D3+
Differential input
IN_D3–
Differential input
IN_D2+
Differential input
IN_D2–
Differential input
IN_D1+
Differential input
IN_D1–
Differential input
OUT_D4+
TMDS Differential output
OUT_D4–
TMDS Differential output
OUT_D3+
TMDS Differential output
OUT_D3–
TMDS Differential output
08-0294
3
Note: Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Description
Enable for level shifter path
OE#
IN_D Termination OUT_D Outputs
1
>100KΩ
High-Z
0
50Ω
Active
Low-swing diff input from GMCH PCIE outputs.
IN_D4+ makes a differential pair with IN_D4–.
Low-swing diff input from GMCH PCIE outputs.
IN_D4– makes a differential pair with IN_D4+.
Low-swing diff input from GMCH PCIE outputs.
IN_D3+ makes a differential pair with IN_D3–.
Low-swing diff input from GMCH PCIE outputs.
IN_D3– makes a differential pair with IN_D3+.
Low-swing diff input from GMCH PCIE outputs.
IN_D2+ makes a differential pair with IN_D2–.
Low-swing diff input from GMCH PCIE outputs.
IN_D2– makes a differential pair with IN_D2+.
Low-swing diff input from GMCH PCIE outputs.
IN_D1+ makes a differential pair with IN_D1–.
Low-swing diff input from GMCH PCIE outputs.
IN_D1– makes a differential pair with IN_D1+.
HDMI 1.3 compliant TMDS output. OUT_D4+
makes a differential output signal with OUT_D4–.
HDMI 1.3 compliant TMDS output. OUT_D4–
makes a differential output signal with OUT_D4+.
HDMI 1.3 compliant TMDS output. OUT_D3+
makes a differential output signal with OUT_D3–.
HDMI 1.3 compliant TMDS output. OUT_D3–
makes a differential output signal with OUT_D3+.
PS8906F
11/06/08
PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Pin Name
OUT_D2+
Type
TMDS Differential output
OUT_D2–
TMDS Differential output
OUT_D1+
TMDS Differential output
OUT_D1–
TMDS Differential output
HPD_SINK
5V tolerance single-ended input Low Frequency, 0V to 5V (nominal) input signal. This
signal comes from the HDMI connector. Voltage High
indicates "plugged" state; voltage low indicated
"unplugged". HPD_SINK is pulled down by an
integrated 100K ohm pull-down resistor.
1V buffer
Inverted buffer from 0V to 5V input signal. If input is
LOGIC HIGH, then output will be LOGIC LOW, with
VOL max of 0.1V max. If input is LOGIC LOW, then
output will be LOGIC HIGH, with VOH of 0.8V min.
Single-ended 3.3V open-drain 3.3V DDC Data I/O. Pulled up by external terminaDDC I/O
tion to 3.3V. Connected to SCL_SINK through voltage-limiting integrated NMOS passgate.
Single-ended 3.3V open-drain 3.3V DDC Data I/O. Pulled up by external termination
DDC I/O
to 3.3V. Connected to SDA_SINK through voltagelimiting integrated NMOS passgate.
Single-ended 5V open-drain
5V DDC Clock I/O. Pulled up by external termination
DDC I/O
to 5V. Connected to SCL_SOURCE through voltagelimiting integrated NMOS passgate.
Single-ended 5V open-drain
5V DDC Data I/O. Pulled up by external termination
DDC I/O
to 5V. Connected to SDA_SOURCE through voltagelimiting integrated NMOS passgate.
5.0V tolerant Single-ended
Enables bias voltage to the DDC passgate level shifter
input
gates. (May be implemented as a bias voltage connection to the DDC pass gates themselves.)
DDC_EN
Passgate
0V
Disabled
3.3V
Enabled
HPD_SOURCE#
SCL_SOURCE
SDA_SOURCE
SCL_SINK
SDA_SINK
DDC_EN
VDD
OC_2 (1)
(REXT)
Description
HDMI 1.3 compliant TMDS output. OUT_D2+ makes
a differential output signal with OUT_D2–.
HDMI 1.3 compliant TMDS output. OUT_D2– makes
a differential output signal with OUT_D2+.
HDMI 1.3 compliant TMDS output. OUT_D1+ makes
a differential output signal with OUT_D1–.
HDMI 1.3 compliant TMDS output. OUT_D1– makes
a differential output signal with OUT_D1+.
3.3V DC Supply
3.3V ± 10%
3.3V single-ended control input Acceptable connections to OC_1 (REXT) pin are: Resistor to GND; Resistor to 3.3V; NC. (Resistor should
be 0-ohm).
Note:
1) internal 100Kohm pull-up
08-0294
4
PS8906F
11/06/08
PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Pin Name
OC_3
Type
Analog connection to external
component or supply
Output and Input jitter elimination control
OC_0
OC_1
EQ_0
EQ_1
Truth Table 1
OC_3(2)
OC_2(1)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Truth Table 2
EQ_1(2)
EQ_0(1)
0
0
1
1
0
1
0
1
OC_1(1)
OC_0(1)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Acceptable connections to OC_3 pin are: short to
3.3V or to GND; NC.
Control pins are to enable Jitter elimination features.
For normal operation these pins are tied GND or to
VDD. Please see the truth tables for more information.
Vswing
(mV)
500
600
750
1000
500
500
500
500
400
400
400
400
1000
1000
1000
1000
Pre/Deemphasis
0
0
0
0
0
1.5dB
3.5dB
6dB
0
3.5dB
6dB
9dB
0
-3.5dB
-6dB
-9dB
Equalization
@ 1.25GHz
(dB)
3
6
9
12
Notes:
1. Internal 100Kohm pull-up
2. For 42-TQFN (ZHE) package, there is an internal connection to GND.
For 48-TQFN (ZDE) package, external connection is allowed and there is an internal 100KΩ pull-up.
08-0294
5
PS8906F
11/06/08
PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Electrical Characteristics
Table 3: Power Supplies and Temperature Range
Symbol
Parameter
Min
Nom
VDD
3.3V Power
3.0
3.3
Supply
ICC
Max Current
ICCQ
TCASE
Standby Current Consumption
Case temperature range for
operation with
spec.
Table 4: OE# Description
OE#
Asserted (low voltage)
Unasserted (high voltage)
-40
Max
Units
3.6
V
100
mA
2
mA
85
Celcius
Device State
Differential input buffers and output
buffers enabled. Input impedance =
50Ω
Low-power state.
Differential input buffers and termination are disabled. Differential
inputs are in a high-impedance state.
OUT_D level-shifting outputs are
disabled.
OUT_D level-shifting outputs are in
high-impedence state.
Internal bias currents are turned off.
08-0294
6
Comments
Total current from
VDD 3.3V supply
when de-emphasis/
pre-emphasis is set to
0dB.
OE# = HIGH
Comments
Normal functioning state for IN_D
to OUT_D level shifting function.
Intended for lowest power condition when:
•
•
No display is plugged in or
The level shifted data path is
disabled
HPD_SINK input and HPD_SOURCE#
output are not affected by OE# SCL_
SOURCE, SCL_SINK, SDA_SOURCE
and SDA_SINK signals and functions are
not affected by OE#
PS8906F
11/06/08
PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Table 5: Differential Input Characteristics for IN_D and RX_IN signals
Symbol
Parameter
Min Nom Max Units Comments
Tbit is determined by the display mode. NomTbit
Unit Interval
360
ps
inal bit rate ranges from 250Mbps to 2.5Gbps
per lane. Nominal Tbit at 2.5Gbps=400ps.
360ps=400ps-10%
VRX-DIFFp-p Differential Input Peak 0.175
to Peak Voltage
Minimum Eye Width at 0.8
TRX-EYE
IN_D input pair
VCM-AC-pp AC Peak
Common Mode Input
Voltage
ZRX-DC
40
VRX-Bias
0
ZRX-HIGH-Z
100
08-0294
1.200 V
Tbit
50
100
mV
60
Ω
2.0
V
kΩ
7
VRX-DIFFp-p=2'|VRX-D+ x VRX-D-|
Applies to IN_D and RX_IN signals
The level shifter may add a maximum of
0.02UI jitter
VCM-AC-pp = |VRX-D+ + VRX-D-|/2
- VRX-CM-DC.
VRX-CM-DC = DC(avg) of|VRX-D+ +
VRX-D-|/2
VCM-AC-pp includes all frequencies
above 30 kHz.
Required IN_D+ as well as IN_D- DC
impedance (50Ω ± 20% tolerance).
Intended to limit power-up stress on
chipset's PCIE output buffers.
Differential inputs must be in a high impedance state when OE# is HIGH.
PS8906F
11/06/08
PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
TMDS Outputs
The level shifter's TMDS outputs are required to meet HDMI 1.3 specifications.
The HDMI 1.3 Specification is assumed to be the correct reference in instances where this document conflicts
with the HDMI 1.3 specification.
Table 6: Differential Output Characteristics for TMDS_OUT signals
Symbol
VH
Parameter
Min
Single-ended
AVDD-10mV
high level output
voltage
VL
Single-ended
AVDD-600mV AVDD-500mV AVDD-400mV
low level output
voltage
Single-ended
450mV
500mV
600mV
output swing
voltage
Single-ended
50
current in high-Z
state
V
TR
Rise time
125ps
0.4Tbit
ps
TF
Fall time
125ps
0.4Tbit
ps
TSKEW-INTRA
Intra-pair
differential skew
30
ps
TSKEW-INTER
Inter-pair laneto-lane output
skew
100
ps
TJIT
Jitter added to
TMDS signals
25
ps
VSWING
IOFF
08-0294
Nom
AVDD
8
Max
AVDD+10mV
Units Comments
AVDD is the DC terminaV
tion voltage in the HDMI
or DVI Sink. AVDD is
nominally 3.3V
The open-drain output
pulls down from AVDD.
V
Swing down from TMDS
termination voltage (3.3V
± 10%)
μA
Measured with TMDS
outputs pulled up to
AVDD Max (3.6V)
through 50Ω resistors.
Max Rise/Fall time
@2.7Gbps = 148ps.
125ps = 148-15%
Max Rise/Fall time
@2.7Gbps = 148ps.
125ps = 148-15%
This differential skew
budget is in addition to
the skew presented between D+ and D- paired
input pins. HDMI revision
1.3 source allowable intra-pair skew is 0.15Tbit.
This lane-to-lane skew
budget is in addition to
skew between differential
input pairs
Jitter budget for TMDS
signals as they pass
through the level
shifter. 25ps = 0.056
Tbit at 2.25 Gb/s
PS8906F
11/06/08
PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
TMDS output oscillation elimination
The inputs do not incorporate a squelch circuit. Therefore, we reccomend the input to be externally biased to
prevent output oscillation. Pericom reccomends to add a 1.5Kohm pull-up to the CLK- input for each oif the
video input ports.
VBIAS
3.3V
1.5Kohm
RINT
RINT
DMDP
Receiver
TMDS
Driver
SS
RT
AVDD
SS
RT
TMDS Input Fail-Safe Recommendation
08-0294
9
PS8906F
11/06/08
PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Table 8: HPD Characteristics
Symbol
Parameter
Input High Level
VIH-HPD
VIL-HPD
IIN-HPD
VOH-HPDB
VOL-HPDB
THPD
TRF-HPDB
HPD_sink Input
Low Level
HPD_sink Input
Leakage Current
HPD_Source#
Output High-Level, IOH = -200μA
HPD_Source#
Output Low-Level, IOL = 200μA
HPD_Source#
to HPD_source
propagation delay
HPD_Source#
rise/fall time
Table 9: OE# Input and DDC_EN
Symbol
Parameter
VIH
Input High Level
VIL
IIN
Input Low Level
Input Leakage Current
Min
2.0
Nom
5.0
Max
5.3
Units
V
0.8
V
70
μA
0.8
1.1
V
0
0.1
V
200
ns
20
ns
0
1
Min
Nom
Comments
Low-speed input changes state on
cable plug/unplug
Measured with HPD_sink at VIH-HPD
max and VIL-HPD min
VDD = 3.3V ± 10%
Time from HPD_sink changing state
to HPD_source# changing state. Includes HPD_source rise/fall time
Time required to transition from VOHHPD to VOL-HPD or from VOL-HPD to
VOH-HPD
Max
Units
2.0
VDD
V
0
0.8
10
V
μA
Comments
TMDS enable input changes state
on cable plug/unplug
Measured with input at VIH-EN
max and VIL-EN min
DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK)
|Ilkg|
Input leakage current
VI = 0.1VDD to 0.9VDD to isolated
DDC ports
0.1
CIO
Input/output capacitance
VI = 0V
7.5
RON
Switch resistance
IO = 3mA, VO = 0.4V
VPASS
Switch output voltage
08-0294
VI = 3.3V, II = 100μA
10
1.5(2)
2
μA
pF
25
50
ohm
2.0
2.5(3)
V
PS8906F
11/06/08
PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Table 10: Termination Resistors
Symbol
Parameter
HPD_sink input pulldown resistor.
RHPD
Min
Nom
Max
Units
Comments
80K
100k
120K
Ω
Guarantees HPD_sink is LOW when
no display is plugged in.
Packaging Mechanical: 48-Pin, TQFN (ZD)
DATE: 11/16/07
DESCRIPTION: 48-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZD (ZD48)
DOCUMENT CONTROL #: PD-2045
08-0294
11
REVISION: B
PS8906F
11/06/08
PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Packaging Mechanical: 42-Pin, TQFN (ZH)
DATE: 03/03/08
DESCRIPTION: 42-contact Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZH (ZH42)
DOCUMENT CONTROL #: PD-2035
REVISION: B
08-0098
08-0294
12
PS8906F
11/06/08
PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Packaging Mechanical: 48-Pin, TQFN (ZB)
1
DATE: 08/13/08
DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE:
ZB48
DOCUMENT CONTROL #: PD-2080
REVISION: --
Ordering Information
Ordering Code
Package Code
Package Description
PI3VDP411LSTZDE
ZD
48-pin Pb-free & Green, TQFN
PI3VDP411LSTZHE
ZH
42-pin Pb-free & Green, TQFN
PI3VDP411LSTZBE
ZB
48-pin Pb-free & Green, TQFN
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• Adding an X Suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
08-0294
13
PS8906F
11/06/08