PCAL6524
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O
expander with Agile I/O features, interrupt output and reset
Rev. 1 — 22 September 2015
Product data sheet
1. General description
The PCAL6524 is a 24-bit general purpose I/O expander that provides remote I/O
expansion for most microcontroller families via the Fast-mode Plus (Fm+) I2C-bus
interface. The ultra low-voltage interface allows for direct connection to a microcontroller
operating down to 0.8 V.
NXP I/O expanders provide a simple solution when additional I/Os are needed while
keeping interconnections to a minimum, for example, in battery-powered mobile
applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing
a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage
level down to 0.8 V to I/O devices operating at a different voltage level 1.65 V to 5.5 V.
The PCAL6524 has built-in level shifting feature that makes these devices extremely
flexible in mixed power supply systems where communication between incompatible I/O
voltages is required, allowing seamless communications with next-generation low voltage
microprocessors and microcontrollers on the interface side (SDA/SCL) and peripherals at
a higher voltage on the port side.
There are two supply voltages for PCAL6524: VDD(I2C-bus) and VDD(P). VDD(I2C-bus) provides
the supply voltage for the interface at the master side (for example, a microcontroller) and
the VDD(P) provides the supply for core circuits and Port P. The bidirectional voltage level
translation in the PCAL6524 is provided through VDD(I2C-bus). VDD(I2C-bus) should be
connected to the VDD of the external SCL/SDA lines. This indicates the VDD level of the
I2C-bus to the PCAL6524, while the voltage level on Port P of the PCAL6524 is
determined by the VDD(P).
The PCAL6524 fully meets the Fm+ I2C-bus specification at speeds to 1 MHz and
implements Agile I/O, which are additional features specifically designed to enhance the
I/O. These additional features are: programmable output drive strength, latchable inputs,
programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register,
programmable open-drain or push-pull outputs.
Additional Agile I/O Plus features include I2C software reset and device ID. Interrupts can
be specified by level or edge, and can be cleared individually without disturbing the other
interrupt events. Also, switch debounce hardware is implemented.
At power-on, the I/Os are configured as inputs. However, the system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding input or output register. The polarity of
the Input Port register can be inverted with the Polarity Inversion register, saving external
logic gates. Programmable pull-up and pull-down resistors eliminate the need for discrete
components.
PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
The power-on reset puts the registers in their default state and initializes the
I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to
occur without depowering the part. The system master can also accomplish a reset via an
I2C command and initialize all registers to their default state.
The PCAL6524 open-drain interrupt (INT) output is activated when any input state differs
from its corresponding Input Port register state. As well, the INT output can be specified to
activate on input pin edges. There are a large number of interrupt mask functions
available to maximize flexibility.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without communication via the I2C-bus. Thus, the PCAL6524 can remain a
simple slave device. The input latch feature holds or latches the input pin state and keeps
the logic values that created the interrupt until the master can service the interrupt. This
minimizes the host’s interrupt service response for fast moving inputs.
The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while
consuming low device current.
One hardware pin (ADDR) can be used to program and vary the fixed I2C-bus address
and allow up to four devices to share the same I2C-bus or SMBus.
2. Features and benefits
PCAL6524
Product data sheet
I2C-bus to parallel port expander
1 MHz Fast-mode Plus I2C-bus
Operating power supply voltage range of 0.8 V to 3.6 V on the I2C-bus side
Allows bidirectional voltage-level translation and GPIO expansion between 0.8 V to
3.6 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V, 5.5 V Port P
Low standby current consumption: 2.0 A typical at 3.3 V VDD(P)
Schmitt trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
Vhys = 0.05 V (typical) at 0.8 V
Vhys = 0.18 V (typical) at 1.8 V
Vhys = 0.33 V (typical) at 3.3 V
5.5 V tolerant I/O ports and 3.6 V tolerant I2C-bus pins
Active LOW reset input (RESET)
Open-drain active LOW interrupt output (INT)
Internal power-on reset
Noise filter on SCL/SDA inputs
Latched outputs with 25 mA drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD 78, Class II
ESD protection exceeds JESD 22
2000 V Human-Body Model (A114-A)
1000 V Charged-Device Model (C101)
Packages offered: TSSOP32, HUQFN32
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Rev. 1 — 22 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
2.1 Agile I/O features
Output port configuration: bank selectable or pin selectable push-pull or open-drain
output stages
Interrupt status: read-only register identifies the source of an interrupt
Bit-wise I/O programming features:
Output drive strength: four programmable drive strengths to reduce rise and fall
times in low-capacitance applications
Input latch: Input Port register values changes are kept until the Input Port register
is read
Pull-up/pull-down enable: floating input or pull-up/pull-down resistor enable
Pull-up/pull-down selection: 100 k pull-up/pull-down resistor selection
Interrupt mask: mask prevents the generation of the interrupt when input changes
state to prevent spurious interrupts
2.2 Additional Agile I/O Plus features
Interrupt edge specification on a bit-by-bit basis
Interrupt individual clear without disturbing other events
Read all interrupt events without clear
Switch debounce hardware
General call software reset
I2C software Device ID function
3. Ordering information
Table 1.
Ordering information
Type number
Topside
marking
Package
Name
Description
Version
PCAL6524HE
L6524
HUQFN32
plastic thermal enhanced very thin quad flat package;
no leads; 32 terminals; body 5 5 0.56 mm
SOT1426-1
PCAL6524DR
PCAL6524
TSSOP32[1] plastic thin shrink small outline package; 32 leads;
body width 6.1 mm; lead pitch 0.65 mm
[1]
SOT487-1
Under development. Please contact your local NXP sales office for availability.
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
PCAL6524HE
PCAL6524HEHP
HUQFN32
Reel 13” Q2/T3
5000
*standard mark SMD
Tamb = 40 C to +85 C
PCAL6524HE
PCAL6524HEAZ
HUQFN32
Reel 7” Q2/T3
500
*standard mark SMD
Tamb = 40 C to +85 C
PCAL6524DR
PCAL6524DRJ
2500
TSSOP32[1] Reel 13” Q1/T1
*standard mark SMD
[1]
Minimum
order quantity
Temperature
Tamb = 40 C to +85 C
Under development. Please contact your local NXP sales office for availability.
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
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PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
4. Block diagram
PCAL6524
INT
INTERRUPT
LOGIC
LP FILTER
ADDR
SCL
SDA
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
INPUT
FILTER
I2C-BUS
CONTROL
VDD(I2C-bus)
VDD(P)
RESET
POWER-ON
RESET
SHIFT
REGISTER
24 BITS
I/O
PORT
write pulse
read pulse
I/O control
VSS
aaa-008797
All I/Os are set to inputs at reset.
Fig 1.
PCAL6524
Product data sheet
Block diagram (positive logic)
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PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
5. Pinning information
29 VSS
P0_0
5
28 P2_7
P0_1
6
27 P2_6
P0_0
1
24 P2_7
P0_2
7
26 P2_5
P0_1
2
23 P2_6
P0_3
8
25 P2_4
P0_2
3
22 P2_5
P0_4
9
24 P2_3
P0_3
4
P0_5 10
23 P2_2
P0_4
5
P0_6 11
22 P2_1
P0_5
6
19 P2_2
P0_7 12
21 P2_0
P0_6
7
18 P2_1
P1_0 13
20 P1_7
P0_7
8
17 P2_0
P1_1 14
19 P1_6
9
P1_2 15
18 P1_5
P1_3 16
17 P1_4
Pin configuration for TSSOP32
PCAL6524
Product data sheet
P1_7 16
P1_6 15
P1_5 14
P1_4 13
P1_3 12
P1_2 11
20 P2_3
aaa-008799
Transparent top view
aaa-008798
Fig 2.
21 P2_4
PCAL6524HE
P1_1 10
PCAL6524DR
terminal 1
index area
25 VSS
4
26 ADDR
30 ADDR
INT
27 VDD(P)
3
28 RESET
31 VDD(P)
VDD(I2C-bus)
29 SCL
32 RESET
2
30 SDA
1
32 INT
SCL
SDA
P1_0
31 VDD(I2C-bus)
5.1 Pinning
Fig 3.
Pin configuration for HUQFN32
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
5.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
TSSOP32 HUQFN32 Type
SCL
1
29
I
Serial clock line. Connect to VDD(I2C-bus) through a pull-up resistor.
SDA
2
30
I/O
Serial data line. Connect to VDD(I2C-bus) through a pull-up resistor.
VDD(I2C-bus)
3
31
power
supply
Supply voltage of I2C-bus. Connect directly to the VDD of the external
I2C-bus master. Provides voltage-level translation.
INT
4
32
O
Interrupt output. Connect to VDD(I2C-bus) or VDD(P) through a pull-up resistor.
P0_0[1]
5
1
I/O
Port 0 input/output 0.
P0_1[1]
6
2
I/O
Port 0 input/output 1.
P0_2[1]
7
3
I/O
Port 0 input/output 2.
P0_3[1]
8
4
I/O
Port 0 input/output 3.
P0_4[1]
9
5
I/O
Port 0 input/output 4.
P0_5[1]
10
6
I/O
Port 0 input/output 5.
P0_6[1]
11
7
I/O
Port 0 input/output 6.
P0_7[1]
12
8
I/O
Port 0 input/output 7.
P1_0[2]
13
9
I/O
Port 1 input/output 0.
P1_1[2]
14
10
I/O
Port 1 input/output 1.
P1_2[2]
15
11
I/O
Port 1 input/output 2.
P1_3[2]
16
12
I/O
Port 1 input/output 3.
P1_4[2]
17
13
I/O
Port 1 input/output 4.
P1_5[2]
18
14
I/O
Port 1 input/output 5.
P1_6[2]
19
15
I/O
Port 1 input/output 6.
P1_7[2]
20
16
I/O
Port 1 input/output 7.
P2_0[3]
21
17
I/O
Port 2 input/output 0.
P2_1[3]
22
18
I/O
Port 2 input/output 1.
P2_2[3]
23
19
I/O
Port 2 input/output 2.
P2_3[3]
24
20
I/O
Port 2 input/output 3.
P2_4[3]
25
21
I/O
Port 2 input/output 4.
P2_5[3]
26
22
I/O
Port 2 input/output 5.
P2_6[3]
27
23
I/O
Port 2 input/output 6.
P2_7[3]
28
24
I/O
Port 2 input/output 7.
VSS
29
25
ground Supply ground.
ADDR
30
26
I
Address input. Connect directly to VDD(I2C-bus), ground, SCL or SDA.
VDD(P)
31
27
power
supply
Supply voltage of PCAL6524 for Port P.
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Table 3.
Symbol
Pin description …continued
Pin
Description
TSSOP32 HUQFN32 Type
RESET
32
28
I
Active LOW reset input. Connect to VDD(I2C-bus) through a pull-up resistor if
no active connection is used.
[1]
Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-on, all I/Os are configured as inputs.
[2]
Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-on, all I/Os are configured as inputs.
[3]
Pins P2_0 to P2_7 correspond to bits P2.0 to P2.7. At power-on, all I/Os are configured as inputs.
6. Functional description
Refer to Figure 1 “Block diagram (positive logic)”.
6.1 Device address
Following a START condition, the bus master must send the target slave address followed
by a read (R/W = 1) or write (R/W = 0) operation bit. The slave address of the PCAL6524
is shown in Figure 4. Slave address pin ADDR chooses one of four slave addresses.
Table 4 shows all four slave addresses by connecting the ADDR pin to SCL, SDA, VSS, or
VDD.
Table 4.
ADDR
PCAL6524 address map
Device family high-order address bits
Variable portion
of address
Address
A6
A5
A4
A3
A2
A1
A0
SCL
0
1
0
0
0
0
0
40h
SDA
0
1
0
0
0
0
1
42h
VSS
0
1
0
0
0
1
0
44h
VDD
0
1
0
0
0
1
1
46h
The last bit of the first byte defines the reading from or writing to the PCAL6524. When set
to logic 1 a read is selected, while logic 0 selects a write operation.
slave address
0
1
0
0
fixed
0
A1
A0 R/W
programmable
aaa-011036
Fig 4.
PCAL6524
Product data sheet
PCAL6524 address
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
6.2 Interface definition
Table 5.
Interface definition
Byte
I2C-bus
Bit
7 (MSB)
6
5
4
3
2
1
0 (LSB)
L
H
L
L
L
A1
A0
R/W
slave address
I/O data bus
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
6.3 Software Reset Call, and device ID addresses
Two other different addresses can be sent to the device.
• General Call address: allows to reset the device through the I2C-bus upon reception
of the right I2C-bus sequence. See Section 6.3.1 “Software Reset” for more
information.
• Device ID address: allows to read ID information from the device (manufacturer, part
identification, revision). See Section 6.3.2 “Device ID (PCAL6524 ID field)” for more
information.
R/W
0
0
0
0
0
0
0
0
1
1
1
1
1
002aac115
Fig 5.
General Call address
0
0
R/W
002aac116
Fig 6.
Device ID address
6.3.1 Software Reset
The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up
state value through a specific formatted I2C-bus command. To be performed correctly, it
implies that the I2C-bus is functional and that there is no device hanging the bus.
The Software Reset sequence is defined as following:
1. A START command is sent by the I2C-bus master.
2. The reserved General Call I2C-bus address ‘0000 000’ with the R/W bit set to 0 (write)
is sent by the I2C-bus master.
3. The device acknowledges after seeing the General Call address ‘0000 0000’ (00h)
only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I2C-bus
master.
4. Once the General Call address has been sent and acknowledged, the master sends
1 byte. The value of the byte must be equal to 06h.
a. The device acknowledges this value only. If the byte is not equal to 06h, the device
does not acknowledge it.
If more than 1 byte of data is sent, the device does not acknowledge any more.
PCAL6524
Product data sheet
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PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
5. Once the right byte has been sent and correctly acknowledged, the master sends a
STOP command to end the Software Reset sequence: the device then resets to the
default value (power-up value) and is ready to be addressed again within the specified
bus free time. If the master sends a Repeated START instead, no reset is performed.
The I2C-bus master must interpret a non-acknowledge from the device (at any time) as a
‘Software Reset Abort’. The device does not initiate a reset of its registers.
The unique sequence that initiates a Software Reset is described in Figure 7.
SWRST Call I2C-bus address
S
0
0
0
0
0
0
START condition
0
SWRST data = 06h
0
A
0
0
R/W
acknowledge
from slave(s)
0
0
0
1
1
0
A
P
acknowledge
from slave(s)
PCAL6524 is reset.
Registers are set to default power-up values.
aaa-008801
Fig 7.
Software Reset sequence
6.3.2 Device ID (PCAL6524 ID field)
The Device ID field is a 3-byte read-only (24 bits) word giving the following information:
• 12 bits with the manufacturer name, unique per manufacturer (for example, NXP).
• 9 bits with the part identification, assigned by manufacturer.
• 3 bits with the die revision, assigned by manufacturer (for example, Rev X).
The Device ID is read-only, hardwired in the device and can be accessed as follows:
1. START command
2. The master sends the Reserved Device ID I2C-bus address followed by the R/W bit
set to 0 (write): ‘1111 1000’.
3. The master sends the I2C-bus slave address of the slave device it needs to identify.
The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one
that has the I2C-bus slave address).
4. The master sends a Re-START command.
Remark: A STOP command followed by a START command will reset the slave state
machine and the Device ID read cannot be performed. Also, a STOP command or a
Re-START command followed by an access to another slave device will reset the
slave state machine and the Device ID Read cannot be performed.
5. The master sends the Reserved Device ID I2C-bus address followed by the R/W bit
set to 1 (read): ‘1111 1001’.
6. The Device ID Read can be done, starting with the 12 manufacturer bits (first byte +
4 MSB of the second byte), followed by the 9 part identification bits (4 LSBs of the
second byte + 5 MSBs of the third byte), and then the 3 die revision bits (3 LSBs of
the third byte).
7. The master ends the reading sequence by NACKing the last byte, thus resetting the
slave device state machine and allowing the master to send the STOP command.
PCAL6524
Product data sheet
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PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Remark: The reading of the Device ID can be stopped anytime by sending a NACK
command.
If the master continues to ACK the bytes after the third byte, the slave rolls back to the
first byte and keeps sending the Device ID sequence until a NACK has been
detected.
For the PCAL6524, the Device ID is as shown in Figure 8.
manufacturer
0
0
0
part identification
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
revision
0
aaa-008802
Fig 8.
PCAL6524 Device ID field
acknowledge from
one or several slaves
Device ID address
S 1
1
1
1
1
0
START condition
0
I2C-bus slave address
of the device to be identified
0 A 0
1
0
0
R/W
acknowledge from
slave to be identified
Device ID address
0 A1 A0 0 A Sr 1
don’t care
acknowledge
from master
acknowledge from
slave to be identified
1
1
1
repeated START
condition
acknowledge
from master
1
0
0
1 A
R/W
no acknowledge
from master
M M
A M3 M2 M1 M0 P8 P7 P6 P5 A P4 P3 P2 P1 P0 R2 R1 R0 A P
11 10 M9 M8 M7 M6 M5 M4
STOP condition
manufacturer name = 000000000000
part identification = 100000110
revision = 000
aaa-008803
If more than 3 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the
master generates a ‘no acknowledge’.
Fig 9.
Device ID field reading
PCAL6524
Product data sheet
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PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
6.4 Pointer register and command byte
Following the successful acknowledgement of the slave address byte, the bus master
sends a command byte, which is write only and stored in the pointer register in the
PCAL6524. The lowest 7 bits (B[6:0] in Table 6) are used as a pointer to determine which
register is accessed and the highest bit is used as Auto-Increment (AI) as shown in
Figure 10. At power-up, hardware or software reset, the pointer register defaults to 00h,
with the AI bit set to ‘0’ and the lowest seven bits set to ‘000 0000’.
When the Auto-Increment bit is set (AI = 1), the seven low-order bits of the pointer register
are automatically incremented after a read or write until a STOP condition is encountered.
This allows the user to program the registers sequentially without modifying the pointer
register. The contents of these bits will roll over to ‘000 0000’ after the last register
(address = 76h) is accessed. Unimplemented register addresses (reserved registers) are
skipped. If more than 52 bytes are written, the address will loop back to the register which
is indicated by the seven low-order bits in the pointer register, and previously-written data
will be overwritten. A STOP condition will keep the pointer register value in the last read or
write location.
When the Auto-Increment bit is cleared (AI = 0), the 2 least significant bits are
automatically incremented after a read or write for 3-register group which allows the user
to program each of the 3-register group sequentially. If more than 3 bytes of data are read
or written when AI is 0, previous data in the selected registers will be overwritten. For
example: if input port 1 is read first, the next 2nd byte will be input port 2, and next 3nd
byte will be input port 0, there is no limit on the number of data bytes for this read
operation. There are two special 6-register groups: output drive strength (40h~45h) and
interrupt edge (60h~65h) registers will allow user to program each of the 6-register group
sequentially. Only Output port configuration register location (5Ch) remains in the same
location after a successive read or write.
AI
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
default value at power-up
or HW/SW reset
aaa-009085
AI = Auto-Increment
Fig 10. Pointer register bits
PCAL6524
Product data sheet
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Table 6.
Command byte
Pointer register bits
B6 B5
B4
B3
B2
B1
Command
Register
byte
B0
(hexadecimal)
Protocol
Power-up
default
0
0
0
0
0
0
0
00h
Input port 0
read byte
xxxx xxxx[1]
0
0
0
0
0
0
1
01h
Input port 1
read byte
xxxx xxxx[1]
0
0
0
0
0
1
0
02h
Input port 2
read byte
xxxx xxxx[1]
0
0
0
0
0
1
1
03h
reserved[3]
reserved
reserved
0
0
0
0
1
0
0
04h
Output port 0
read/write byte
1111 1111
0
0
0
0
1
0
1
05h
Output port 1
read/write byte
1111 1111
0
0
0
0
1
1
0
06h
Output port 2
read/write byte
1111 1111
0
0
0
0
1
1
1
07h
reserved[3]
reserved
reserved
0
0
0
1
0
0
0
08h
Polarity Inversion port 0
read/write byte
0000 0000
0
0
0
1
0
0
1
09h
Polarity Inversion port 1
read/write byte
0000 0000
0
0
0
1
0
1
0
0Ah
Polarity Inversion port 2
read/write byte
0000 0000
0
0
0
1
0
1
1
0Bh
reserved[3]
reserved
reserved
0
0
0
1
1
0
0
0Ch
Configuration port 0
read/write byte
1111 1111
0
0
0
1
1
0
1
0Dh
Configuration port 1
read/write byte
1111 1111
0
0
0
1
1
1
0
0Eh
Configuration port 2
read/write byte
1111 1111
reserved[3]
-
-
-
-
-
-
-
0Fh to 3Fh
reserved
reserved
1
0
0
0
0
0
0
40h
Output drive strength register port 0A
read/write byte
1111 1111
1
0
0
0
0
0
1
41h
Output drive strength register port 0B
read/write byte
1111 1111
1
0
0
0
0
1
0
42h
Output drive strength register port 1A
read/write byte
1111 1111
1
0
0
0
0
1
1
43h
Output drive strength register port 1B
read/write byte
1111 1111
1
0
0
0
1
0
0
44h
Output drive strength register port 2A
read/write byte
1111 1111
1
0
0
0
1
0
1
45h
Output drive strength register port 2B
read/write byte
1111 1111
46h
reserved[3]
reserved
reserved
1
0
0
0
1
1
0
1
0
0
0
1
1
1
47h
reserved[3]
reserved
reserved
1
0
0
1
0
0
0
48h
Input latch register port 0
read/write byte
0000 0000
1
0
0
1
0
0
1
49h
Input latch register port 1
read/write byte
0000 0000
1
0
0
1
0
1
0
4Ah
Input latch register port 2
read/write byte
0000 0000
1
0
0
1
0
1
1
4Bh
reserved[3]
reserved
reserved
1
0
0
1
1
0
0
4Ch
Pull-up/pull-down enable register port
0
read/write byte
0000 0000
1
0
0
1
1
0
1
4Dh
Pull-up/pull-down enable register port
1
read/write byte
0000 0000
1
0
0
1
1
1
0
4Eh
Pull-up/pull-down enable register port
2
read/write byte
0000 0000
1
0
0
1
1
1
1
4Fh
reserved[3]
reserved
reserved
1
0
1
0
0
0
0
50h
Pull-up/pull-down selection register
port 0
read/write byte
1111 1111
1
0
1
0
0
0
1
51h
Pull-up/pull-down selection register
port 1
read/write byte
1111 1111
1
0
1
0
0
1
0
52h
Pull-up/pull-down selection register
port 2
read/write byte
1111 1111
PCAL6524
Product data sheet
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Table 6.
Command byte …continued
Pointer register bits
B6 B5
B4
B3
B2
B1
B0
1
0
0
1
1
Command
Register
byte
(hexadecimal)
53h
reserved[3]
Protocol
Power-up
default
reserved
reserved
1
0
1
0
1
0
1
0
0
54h
Interrupt mask register port 0
read/write byte
1111 1111
1
0
1
0
1
0
1
55h
Interrupt mask register port 1
read/write byte
1111 1111
1
0
1
0
1
1
0
56h
Interrupt mask register port 2
read/write byte
1111 1111
reserved
reserved
1
0
1
0
1
1
1
57h
reserved[3]
1
0
1
1
0
0
0
58h
Interrupt status register port 0
read byte
0000 0000
1
0
1
1
0
0
1
59h
Interrupt status register port 1
read byte
0000 0000
1
0
1
1
0
1
0
5Ah
Interrupt status register port 2
read byte
0000 0000
1
5Bh
reserved[3]
reserved
reserved
1
0
1
1
0
1
1
0
1
1
1
0
0
5Ch[2]
Output port configuration register
read/write byte
0000 0000
1
0
1
1
1
0
1
5Dh
reserved[3]
reserved
reserved
5Eh
reserved[3]
reserved
reserved
reserved
reserved
1
0
1
1
1
1
0
1
0
1
1
1
1
1
5Fh
reserved[3]
1
1
0
0
0
0
0
60h
Interrupt edge register port 0A
read/write byte
0000 0000
1
1
0
0
0
0
1
61h
Interrupt edge register port 0B
read/write byte
0000 0000
1
1
0
0
0
1
0
62h
Interrupt edge register port 1A
read/write byte
0000 0000
1
1
0
0
0
1
1
63h
Interrupt edge register port 1B
read/write byte
0000 0000
1
1
0
0
1
0
0
64h
Interrupt edge register port 2A
read/write byte
0000 0000
1
1
0
0
1
0
1
65h
Interrupt edge register port 2B
read/write byte
0000 0000
66h
reserved[3]
reserved
reserved
reserved
reserved
1
1
0
0
1
1
0
1
1
0
0
1
1
1
67h
reserved[3]
1
1
0
1
0
0
0
68h
Interrupt clear register port 0
write byte
0000 0000
1
1
0
1
0
0
1
69h
Interrupt clear register port 1
write byte
0000 0000
1
1
0
1
0
1
0
6Ah
Interrupt clear register port 2
write byte
0000 0000
reserved
reserved
1
1
0
1
0
1
1
6Bh
reserved[3]
1
1
0
1
1
0
0
6Ch
Input status port 0
read byte
xxxx xxxx[1]
1
1
0
1
1
0
1
6Dh
Input status port 1
read byte
xxxx xxxx[1]
1
1
0
1
1
1
0
6Eh
Input status port 2
read byte
xxxx xxxx[1]
1
1
0
1
1
1
1
6Fh
reserved[3]
reserved
reserved
1
1
1
0
0
0
0
70h
Individual pin output port 0
configuration register
read/write byte
0000 0000
1
1
1
0
0
0
1
71h
Individual pin output port 1
configuration register
read/write byte
0000 0000
1
1
1
0
0
1
0
72h
Individual pin output port 2
configuration register
read/write byte
0000 0000
1
1
1
0
0
1
1
73h
reserved[3]
reserved
reserved
1
1
1
0
1
0
0
74h
Switch debounce enable 0
read/write byte
0000 0000
1
1
1
0
1
0
1
75h
Switch debounce enable 1
read/write byte
0000 0000
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
13 of 68
PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Table 6.
Command byte …continued
Pointer register bits
B6 B5
1
1
-
-
B4
B3
B2
B1
B0
1
0
1
1
0
-
-
-
-
-
Command
Register
byte
(hexadecimal)
76h
77h to 7Fh
Protocol
Power-up
default
Switch debounce count
read/write byte
0000 0000
reserved[3]
reserved
reserved
[1]
Undefined.
[2]
Successive read and write accesses to remain at this register address.
[3]
These registers marked “reserved” should not be written, and the master will not be acknowledged when accessed.
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
6.5 Register descriptions
6.5.1 Input port registers (00h, 01h, 02h)
The Input port registers (registers 00h, 01h, 02h) reflect the incoming logic levels of the
pins. The Input port registers are read only; writes to these registers have no effect and
the transaction will be acknowledged (ACK). The default value ‘X’ is determined by the
externally applied logic level. If a pin is configured as an output (registers 04h, 05h, 06h),
the port value is equal to the actual voltage level on that pin. If the output is configured as
open-drain (register 5Ch and registers 70h, 71h, 72h), the input port value is forced to 0.
An Input port register group read operation is performed as described in Section 7.2.
After reading input port registers, all interrupts will be cleared.
Table 7.
Bit
Input port 0 register (address 00h)
7
6
5
4
3
2
1
0
Symbol
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
Default
X
X
X
X
X
X
X
X
Table 8.
Bit
Input port 1 register (address 01h)
7
6
5
4
3
2
1
0
Symbol
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
Default
X
X
X
X
X
X
X
X
Table 9.
Bit
Input port 2 register (address 02h)
7
6
5
4
3
2
1
0
Symbol
I2.7
I2.6
I2.5
I2.4
I2.3
I2.2
I2.1
I2.0
Default
X
X
X
X
X
X
X
X
6.5.2 Output port registers (04h, 05h, 06h)
The Output port registers (registers 04h, 05h, 06h) show the outgoing logic levels of the
pins defined as outputs by the Configuration register. Bit values in these registers have no
effect on pins defined as inputs. In turn, reads from these registers reflect the value that
was written to these registers, not the actual pin value. A register group write is described
in Section 7.1 and a register group read is described in Section 7.2.
Table 10.
Bit
7
6
5
4
3
2
1
0
Symbol
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
Default
1
1
1
1
1
1
1
1
Table 11.
Bit
PCAL6524
Product data sheet
Output port 0 register (address 04h)
Output port 1 register (address 05h)
7
6
5
4
3
2
1
0
Symbol
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
Default
1
1
1
1
1
1
1
1
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Table 12.
Bit
Output port 2 register (address 06h)
7
6
5
4
3
2
1
0
Symbol
O2.7
O2.6
O2.5
O2.4
O2.3
O2.2
O2.1
O2.0
Default
1
1
1
1
1
1
1
1
6.5.3 Polarity inversion registers (08h, 09h, 0Ah)
The Polarity inversion registers (registers 08h, 09h, 0Ah) allow polarity inversion of pins
defined as inputs by the Configuration register. If a bit in these registers is set (written with
‘1’), the corresponding port pin’s polarity is inverted in the input register. If a bit in this
register is cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A
register group write is described in Section 7.1 and a register group read is described in
Section 7.2.
Table 13.
Bit
Polarity inversion port 0 register (address 08h)
7
6
5
4
3
2
1
0
Symbol
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
Default
0
0
0
0
0
0
0
0
Table 14.
Bit
Polarity inversion port 1 register (address 09h)
7
6
5
4
3
2
1
0
Symbol
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
Default
0
0
0
0
0
0
0
0
Table 15.
Bit
Polarity inversion port 2 register (address 0Ah)
7
6
5
4
3
2
1
0
Symbol
N2.7
N2.6
N2.5
N2.4
N2.3
N2.2
N2.1
N2.0
Default
0
0
0
0
0
0
0
0
6.5.4 Configuration registers (0Ch, 0Dh, 0Eh)
The Configuration registers (registers 0Ch, 0Dh, 0Eh) configure the direction of the I/O
pins. If a bit in these registers is set to 1, the corresponding port pin is enabled as a
high-impedance input. If a bit in these registers is cleared to 0, the corresponding port pin
is enabled as an output. A register group write is described in Section 7.1 and a register
group read is described in Section 7.2.
Table 16.
Bit
7
6
5
4
3
2
1
0
Symbol
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
Default
1
1
1
1
1
1
1
1
Table 17.
Bit
PCAL6524
Product data sheet
Configuration port 0 register (address 0Ch)
Configuration port 1 register (address 0Dh)
7
6
5
4
3
2
1
0
Symbol
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
Default
1
1
1
1
1
1
1
1
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Table 18.
Bit
Configuration port 2 register (address 0Eh)
7
6
5
4
3
2
1
0
Symbol
C2.7
C2.6
C2.5
C2.4
C2.3
C2.2
C2.1
C2.0
Default
1
1
1
1
1
1
1
1
6.5.5 Output drive strength registers (40h, 41h, 42h, 43h, 44h, 45h)
The Output drive strength registers control the output drive level of the GPIO. Each GPIO
can be configured independently to a certain output current level by two register control
bits. For example Port 0.7 is controlled by register 41h CC0.7 (bits [7:6]), Port 0.6 is
controlled by register 41h CC0.6 (bits [5:4]). The output drive level of the GPIO is
programmed 00b = 0.25, 01b = 0.5, 10b = 0.75 or 11b = 1 of the drive capability of
the I/O. See Section 8.1 “Output drive strength control” for more details. A register group
write operation is described in Section 7.1. A register group read operation is described in
Section 7.2.
Table 19.
Bit
Current control port 0A register (address 40h)
7
Symbol
Default
Table 20.
Bit
Table 21.
Bit
1
Table 22.
Bit
Table 23.
Bit
Table 24.
Bit
PCAL6524
Product data sheet
6
1
2
1
CC0.1
1
1
0
CC0.0
1
1
1
5
4
3
2
1
0
CC0.6
1
1
CC0.5
1
1
CC0.4
1
1
1
2
1
0
Current control port 1A register (address 42h)
7
6
5
CC1.3
1
4
3
CC1.2
1
1
CC1.1
1
1
CC1.0
1
1
1
2
1
0
Current control port 1B register (address 43h)
7
6
5
CC1.7
1
4
3
CC1.6
1
1
CC1.5
1
1
CC1.4
1
1
1
2
1
0
Current control port 2A register (address 44h)
7
6
5
CC2.3
1
4
3
CC2.2
1
1
CC2.1
1
1
CC2.0
1
1
1
2
1
0
Current control port 2B register (address 45h)
7
Symbol
Default
1
CC0.7
Symbol
Default
3
CC0.2
1
7
Symbol
Default
4
Current control port 0B register (address 41h)
Symbol
Default
5
CC0.3
Symbol
Default
6
6
5
CC2.7
1
4
3
CC2.6
1
1
CC2.5
1
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 September 2015
1
CC2.4
1
1
1
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
6.5.6 Input latch registers (48h, 49h, 4Ah)
The input latch registers (registers 48h, 49h, 4Ah) enable and disable the input latch of the
I/O pins. These registers are effective only when the pin is configured as an input port.
When an input latch register bit is 0, the corresponding input pin state is not latched. A
state change in the corresponding input pin generates an interrupt. A read of the input
register clears the interrupt. If the input goes back to its initial logic state before the input
port register is read, then the interrupt is cleared.
When an input latch register bit is 1, the corresponding input pin state is latched. A change
of state of the input generates an interrupt and the input logic value is loaded into the
corresponding bit of the input port register (registers 0, 1 and 2). A read of the input port
register clears the interrupt. If the input pin returns to its initial logic state before the input
port register is read, then the interrupt is not cleared and the corresponding bit of the input
port register keeps the logic value that initiated the interrupt. See Figure 20.
For example, if the P0_4 input was as logic 0 and the input goes to logic 1 then back to
logic 0, the input port 0 register will capture this change and an interrupt is generated (if
unmasked). When the read is performed on the input port 0 register, the interrupt is
cleared, assuming there were no additional input(s) that have changed, and bit 4 of the
input port 0 register will read ‘1’. The next read of the input port register bit 4 register
should now read ‘0’.
An interrupt remains active when a non-latched input simultaneously switches state with a
latched input and then returns to its original state. A read of the input register reflects only
the change of state of the latched input and also clears the interrupt. The interrupt is
cleared if the input latch register changes from latched to non-latched configuration and
I/O pin returns to its original state.
If the input pin is changed from latched to non-latched input, a read from the input port
register reflects the current port logic level. If the input pin is changed from non-latched to
latched input, the read from the input register reflects the latched logic level. A register
group write operation is described in Section 7.1. A register group read operation is
described in Section 7.2.
Table 25.
Bit
7
6
5
4
3
2
1
0
Symbol
L0.7
L0.6
L0.5
L0.4
L0.3
L0.2
L0.1
L0.0
Default
0
0
0
0
0
0
0
0
Table 26.
Bit
6
5
4
3
2
1
0
Symbol
L1.7
L1.6
L1.5
L1.4
L1.3
L1.2
L1.1
L1.0
Default
0
0
0
0
0
0
0
0
Bit
Product data sheet
Input latch port 1 register (address 49h)
7
Table 27.
PCAL6524
Input latch port 0 register (address 48h)
Input latch port 2 register (address 4Ah)
7
6
5
4
3
2
1
0
Symbol
L2.7
L2.6
L2.5
L2.4
L2.3
L2.2
L2.1
L2.0
Default
0
0
0
0
0
0
0
0
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Rev. 1 — 22 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
18 of 68
PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
6.5.7 Pull-up/pull-down enable registers (4Ch, 4Dh, 4Eh)
The pull-up and pull-down enable registers allow the user to enable or disable
pull-up/pull-down resistors on the I/O pins. Setting the bit to logic 1 enables the selection
of pull-up/pull-down resistors. Setting the bit to logic 0 disconnects the pull-up/pull-down
resistors from the I/O pins. Also, the resistors will be disconnected when the outputs are
configured as open-drain outputs (see Section 6.5.11 and Section 6.5.15). Use the
pull-up/pull-down registers to select either a pull-up or pull-down resistor. A register group
write operation is described in Section 7.1. A register group read operation is described in
Section 7.2.
Table 28.
Bit
Pull-up/pull-down enable port 0 register (address 4Ch)
7
6
5
4
3
2
1
0
Symbol
PE0.7
PE0.6
PE0.5
PE0.4
PE0.3
PE0.2
PE0.1
PE0.0
Default
0
0
0
0
0
0
0
0
Table 29.
Bit
Pull-up/pull-down enable port 1 register (address 4Dh)
7
6
5
4
3
2
1
0
Symbol
PE1.7
PE1.6
PE1.5
PE1.4
PE1.3
PE1.2
PE1.1
PE1.0
Default
0
0
0
0
0
0
0
0
Table 30.
Bit
Pull-up/pull-down enable port 2 register (address 4Eh)
7
6
5
4
3
2
1
0
Symbol
PE2.7
PE2.6
PE2.5
PE2.4
PE2.3
PE2.2
PE2.1
PE2.0
Default
0
0
0
0
0
0
0
0
6.5.8 Pull-up/pull-down selection registers (50h, 51h, 52h)
The I/O port can be configured to have pull-up or pull-down resistor by programming the
pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k pull-up
resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that
I/O pin. If the pull-up/down feature is disconnected, writing to this register will have no
effect on I/O pin. Typical value is 100 k with minimum of 50 k and maximum of 150 k.
A register group write operation is described in Section 7.1. A register group read
operation is described in Section 7.2.
Table 31.
Bit
7
6
5
4
3
2
1
0
Symbol
PUD0.7
PUD0.6
PUD0.5
PUD0.4
PUD0.3
PUD0.2
PUD0.1
PUD0.0
Default
1
1
1
1
1
1
1
1
Table 32.
Bit
PCAL6524
Product data sheet
Pull-up/pull-down selection port 0 register (address 50h)
Pull-up/pull-down selection port 1 register (address 51h)
7
6
5
4
3
2
1
0
Symbol
PUD1.7
PUD1.6
PUD1.5
PUD1.4
PUD1.3
PUD1.2
PUD1.1
PUD1.0
Default
1
1
1
1
1
1
1
1
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Table 33.
Bit
Pull-up/pull-down selection port 2 register (address 52h)
7
6
5
4
3
2
1
0
Symbol
PUD2.7
PUD2.6
PUD2.5
PUD2.4
PUD2.3
PUD2.2
PUD2.1
PUD2.0
Default
1
1
1
1
1
1
1
1
6.5.9 Interrupt mask registers (54h, 55h, 56h)
Interrupt mask registers are set to logic 1 upon power-on, disabling interrupts during
system start-up. Interrupts may be enabled by setting corresponding mask bits to logic 0.
If an input changes state and the corresponding bit in the Interrupt mask register is set
to 1, the interrupt is masked and the interrupt pin will not be asserted. If the corresponding
bit in the Interrupt mask register is set to 0, the interrupt pin will be asserted.
When an input changes state and the resulting interrupt is masked (interrupt mask bit
is 1), setting the input mask register bit to 0 will cause the interrupt pin to be asserted. If
the interrupt mask bit of an input that is currently the source of an interrupt is set to 1, the
interrupt pin will be de-asserted. A register group write operation is described in
Section 7.1. A register group read operation is described in Section 7.2.
Table 34.
Bit
Interrupt mask port 0 register (address 54h) bit description
7
6
5
4
3
2
1
0
Symbol
M0.7
M0.6
M0.5
M0.4
M0.3
M0.2
M0.1
M0.0
Default
1
1
1
1
1
1
1
1
Table 35.
Bit
Interrupt mask port 1 register (address 55h) bit description
7
6
5
4
3
2
1
0
Symbol
M1.7
M1.6
M1.5
M1.4
M1.3
M1.2
M1.1
M1.0
Default
1
1
1
1
1
1
1
1
Table 36.
Bit
Interrupt mask port 2 register (address 56h) bit description
7
6
5
4
3
2
1
0
Symbol
M2.7
M2.6
M2.5
M2.4
M2.3
M2.2
M2.1
M2.0
Default
1
1
1
1
1
1
1
1
6.5.10 Interrupt status registers (58h, 59h, 5Ah)
The read-only interrupt status registers are used to identify the source of an interrupt.
When read, a logic 1 indicates that the corresponding input pin was the source of the
interrupt. A logic 0 indicates that the input pin is not the source of an interrupt.
When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt
status bit will return logic 0. A register group read operation is described in Section 7.2.
Table 37.
Bit
PCAL6524
Product data sheet
Interrupt status port 0 register (address 58h) bit description
7
6
5
4
3
2
1
0
Symbol
S0.7
S0.6
S0.5
S0.4
S0.3
S0.2
S0.1
S0.0
Default
0
0
0
0
0
0
0
0
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NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Table 38.
Bit
Interrupt status port 1 register (address 59h) bit description
7
6
5
4
3
2
1
0
Symbol
S1.7
S1.6
S1.5
S1.4
S1.3
S1.2
S1.1
S1.0
Default
0
0
0
0
0
0
0
0
Table 39.
Bit
Interrupt status port 2 register (address 5Ah) bit description
7
6
5
4
3
2
1
0
Symbol
S2.7
S2.6
S2.5
S2.4
S2.3
S2.2
S2.1
S2.0
Default
0
0
0
0
0
0
0
0
6.5.11 Output port configuration register (5Ch)
The output port configuration register selects port-wise push-pull or open-drain I/O stage.
A logic 0 configures the I/O as push-pull (Q1 and Q2 are active, see Figure 11). A logic 1
configures the I/O as open-drain (Q1 is disabled, Q2 is active) and the recommended
command sequence is to program this register (5Ch) before the Configuration register
(0Ch, 0Dh, 0Eh) sets the port pins as outputs.
ODEN0 configures Port 0_x, ODEN1 configures Port 1_x, and ODEN2 configures
Port 2_x.
Individual pins may be programmed as open-drain or push-pull by programming Individual
Pin Output Configuration registers (70h, 71h, 72h). See Section 6.5.15 for more
information.
A register group read or write operation is not allowed on this register. Successive read or
write accesses will remain at this register address.
Table 40.
Bit
Output port configuration register (address 5Ch)
7
6
Symbol
Default
5
4
3
reserved
0
0
0
0
0
2
1
0
ODEN2
ODEN1
ODEN0
0
0
0
6.5.12 Interrupt edge registers (60h, 61h, 62h and 63h, 64h, 65h)
The interrupt edge registers determine what action on an input pin will cause an interrupt
along with the Interrupt Mask registers (54h, 55h and 56h). If the Interrupt is enabled (set
‘0’ in the Mask register) and the action at the corresponding pin matches the required
activity, the INT output will become active. The default value for each pin is 00b or level
triggered, meaning a level change on the pin will cause an interrupt event. A level
triggered action means a change in logic state (HIGH-to-LOW or LOW-to-HIGH), since
the last read of the Input port (00h, 01h or 02h) which can be latched with a corresponding
‘1’ set in the Input Latch register (48h, 49h, 4Ah). If the Interrupt edge register entry is set
to 11b, any edge, positive- or negative-going, causes an interrupt event. If an entry is 01b,
only a positive-going edge will cause an interrupt event, while a 10b will require a
negative-going edge to cause an interrupt event. These edge interrupt events are latched,
regardless of the status of the Input Latch register (48h, 49h, 4Ah). These edged
interrupts can be cleared in a number of ways: Reading input port registers (00h, 01h,
02h); setting the Interrupt Mask register (54h, 55h, 56h) to 1 (masked); setting the
Interrupt Clear register (68h, 69h, 6Ah) to 1 (this is a write-only register); resetting the
Interrupt Edge register (60h to 65h) back to 0. A register group write operation is
described in Section 7.1. A register group read operation is described in Section 7.2.
PCAL6524
Product data sheet
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Table 41.
Bit
Interrupt edge port 0A register (address 60h)
7
Symbol
Default
Table 42.
Bit
Table 43.
Bit
Table 44.
Bit
Table 45.
Bit
Table 46.
Bit
Table 47.
PCAL6524
Product data sheet
0
6
2
1
IE0.1
0
5
IE0.7
0
4
3
IE0.6
0
0
IE0.0
0
0
0
2
1
0
0
0
IE0.5
0
0
IE0.4
0
0
0
2
1
0
Interrupt edge port 1A register (address 62h)
7
6
5
IE1.3
4
3
IE1.2
0
0
0
IE1.1
0
0
IE1.0
0
0
0
2
1
0
Interrupt edge port 1B register (address 63h)
7
6
5
IE1.7
4
3
IE1.6
0
0
0
IE1.5
0
0
IE1.4
0
0
0
2
1
0
Interrupt edge port 2A register (address 64h)
7
6
5
IE2.3
4
3
IE2.2
0
0
0
IE2.1
0
0
IE2.0
0
0
0
2
1
0
Interrupt edge port 2B register (address 65h)
7
Symbol
Default
0
7
Symbol
Default
3
Interrupt edge port 0B register (address 61h)
Symbol
Default
4
IE0.2
0
Symbol
Default
5
IE0.3
Symbol
Default
6
6
5
IE2.7
4
3
IE2.6
0
0
0
IE2.5
0
0
IE2.4
0
0
0
Interrupt edge bits (IEx.x)
Bit 1
Bit 0
Description
0
0
level-triggered interrupt
0
1
positive-going (rising) edge triggered interrupt
1
0
negative-going (falling) edge triggered interrupt
1
1
any edge (positive or negative-going) triggered
interrupt
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
6.5.13 Interrupt clear registers (68h, 69h, 6Ah)
The write-only interrupt clear registers clear individual interrupt sources (status bit).
Setting an individual bit or any combination of bits to logic 1 will reset the corresponding
interrupt source, so if that source was the only event causing an interrupt, the INT will be
cleared. After writing a logic 1 the bit returns to logic 0. A register group write operation is
described in Section 7.1.
Table 48.
Bit
Interrupt clear port 0 register (address 68h) bit description
7
6
5
4
3
2
1
0
Symbol
IC0.7
IC0.6
IC0.5
IC0.4
IC0.3
IC0.2
IC0.1
IC0.0
Default
0
0
0
0
0
0
0
0
Table 49.
Bit
Interrupt clear port 1 register (address 69h) bit description
7
6
5
4
3
2
1
0
Symbol
IC1.7
IC1.6
IC1.5
IC1.4
IC1.3
IC1.2
IC1.1
IC1.0
Default
0
0
0
0
0
0
0
0
Table 50.
Bit
Interrupt clear port 2 register (address 6Ah) bit description
7
6
5
4
3
2
1
0
Symbol
IC2.7
IC2.6
IC2.5
IC2.4
IC2.3
IC2.2
IC2.1
IC2.0
Default
0
0
0
0
0
0
0
0
6.5.14 Input status registers (6Ch, 6Dh, 6Eh)
The read-only input status registers function exactly like Input Port 0, 1 and 2 (00h, 01h,
02h) without resetting the interrupt logic. This allows inspection of the actual state of the
input pins without upsetting internal logic. If the pin is configured as an input, the port read
is unaffected by input latch logic or other features, the state of the register is simply a
reflection of the current state of the input pins. If a pin is configured as an output by the
Configuration register (0Ch, 0Dh, 0Eh), and is also configured as open-drain (register 5Ch
and 70h, 71h, 72h), the read for that pin will always return 0, otherwise that state of that
pin is returned. A register group read operation is described in Section 7.2.
Table 51.
Bit
7
6
5
4
3
2
1
0
Symbol
II0.7
II0.6
II0.5
II0.4
II0.3
II0.2
II0.1
II0.0
Default
X
X
X
X
X
X
X
X
Table 52.
Bit
6
5
4
3
2
1
0
Symbol
II1.7
II1.6
II1.5
II1.4
II1.3
II1.2
II1.1
II1.0
Default
X
X
X
X
X
X
X
X
Bit
Product data sheet
Input status port 1 register (address 6Dh) bit description
7
Table 53.
PCAL6524
Input status port 0 register (address 6Ch) bit description
Input status port 2 register (address 6Eh) bit description
7
6
5
4
3
2
1
0
Symbol
II2.7
II2.6
II2.5
II2.4
II2.3
II2.2
II2.1
II2.0
Default
X
X
X
X
X
X
X
X
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
6.5.15 Individual pin output configuration registers (70h, 71h, 72h)
The individual pin output configuration registers modify output configuration (push-pull or
open-drain) set by the Output Port Configuration register (5Ch).
If the ODENx bit is set at logic 0 (push-pull), any bit set to logic 1 in the IOCRx register will
reverse the output state of that pin only to open-drain. When ODENx bit is set at
logic 1 (open-drain), a logic 1 in IOCRx will set that pin to push-pull.
The recommended command sequence to program the output pin is to program ODENx
(5Ch), the IOCRx, and finally the Configuration register (0Ch, 0Dh, 0Eh) to set the pins as
outputs. A register group write operation is described in Section 7.1. A register group read
operation is described in Section 7.2.
Table 54.
Bit
Symbol
Default
Table 55.
Bit
Symbol
Default
Table 56.
Bit
Symbol
Default
PCAL6524
Product data sheet
Individual pin output configuration register 0 (address 70h) bit description
7
6
5
4
3
2
1
0
IOCR0.7 IOCR0.6 IOCR0.5 IOCR0.4 IOCR0.3 IOCR0.2 IOCR0.1 IOCR0.0
0
0
0
0
0
0
0
0
Individual pin output configuration register 1 (address 71h) bit description
7
6
5
4
3
2
1
0
IOCR1.7 IOCR1.6 IOCR1.5 IOCR1.4 IOCR1.3 IOCR1.2 IOCR1.1 IOCR1.0
0
0
0
0
0
0
0
0
Individual pin output configuration register 2 (address 72h) bit description
7
6
5
4
3
2
1
0
IOCR2.7 IOCR2.6 IOCR2.5 IOCR2.4 IOCR2.3 IOCR2.2 IOCR2.1 IOCR2.0
0
0
0
0
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0
0
0
0
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NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
6.5.16 Switch debounce enable registers (74h, 75h)
The switch debounce enable registers enable the switch debounce function for Port 0 and
Port 1 pins. If a pin on Port 0 or Port 1 is designated as an input, a logic 1 in the Switch
debounce enable register will connect debounce logic to that pin. If a pin is assigned as an
output (via Configuration Port 0 or Port 1 register) the debounce logic is not connected to
that pin and it will function as a normal output. The switch debounce logic requires an
oscillator time base input and if this function is used, P0_0 is designated as the oscillator
input. If P0_0 is not configured as input and if SD0.0 is not set to logic 1, then switch
debounce logic is not connected to any pin. See Section 6.10 “Switch debounce circuitry”
for additional information about Switch debounce logic functionality.
Table 57.
Bit
Switch debounce enable Port 0 register (address 74h) bit description
7
6
5
4
3
2
1
0
Symbol
SD0.7
SD0.6
SD0.5
SD0.4
SD0.3
SD0.2
SD0.1
SD0.0
Default
0
0
0
0
0
0
0
0
Table 58.
Bit
Switch debounce enable Port 1 register (address 75h) bit description
7
6
5
4
3
2
1
0
Symbol
SD1.7
SD1.6
SD1.5
SD1.4
SD1.3
SD1.2
SD1.1
SD1.0
Default
0
0
0
0
0
0
0
0
6.5.17 Switch debounce count register (76h)
The switch debounce count register is used to count the debounce time that the switch
debounce logic uses to determine if a switch connected to one of the Port 0 or Port 1 pins
finally stays open (logic 1) or closed (logic 0). This number, together with the oscillator
frequency supplied to P0_0, determines the debounce time (for example, the debounce
time will be 10 s if this register is set to 0Ah and external oscillator frequency is 1 MHz).
See Section 6.10 “Switch debounce circuitry” for further information.
Table 59.
Bit
7
6
5
4
3
2
1
0
Symbol
SDC0.7
SDC0.6
SDC0.5
SDC0.4
SDC0.3
SDC0.2
SDC0.1
SDC0.0
Default
0
0
0
0
0
0
0
0
[1]
PCAL6524
Product data sheet
Switch debounce count register (address 76h) bit description [1]
The switch debounce logic is disabled if this register is set to 00h.
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
6.6 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above VDD(P) to a maximum of
5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either VDD(P) or VSS. The external voltage applied to this I/O pin should not exceed the
recommended levels for proper operation.
data from
shift register
data from
shift register
write
configuration
pulse
output port
register data
configuration
register
D
VDD(P)
Q1
Q
FF
CK
Q
D
Q
FF
write pulse
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
ESD
protection
diode
Q2
CK
output port
register
VSS
D
Q
input port
register data
FF
read pulse
CK
VDD(P)
PULL-UP/PULL-DOWN
CONTROL
INTERRUPT
MASK
input port
register
100 kΩ
D
input latch
register
data from
shift register
D
Q
CK
data from
shift register
Q
LATCH
read pulse
FF
write input
latch pulse
to INT
polarity inversion
register
D
EN
input port
latch
Q
FF
write polarity
pulse
CK
002aag034
On power-up or reset, all registers return to default values.
Fig 11. Simplified schematic of P0_0 to P2_7
6.7 Power-on reset
When power (from 0 V) is applied to VDD(P), an internal power-on reset holds the
PCAL6524 in a reset condition until VDD(P) has reached VPOR. At that time, the reset
condition is released and the PCAL6524 registers and I2C-bus/SMBus state machine
initializes to their default states. After that, VDD(P) must be lowered to below VPOR and
back up to the operating voltage for a power-reset cycle. See Section 8.2 “Power-on reset
requirements”.
PCAL6524
Product data sheet
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
6.8 Reset input (RESET)
The RESET input can be asserted to initialize the system while keeping the VDD(P) at its
operating level. A reset can be accomplished by holding the RESET pin LOW for a
minimum of tw(rst). The PCAL6524 registers and I2C-bus/SMBus state machine are
changed to their default state once RESET is LOW (0). When RESET is HIGH (1), the I/O
levels at the P port can be changed externally or through the master. This input requires a
pull-up resistor to VDD(I2C-bus) if no active connection is used.
6.9 Interrupt output (INT)
The INT output has an open-drain structure and requires pull-up resistor to VDD(P) or
VDD(I2C-bus) depending on the application. When any current input port state differs from its
corresponding input port register state, the interrupt output pin is asserted (logic 0) to
indicate the system master (MCU) that one of input port states has changed. A pin
configured as an output cannot cause an interrupt. Changing an I/O from an output to an
input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the input port register.
In order to enable the interrupt output, the following three conditions must be satisfied:
• The GPIO must be configured as an input port by writing "1" to configuration port
registers (0Ch, 0Dh, 0Eh)
• The interrupt mask registers (54h, 55h, 56h) must set to "0" to unmask interrupt
sources.
• The interrupt edge registers (60h to 65h) select what action on each input pin will
cause an interrupt; there are four different interrupt trigger modes: level trigger,
rising-edge trigger, falling-edge trigger, or any edge trigger.
The input latch registers (48h, 49h, 4Ah) control each input pin either to enable latched
input state or non-latched input state. When input pin is set to latch state, it will hold or
latch the input pin state (keep the logic value) and generate an interrupt until the master
can service the interrupt. This minimizes the host's interrupt service response for fast
moving inputs.
Any interrupt status bit can be cleared and INT pin de-asserted by using one of the
following methods and conditions:
•
•
•
•
•
•
•
Power on reset (POR), hardware reset from RESET pin, or software reset call
Read input port registers (00h, 01h, 02h)
Write logic 1 to interrupt clear registers (68h, 69h, 6Ah)
Write logic 1 to interrupt mask registers (54h, 55h, 56h)
Write logic 0 to configuration registers (0Ch, 0Dh, 0Eh), set pin as output port.
Input pin goes back to its initial state in level trigger and non-latch mode
Input pin goes back to its initial state in level trigger and change latch to non-latch
mode
• Change the interrupt trigger mode from level trigger to edge trigger or vice versa in
interrupt edge registers
PCAL6524
Product data sheet
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PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
When using the input latch feature, the input pin state is latched. The interrupt is
de-asserted only when data is read from the port that generated the interrupt. The
interrupt reset occurs in the read mode at the acknowledge (ACK) or not acknowledge
(NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or
NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during
this pulse. Any change of the inputs after resetting is detected and is transmitted as INT.
6.10 Switch debounce circuitry
Mechanical switches do not make clean make-or-break connections and the contacts can
‘bounce’ for a significant period of time before settling into a steady-state condition. This
can confuse fast processors and make the physical interface difficult to design and the
software interface difficult to make reliable.
The PCAL6524 implements hardware to ease the hardware interface by debouncing
switch closures with dedicated circuitry. P0_1 to P0_7, P1_0 to P1_7 can connect to this
debounce hardware on a pin-by-pin basis. These switch debouncers remove bounce
when a switch opens or closes by requiring that sequentially clocked inputs remain in the
same state for a number of sampling periods. The output does not change until the input
is stable for a programmable duration. The circuit block diagram (Figure 13) shows the
functional blocks consisting of an external oscillator, counter, edge detector, and
D flip-flop. When the switch input state changes, the edge detector will reset the counter.
When the switch input state is stable for the full qualification period, the counter clocks the
flip-flop, updating the output. Figure 14 shows the typical opening and closing switch
debounce operation timing.
To use the debounce circuitry, set the port pins (P0_1 to P0_7, and P1_0 to P1_7) with
switches attached in the Switch Debounce Enable 0 and 1 registers (74h, 75h). Connect
an external oscillator signal on P0_0, which serves as a time base to the debounce timer.
Finally, set a delay time in the Switch Debounce Count register (76h). The combination of
time base of the external oscillator and the debounce count sets the qualification
debounce period or tDP in Figure 14. Note that all debounce counters will use the same
time base and count, but they all function independently.
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
28 of 68
PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
aaa-019792
Fig 12. Switch contact bounce
P0_1
~
P1_7
EDGE
DETECT
switch
debounce
counter (76h)
D
P0_0
(external
oscillator)
R
COUNTER
Q
Q
filtered P0_1 ~ P1_7
internal
Clk
aaa-009086
The first time external clock is connected, external clock is required to wait 9 clock cycles for the
debounce circuit in normal operation.
Fig 13. Debouncer block diagram
PCAL6524
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29 of 68
PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
tDP
P0_1
~
P1_7
Filtered
P0_1 ~ P1_7
(internal)
aaa-014658
tDP = [PERIOD of EXT CLOCK] * [Debounce counter(76h)] = 1 s * 10 = 10 s (if external clock =
1 MHz, debounce count register (76h) = 0Ah)
Fig 14. Switch debounce timing
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
7. Bus transactions
The PCAL6524 is an I2C-bus slave device. Data is exchanged between the master and
PCAL6524 through write and read commands using I2C-bus. The two communication
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Write commands
Data is transmitted to the PCAL6524 by sending the device address with the Least
Significant Bit (LSB) set to a logic 0 (see Figure 4 for device address). The command byte
is sent after the address and determines which register receives the data that follows the
command byte.
Many of the registers within the PCAL6524 are configured to operate as register triples.
The groups are input ports, output ports, polarity inversion and configuration registers, as
well as Input latch, Pull-up/pull-down enable and selection registers, Interrupt mask and
Interrupt status, Interrupt clear, and Input port (status) without Interrupt clear registers,
Individual pin output port configuration registers, and switch debounce registers. After
sending data to one register, the next data byte is sent to the next register in the group.
For example, if the first byte is sent to Output Port 1 (register 05h), the next byte is stored
in Output Port 2 (register 06h). The next byte sent is stored in Output Port 0 (register 04h)
and the next byte will overwrite Output Port 1 (register 05h). Since every new write access
after a STOP condition requires a Command byte, which sets the Pointer register, the next
new write access will be to an arbitrary register.
There is no limit on the number of data bytes sent in one write transmission. In this way,
the host can continuously update a register group independently of the other registers or
the host can simply update a single register.
There are two 6-register groups: Output drive strength (40h to 45h) and interrupt edge
(60h to 65h) registers which can be programmed continuously in this group.
There is one register that is not part of a register group: Output port configuration (5Ch).
When this register is accessed multiple times, the register address remains fixed on the
same address.
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
31 of 68
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1
2
3
4
5
6
7
8
9
slave address
SDA S
command byte
0
0 A1 A0 0
START condition
R/W
0
1
0
NXP Semiconductors
PCAL6524
Product data sheet
SCL
A
0
0
0
0
0
1
acknowledge
from slave
data to port 1
data to port 0
0
0
A 0.7
DATA 0
0.0 A 1.7
acknowledge
from slave
DATA 1
STOP
condition
data to port 2
1.0 A 2.7
acknowledge
from slave
DATA 2
2.0 A
P
acknowledge
from slave
acknowledge
from slave
write to port
tv(Q)
data out from port 0
DATA 0 VALID
DATA 1 VALID
tv(Q)
DATA 2 VALID
data out from port 2
aaa-008804
Fig 15. Write to Output port register
SCL
1
2
3
4
5
6
7
8
slave address
0
1
0
0
START condition
data to register (n)
command byte
0 A1 A0 0
A 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 A
R/W
acknowledge
from slave
MSB
acknowledge
from slave
data to register (n + 1)
DATA 0
A
LSB
MSB
acknowledge
from slave
STOP
condition
data to register (n + 2)
DATA 1
A
LSB
MSB
acknowledge
from slave
DATA 2
A
P
LSB
acknowledge
from slave
aaa-008805
Fig 16. Write to device registers (operate as register triples)
PCAL6524
32 of 68
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SDA S
9
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Rev. 1 — 22 September 2015
All information provided in this document is subject to legal disclaimers.
tv(Q)
data out from port 1
PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
7.2 Read commands
To read data from the PCAL6524, the bus master must first send the PCAL6524 address
with the least significant bit set to a logic 0 (see Figure 4 for device address).
The command byte is sent after the address and determines which register is to be
accessed.
After a restart or a STOP followed by a START condition, the device address is sent
again, but this time the least significant bit is set to a logic 1 to read data. Data from the
register defined by the command byte is sent by the PCAL6524 (see Figure 17 to
Figure 20). Additional bytes may be read after the first byte read is complete and will
reflect the next register in the group. For example, if Input Port 1 is read, the next byte
read is Input Port 2. There is no limit on the number of data bytes received in one read
transmission, but on the final byte received the bus master must not acknowledge the
data.
After a subsequent restart or a STOP followed by a START condition, the command byte
contains the value of the next register to be read in the group. For example, if Input Port 1
was read last before the restart, the register that is read after the restart is the
Input Port 2.
command byte
slave address
SDA S
0
1
0
0
0 A1 A0 0
START condition
A
(cont.)
0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 A
R/W
acknowledge
from slave
acknowledge
from slave
data from register (n)
slave address
(cont.) S
0
1
0
0
(repeated)
START condition
MSB
0 A1 A0 1
A
R/W
acknowledge
from slave
data from register (n + 2)
LSB
DATA (first byte)
MSB
A
acknowledge
from master
LSB
DATA (last byte)
NA
no acknowledge
from master
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
P
STOP
condition
aaa-008806
Fig 17. Read from device registers (operate as register triples)
PCAL6524
Product data sheet
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NXP Semiconductors
PCAL6524
Product data sheet
data into port 0
DATA 0
data into port 1
DATA 1
data into port 2
DATA 2
INT
tv(INT)
SCL
1
2
3
4
trst(INT)
5
6
slave address
0
1
0
0
8
9
R/W
0 A1 A0 1
I0.x
A
7
6
5
4
3
I1.x
2
1
0
A
acknowledge
from slave
6
5
4
3
2
1
0
A
(DATA 1)
(DATA 0)
START condition
7
I2.x
acknowledge
from master
7
6
5
4
3
2
1
0
A
(DATA 2)
acknowledge
from master
STOP condition
I0.x
acknowledge
from master
7
6
5
4
3
2
1
0
1
P
(DATA 0)
non acknowledge
from master
read from port 0
read from port 1
read from port 2
aaa-008807
This figure eliminates the command byte transfers and a restart between the initial slave address call and actual data transfer from P port (see Figure 17).
Fig 18. Read input port register (non-latched), scenario 1
PCAL6524
34 of 68
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Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to ‘00’ (read input port register).
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Rev. 1 — 22 September 2015
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SDA S
7
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DATA 00
DATA 01
DATA 02
DATA 03
tsu(D)
th(D)
data into port 1
DATA 10
DATA 11
DATA 12
tsu(D)
th(D)
data into port 2
NXP Semiconductors
PCAL6524
Product data sheet
data into port 0
DATA 20
DATA 21
DATA 22
INT
tv(INT)
1
2
3
4
5
6
slave address
SDA S
0
1
0
0
START condition
7
8
9
R/W
0 A1 A0 1
I0.x
A
acknowledge
from slave
I1.x
DATA 00
A
acknowledge
from master
DATA 10
I2.x
A
acknowledge
from master
DATA 22
I0.x
A
acknowledge
from master
STOP condition
DATA 03
1
P
non acknowledge
from master
read from port 0
read from port 1
read from port 2
aaa-008809
This figure eliminates the command byte transfers and a restart between the initial slave address call and actual data transfer from P port (see Figure 17).
Fig 19. Read input port register (non-latched), scenario 2
PCAL6524
35 of 68
© NXP Semiconductors N.V. 2015. All rights reserved.
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to ‘00’ (read input port register).
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Rev. 1 — 22 September 2015
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SCL
trst(INT)
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DATA 01
DATA 02
NXP Semiconductors
PCAL6524
Product data sheet
data into port 0
DATA 03
tsu(D)
data into port 1
DATA 10
DATA 11
DATA 12
DATA 21
DATA 22
I1.x
I2.x
th(D)
data into port 2
DATA 20
INT
tv(INT)
1
2
3
4
5
6
slave address
SDA S
0
1
0
0
START condition
7
8
9
R/W
0 A1 A0 1
I0.x
A
acknowledge
from slave
DATA 01
A
acknowledge
from master
DATA 10
A
acknowledge
from master
DATA 21
I0.x
A
acknowledge
from master
STOP condition
DATA 02
1
P
non acknowledge
from master
read from port 0
read from port 1
read from port 2
aaa-008810
This figure eliminates the command byte transfers and a restart between the initial slave address call and actual data transfer from P port (see Figure 17).
Fig 20. Read input port register (latch enabled), scenario 3
PCAL6524
36 of 68
© NXP Semiconductors N.V. 2015. All rights reserved.
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to ‘00’ (read input port register).
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Rev. 1 — 22 September 2015
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SCL
trst(INT)
PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
8. Application design-in information
VDD(I2C-bus)
VDD(P)
10 kΩ (× 7)
VDD(I2C-bus) = 1.8 V
10 kΩ
10 kΩ
10 kΩ
VDD
SUBSYSTEM 1
(e.g., alarm system)
10 kΩ
VDD(I2C-bus)
MASTER
CONTROLLER
SCL
SDA
VDD(P)
P0_0
P0_1
SCL
SDA
INT
RESET
ALARM(1)
A
controlled
switch
enable
PCAL6524
B
INT
RESET
P0_2
P0_3
VSS
P0_4
STATUS
MONITOR
P2_7
P0_5
P2_6
P0_6
P2_5
P0_7
P2_4
P1_0
P2_3
P1_1
P2_2
P1_2
P2_1
P1_3
P2_0
P1_4
KEYPAD
P1_5
ADDR
P1_6
VSS
P1_7
aaa-008808
Device address configured as 0100 010x for this example.
P0_0 and P0_2 through P1_0 are configured as inputs.
P0_1 and P1_1 through P1_7, and P2_0 through P2_7 are configured as outputs.
(1) External resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, a resistor
is not needed with internal pull-up or pull-down resistor option. If an output in the P port is configured as an output, there is no
need for external pull-up resistors.
Fig 21. Typical application
PCAL6524
Product data sheet
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PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
8.1 Output drive strength control
The Output drive strength registers allow the user to control the output drive level of the
GPIO. Each GPIO can be configured independently to one of the four possible output
current levels. By programming these bits the user is changing the number of transistor
pairs or ‘fingers’ that drive the I/O pad.
Figure 22 shows a simplified output stage. The behavior of the pad is affected by the
Configuration register, the output port data, and the current control register. When the
Current Control register bits are programmed to 01b, then only two of the fingers are
active, reducing the current drive capability by 50 %.
PMOS_EN0
VDD(P)
PMOS_EN1
Current Control
register
PMOS_EN[3:0]
DECODER
NMOS_EN[3:0]
PMOS_EN2
Configuration
register
PMOS_EN3
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
Output port
register
NMOS_EN3
NMOS_EN2
NMOS_EN1
NMOS_EN0
002aah142
Fig 22. Simplified output stage
Reducing the current drive capability may be desirable to reduce system noise. When the
output switches (transitions from H/L), there is a peak current that is a function of the
output drive selection. This peak current runs through VDD and VSS package inductance
and will create noise (some radiated, but more critically Simultaneous Switching Noise
(SSN)). In other words, switching many outputs at the same time will create ground and
supply noise. The output drive strength control through the Output Drive Strength
registers allows the user to mitigate SSN issues without the need of additional external
components.
PCAL6524
Product data sheet
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
8.2 Power-on reset requirements
In the event of a glitch or data corruption, PCAL6524 can be reset to its default conditions
by using the power-on reset feature. Power-on reset requires that the device go through a
power cycle to be completely reset. This reset also happens when the device is
powered on for the first time in an application.
The two types of power-on reset are shown in Figure 23 and Figure 24.
VDD(P)
ramp-up
ramp-down
re-ramp-up
td(rst)
time
(dV/dt)r
(dV/dt)f
time to re-ramp
when VDD(P) drops
below 0.2 V or to VSS
(dV/dt)r
002aag960
Fig 23. VDD(P) is lowered below 0.2 V or to 0 V and then ramped up to VDD(P)
VDD(P)
ramp-down
ramp-up
td(rst)
VI drops below POR levels
(dV/dt)f
time
time to re-ramp
when VDD(P) drops
to VPOR(min) − 50 mV
(dV/dt)r
002aag961
Fig 24. VDD(P) is lowered below the POR threshold, then ramped back up to VDD(P)
Table 60 specifies the performance of the power-on reset feature for PCAL6524 for both
types of power-on reset.
Table 60. Recommended supply sequencing and ramp rates
Tamb = 25 C (unless otherwise noted). Not tested; specified by design.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
(dV/dt)f
fall rate of change of voltage
Figure 23
0.1
-
2000
ms
(dV/dt)r
rise rate of change of voltage
Figure 23
0.1
-
2000
ms
td(rst)
reset delay time
Figure 23; re-ramp time when
VDD(P) drops below 0.2 V or to VSS
1
-
-
s
Figure 24; re-ramp time when
VDD(P) drops to VPOR(min) 50 mV
1
-
-
s
VDD(gl)
glitch supply voltage difference
Figure 25
[1]
-
-
1.0
V
[2]
tw(gl)VDD
supply voltage glitch pulse width
Figure 25
-
-
10
s
VPOR(trip)
power-on reset trip voltage
falling VDD(P)
0.7
-
-
V
rising VDD(P)
-
-
1.5
V
[1]
Level that VDD(P) can glitch down to with a ramp rate at 0.4 s/V, but not cause a functional disruption when tw(gl)VDD < 1 s.
[2]
Glitch width that will not cause a functional disruption when VDD(gl) = 0.5 VDD(P).
PCAL6524
Product data sheet
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance. Figure 25 and Table 60 provide more information on
how to measure these specifications.
VDD(P)
∆VDD(gl)
tw(gl)VDD
time
002aag962
Fig 25. Glitch width and glitch height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition
is released and all the registers and the I2C-bus/SMBus state machine are initialized to
their default states. The value of VPOR differs based on the VDD being lowered to or from
0 V. Figure 26 and Table 60 provide more details on this specification.
VDD(P)
VPOR (rising VDD(P))
VPOR (falling VDD(P))
time
POR
time
002aag963
Fig 26. Power-on reset voltage (VPOR)
8.3 Device current consumption with internal pull-up and pull-down
resistors
The PCAL6524 integrates programmable pull-up and pull-down resistors to eliminate
external components when pins are configured as inputs and pull-up or pull-down
resistors are required (for example, nothing is driving the inputs to the power supply rails.
Since these pull-up and pull-down resistors are internal to the device itself, they contribute
to the current consumption of the device and must be considered in the overall system
design.
The pull-up or pull-down function is selected in registers 50h, 51h and 52h, while the
resistor is connected by the enable registers 4Ch, 4Dh and 4Eh. The configuration of the
resistors is shown in Figure 11.
If the resistor is configured as a pull-up, that is, connected to VDD, a current will flow from
the VDD(P) pin through the resistor to ground when the pin is held LOW. This current will
appear as additional IDD upsetting any current consumption measurements.
PCAL6524
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
In the same manner, if the resistor is configured as a pull-down and the pin is held HIGH,
current will flow from the power supply through the pin to the VSS pin. While this current
will not be measured as part of IDD, one must be mindful of the 200 mA limiting value
through VSS.
The pull-up and pull-down resistors are simple resistors and the current is linear with
voltage. The resistance specification for these devices spans from 50 k with a nominal
100 k value. Any current flow through these resistors is additive by the number of pins
held HIGH or LOW and the current can be calculated by Ohm’s law. See Figure 30 for a
graph of supply current vs the number of pull-up resistors.
8.4 I2C-bus error recovery techniques
There are a number of techniques to recover from error conditions on the I2C-bus. Slave
devices like the PCAL6524 use a state machine to implement the I2C protocol and expect
a certain sequence of events to occur to function properly. Unexpected events at the I2C
master can wreak havoc with the slaves connected on the bus. However, it is usually
possible to recover deterministically to a known bus state with careful protocol
manipulation.
A hard slave reset, either through power-on reset or by activating the RESET pin, will set
the device back into the default state. Of course, this means the input/output pins and
their configuration will be lost, which might cause some system issues.
A STOP condition, which is only initiated by the master, will reset the slave state machine
into a known condition where SDA is not driven LOW by the slave and logically, the slave
is waiting for a START condition. A STOP condition is defined as SDA transitioning from
LOW to HIGH while SCL is HIGH.
If the master is interrupted during a packet transmission, the slave may be sending data or
performing an Acknowledge, driving the I2C-bus SDA line LOW. Since SDA is LOW, it
effectively blocks any other I2C-bus transaction. A deterministic method to clear this
situation, once the master recognizes a ‘stuck bus’ state, is for the master to blindly
transmit nine clocks on SCL. If the slave was transmitting data or acknowledging, nine or
more clocks ensures the slave state machine returns to a known, idle state since the
protocol calls for eight data bits and one ACK bit. It does not matter when the slave state
machine finishes its transmission, extra clocks will be recognized as STOP conditions.
The PCAL6524 SCL pin is an input only. If SCL is stuck LOW, then only the bus master or
a slave performing a clock stretch operation can cause this condition.
With careful design of the bus master error recovery firmware, many I2C-bus protocol
problems can be avoided.
PCAL6524
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PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
9. Limiting values
Table 61. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD(I2C-bus)
I2C-bus
Conditions
Min
Max
Unit
0.5
+4.0
V
VDD(P)
supply voltage port P
VI
input voltage
[1]
0.5
+6.5
V
0.5
+6.5
VO
output voltage
[1]
V
0.5
+6.5
V
IIK
input clamping current
ADDR, RESET, SCL; VI < 0 V
-
20
mA
IOK
IIOK
output clamping current
INT; VO < 0 V
-
20
mA
input/output clamping current
P port; VO < 0 V or VO > VDD(P)
-
20
mA
SDA; VO < 0 V or VO > VDD(I2C-bus)
-
20
mA
continuous; P port; VO = 0 V to VDD(P)
-
50
mA
continuous; SDA, INT;
VO = 0 V to VDD(I2C-bus)
-
25
mA
supply voltage
LOW-level output current
IOL
IOH
HIGH-level output current
continuous; P port; VO = 0 V to VDD(P)
-
25
mA
IDD
supply current
continuous through VSS
-
200
mA
IDD(P)
supply current port P
continuous through VDD(P)
-
160
mA
IDD(I2C-bus)
I2C-bus supply current
continuous through VDD(I2C-bus)
-
10
mA
Tstg
storage temperature
65
+150
C
Tj(max)
maximum junction temperature
-
125
C
[1]
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
10. Recommended operating conditions
Table 62.
Operating conditions
Symbol
Parameter
VDD(I2C-bus)
I2C-bus
VDD(P)
supply voltage port P
VIH
HIGH-level input voltage
Conditions
Min
Max
Unit
0.8
3.6
V
1.65
5.5
V
VDD(I2C-bus) 1.1 V
0.8 VDD(I2C-bus)
3.6
V
VDD(I2C-bus) > 1.1 V
0.7 VDD(I2C-bus)
3.6
V
0.7 VDD(P)
5.5
V
VDD(I2C-bus) 1.1 V
0.5
0.2 VDD(I2C-bus)
V
VDD(I2C-bus) > 1.1 V
supply voltage
SCL, SDA, RESET, ADDR
P2_7 to P0_0
VIL
LOW-level input voltage
SCL, SDA, RESET, ADDR
0.5
0.3 VDD(I2C-bus)
V
P2_7 to P0_0
0.5
0.3 VDD(P)
V
IOH
HIGH-level output current
P2_7 to P0_0
-
10
mA
IOL
LOW-level output current
P2_7 to P0_0
-
25
mA
Tamb
ambient temperature
operating in free air
40
+85
C
PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
11. Thermal characteristics
Table 63.
Thermal characteristics
Symbol
Parameter
Conditions
Value (typ)
Unit
Rth(j-a)
Thermal resistance from junction to ambient on a JEDEC
2S2P board[1]
TSSOP32 package
78.1
C/W
HUQFN32 package
34.6
C/W
[1]
The package thermal resistance is calculated in accordance with JESD 51-7.
12. Static characteristics
Table 64. Static characteristics
Tamb = 40 C to +85 C; VDD(I2C-bus) = 0.8 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VIK
input clamping voltage
II = 18 mA
1.2
-
-
V
VPOR
power-on reset voltage
VI = VDD(P) or VSS; IO = 0 mA
-
1.2
1.5
V
VOH
HIGH-level output
voltage[2]
P port; IOH = 8 mA; CCX.X = 11b
VDD(P) = 1.65 V
1.2
-
-
V
VDD(P) = 2.3 V
1.8
-
-
V
VDD(P) = 3 V
2.6
-
-
V
VDD(P) = 4.5 V
4.1
-
-
V
P port; IOH = 2.5 mA and CCX.X = 00b;
IOH = 5 mA and CCX.X = 01b;
IOH = 7.5 mA and CCX.X = 10b;
IOH = 10 mA and CCX.X = 11b;
VOL
LOW-level
output voltage[2]
VDD(P) = 1.65 V
1.1
-
-
V
VDD(P) = 2.3 V
1.7
-
-
V
VDD(P) = 3 V
2.5
-
-
V
VDD(P) = 4.5 V
4.0
-
-
V
VDD(P) = 1.65 V
-
-
0.45
V
VDD(P) = 2.3 V
-
-
0.25
V
VDD(P) = 3 V
-
-
0.25
V
VDD(P) = 4.5 V
-
-
0.20
V
VDD(P) = 1.65 V
-
-
0.5
V
VDD(P) = 2.3 V
-
-
0.3
V
VDD(P) = 3 V
-
-
0.25
V
VDD(P) = 4.5 V
-
-
0.2
V
P port; IOL = 8 mA; CCX.X = 11b
P port; IOL = 2.5 mA and CCX.X = 00b;
IOL = 5 mA and CCX.X = 01b;
IOL = 7.5 mA and CCX.X = 10b;
IOL = 10 mA and CCX.X = 11b;
PCAL6524
Product data sheet
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Table 64. Static characteristics …continued
Tamb = 40 C to +85 C; VDD(I2C-bus) = 0.8 V to 3.6 V; unless otherwise specified.
Min
Typ[1]
Max
Unit
VOL = 0.4 V; VDD(I2C-bus) 2 V
15
-
-
mA
VOL = 0.4 V; VDD(I2C-bus) > 2 V
Symbol
Parameter
Conditions
IOL
LOW-level
output current[3]
SDA
II
input current
20
-
-
mA
INT; VOL = 0.4 V; VDD(P) = 1.65 V to 5.5 V
3
[4]
-
mA
ADDR, SCL, SDA, RESET;
VDD(P) = 1.65 V to 5.5 V; VI = VDD(I2C-bus) or VSS
-
-
1
A
IIH
HIGH-level input current P port; VI = VDD(P); VDD(P) = 1.65 V to 5.5 V
-
-
1
A
IIL
LOW-level input current
P port; VI = VSS; VDD(P) = 1.65 V to 5.5 V
-
-
1
A
IDD
supply current
Clocked mode; IDD(I2C-bus) + IDD(P);
SDA, P port, ADDR, RESET; VI on ADDR, SDA
and RESET = VDD(I2C-bus) or VSS;
VI on P port = VDD(P); IO = 0 mA; I/O = inputs
VDD(P) = 3.6 V to 5.5 V; fSCL = 0 kHz
-
3
7
A
VDD(P) = 2.3 V to 3.6 V; fSCL = 0 kHz
-
2
5
A
VDD(P) = 1.65 V to 2.3 V; fSCL = 0 kHz
-
1.5
3
A
VDD(P) = 3.6 V to 5.5 V; fSCL = 400 kHz
-
27
45
A
VDD(P) = 2.3 V to 3.6 V; fSCL = 400 kHz
-
12
25
A
VDD(P) = 1.65 V to 2.3 V; fSCL = 400 kHz
-
7.5
15
A
VDD(P) = 3.6 V to 5.5 V; fSCL = 1 MHz
-
70
110
A
VDD(P) = 2.3 V to 3.6 V; fSCL = 1 MHz
-
30
60
A
VDD(P) = 1.65 V to 2.3 V; fSCL = 1 MHz
-
20
40
A
Active mode; IDD(I2C-bus) + IDD(P);
P port, ADDR, RESET;
VI on ADDR, RESET = VDD(I2C-bus);
VI on P port = VDD(P); IO = 0 mA; I/O = inputs;
continuous register read
VDD(P) = 3.6 V to 5.5 V; fSCL = 400 kHz
-
150
250
A
VDD(P) = 2.3 V to 3.6 V; fSCL = 400 kHz
-
120
200
A
VDD(P) = 1.65 V to 2.3 V; fSCL = 400 kHz
-
75
150
A
VDD(P) = 3.6 V to 5.5 V; fSCL = 1 MHz
-
450
625
A
VDD(P) = 2.3 V to 3.6 V; fSCL = 1 MHz
-
270
500
A
VDD(P) = 1.65 V to 2.3 V; fSCL = 1 MHz
-
160
210
A
-
1.7
2.5
mA
ADDR, SCL, SDA, RESET;
one input at VDD(I2C-bus) 0.6 V, other inputs at
VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V
-
-
25
A
P port; one input at VDD(P) 0.6 V, other inputs at
VDD(P) or VSS; VDD(P) = 1.65 V to 5.5 V
-
-
80
A
with pull-ups enabled; IDD(I2C-bus) + IDD(P);
P port, ADDR, RESET; VI on ADDR, SCL, SDA
and RESET = VDD(I2C-bus) or VSS;
VI on P port = VSS; IO = 0 mA;
I/O = inputs with pull-up enabled; fSCL = 0 kHz
VDD(P) = 1.65 V to 5.5 V
IDD
additional quiescent
supply current[5]
PCAL6524
Product data sheet
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44 of 68
PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Table 64. Static characteristics …continued
Tamb = 40 C to +85 C; VDD(I2C-bus) = 0.8 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
capacitance[6]
Conditions
Min
Typ[1]
Max
Unit
VI = VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V
-
6
-
pF
VI/O = VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V
-
7
-
pF
Ci
input
Cio
input/output
capacitance[6]
VI/O = VDD(P) or VSS; VDD(P) = 1.65 V to 5.5 V
-
7.5
-
pF
Rpu(int)
internal pull-up
resistance
input/output
50
100
150
k
Rpd(int)
internal pull-down
resistance
input/output
50
100
150
k
[1]
For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V or 3.6 V VDD) and Tamb = 25 C. Except for IDD, the typical
values are at VDD(P) = VDD(I2C-bus) = 3.3 V and Tamb = 25 C.
[2]
The total current sourced by all I/Os must be limited to 160 mA.
[3]
Each I/O must be externally limited to a maximum of 25 mA and each octal (P0_0 to P0_7 and P1_0 to P1_7) must be limited to a
maximum current of 100 mA, for a device total of 200 mA.
[4]
Typical value for Tamb = 25 C. VOL = 0.4 V and VDD(I2C-bus) = VDD(P) = 3.3 V. Typical value for VDD(I2C-bus) = VDD(P) < 2.5 V, VOL = 0.6 V.
[5]
Internal pull-up/pull-down resistors disabled.
[6]
Value not tested in production, but guaranteed by design and characterization.
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
12.1 Typical characteristics
DDD
,''
ȝ$
9''
9''
9''
9''
9''
9''
9''
9''
9
9
9
9
9
9
9
9
7DPE&
a. SCL = 400 KHz
DDD
,''
ȝ$
9''
9''
9''
9''
9''
9''
9''
9''
9
9
9
9
9
9
9
9
7DPE&
b. SCL = 1 MHz
Fig 27. Supply current vs ambient temperature
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
46 of 68
PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
DDD
,''VWE
ȝ$
9''
9''
9''
9''
9''
9''
9''
9''
9
9
9
9
9
9
9
9
7DPE&
Fig 28. Standby supply current vs ambient temperature
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
47 of 68
PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
DDD
,''
X$
&
9
'
9
'
'
9
'
9
'
9'
9'
9'
9'
9
9
'
'
9
'
9'
9'
9'
9'
9
9'' 9'',9''3
a. SCL = 400 KHz
DDD
,''
X$
&
9
'
9'
'
9'
9
'
9'
9
'
9'
9
'
9'
9
'
9'
9
'
9'
9
'
9
9'
9'' 9'',9''3
b. SCL = 1 MHz
Fig 29. Supply current vs supply voltage
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
48 of 68
PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
DDD
,''3
P$
7
7
7
7
7
7
7
QXPEHURI,2KHOG/2:
Fig 30. Supply current vs number of I/O held LOW
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
49 of 68
PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
DDD
DDD
,VLQN
P$
,VLQN
P$
7
7
7
7
7
7
92/9
a. VDD(P) = 1.65 V
92/9
b. VDD(P) = 1.8 V
DDD
DDD
,VLQN
P$
,VLQN
P$
7
7
7
7
7
7
92/9
c. VDD(P) = 2.5 V
92/9
d. VDD(P) = 3.3 V
DDD
,VLQN
P$
DDD
,VLQN
P$
7
7
7
7
7
7
92/9
e. VDD(P) = 5 V
92/9
f. VDD(P) = 5.5 V
Fig 31. I/O sink current vs LOW-level output voltage
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
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50 of 68
PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
DDD
,VRXUFH
P$
7
7
7
9''392+9
a. VDD(P) = 1.65 V
DDD
9''392+9
DDD
,VRXUFH
P$
7
7
7
7
7
7
9''392+9
c. VDD(P) = 2.5 V
9''392+9
d. VDD(P) = 3.3 V
DDD
,VRXUFH
P$
DDD
,VRXUFH
P$
7
7
7
7
7
7
b. VDD(P) = 1.8 V
,VRXUFH
P$
7
7
7
DDD
,VRXUFH
P$
9''392+9
e. VDD(P) = 5 V
9''392+9
f. VDD(P) = 5.5 V
Fig 32. I/O source current vs HIGH-level output voltage
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
DDD
92/
P9
9''3
9''3
9''3
9
''3
9''3
9#P$
9#P$
9#P$
9#P$
9#P$
7DPE&
Fig 33. LOW-level output voltage vs temperature
DDD
9''392+
P9
9''3
9''3
9''3
9''3
9#P$
9#P$
9#P$
9#P$
7DPE&
Fig 34. I/O high voltage vs temperature
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
13. Dynamic characteristics
Table 65. I2C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 36.
Symbol Parameter
Conditions
Standard-mod
e I2C-bus
Fast-mode
I2C-bus
Fast-mode Plus Unit
I2C-bus
Min
Max
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
0
1000
tHIGH
HIGH period of the SCL
clock
4
-
0.6
-
0.26
-
s
tLOW
LOW period of the SCL
clock
4.7
-
1.3
-
0.5
-
s
tSP
pulse width of spikes
that must be suppressed
by the input filter
0
50
0
50
0
50
ns
tSU;DAT
data set-up time
250
-
100
-
50
-
ns
tHD;DAT
data hold time
kHz
0
-
0
-
0
-
ns
-
1000
20
300
-
120
ns
-
300
20
(VDD / 5.5 V)
300
-
120
ns
tr
rise time of both SDA
and SCL signals
[1]
tf
fall time of both SDA and
SCL signals
[1]
tBUF
bus free time between a
STOP and START
condition
4.7
-
1.3
-
0.5
-
s
tSU;STA
set-up time for a
repeated START
condition
4.7
-
0.6
-
0.26
-
s
tHD;STA
hold time (repeated)
START condition
4
-
0.6
-
0.26
-
s
tSU;STO
set-up time for STOP
condition
4
-
0.6
-
0.26
-
s
tVD;DAT
data valid time
SCL LOW to SDA
output valid
-
3.45
-
0.9
-
0.45
s
tVD;ACK
data valid acknowledge
time
ACK signal
from SCL LOW
to SDA (out) LOW
-
3.45
-
0.9
-
0.45
s
[1]
Value not tested in production, but guaranteed by design and characterization.
Table 66. Reset timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 38.
Symbol
Parameter
tw(rst)
reset pulse width
trec(rst)
reset recovery time
trst
reset time
[1]
Conditions
Standard-mode
I2C-bus
[1]
Fast-mode
I2C-bus
Fast-mode Plus Unit
I2C-bus
Min
Max
Min
Max
Min
Max
150
-
150
-
150
-
ns
500
-
500
-
500
-
ns
600
-
600
-
600
-
ns
Minimum time for SDA to become HIGH or minimum time to wait before doing a START.
PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
Table 67. Switching characteristics
Over recommended operating free air temperature range; CL 100 pF; unless otherwise specified. See Figure 37.
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Fast-mode Plus Unit
I2C-bus
Min
Max
Min
Max
Min
Max
tv(INT)
valid time on pin INT
from P port to INT
-
1
-
1
-
1
s
trst(INT)
reset time on pin INT
from SCL to INT
-
1
-
1
-
1
s
tv(Q)
data output valid time
from SCL to P port
-
400
-
400
-
400
ns
tsu(D)
data input set-up time
from P port to SCL
0
-
0
-
0
-
ns
th(D)
data input hold time
from P port to SCL
300
-
300
-
300
-
ns
Data
Bit 0
(LSB)
STOP
condition
(P)
14. Parameter measurement information
VDD(I2C-bus)
RL = 1 kΩ
DUT
SDA
CL = 50 pF
002aag977
a. SDA load configuration
two bytes for read Input port register(1)
STOP
START
condition condition
(P)
(S)
Address
Bit 7
(MSB)
Address
Bit 1
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
002aag952
b. Transaction format
tHIGH
tLOW
tSP
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
SCL
tBUF
tVD;DAT
tr
tf
tf(o)
tVD;ACK
tSU;STA
0.7 × VDD(I2C-bus)
SDA
tf
tHD;STA
tr
0.3 × VDD(I2C-bus)
tVD;ACK
tSU;DAT
tSU;STO
tHD;DAT
repeat START condition
STOP condition
002aag978
c. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
All parameters and waveforms are not applicable to all devices.
Byte 1 = I2C-bus address; Byte 2, byte 3 = P port data.
Fig 35. I2C-bus interface load circuit and voltage waveforms
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
VDD(I2C-bus)
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
002aag979
a. Interrupt load configuration
acknowledge
from slave
START condition
R/W
8 bits (one data byte)
from port
slave address
SDA S
SCL
0
1
0
1
2
3
0
4
0 A1 A0 1
5
6
7
8
acknowledge
from slave
DATA 1
A
no acknowledge
from master
STOP
condition
data from port
A
DATA 2
1
P
9
B
trst(INT) B
trst(INT)
INT
tv(INT)
data into
port
A
A
tsu(D)
ADDRESS
INT
DATA 1
0.5 × VDD(I2C-bus)
SCL
DATA 2
R/W
0.3 × VDD(I2C-bus)
tv(INT)
trst(INT)
0.5 × VDD(P)
Pn
0.7 × VDD(I2C-bus)
A
0.5 × VDD(I2C-bus)
INT
View A - A
View B - B
aaa-011059
b. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
All parameters and waveforms are not applicable to all devices.
Fig 36. Interrupt load circuit and voltage waveforms
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
500 Ω
Pn
DUT
2 × VDD(P)
CL = 50 pF
500 Ω
002aag981
a. P port load configuration
SCL
P0
A
P7
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
SDA
tv(Q)
Pn
unstable
data
last stable bit
A
P7
002aag982
b. Write mode (R/W = 0)
SCL
P0
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
tsu(D)
th(D)
Pn
0.5 × VDD(P)
002aag983
c. Read mode (R/W = 1)
CL includes probe and jig capacitance.
tv(Q) is measured from 0.7 VDD(I2C-bus) on SCL to 50 % I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Fig 37. P port load circuit and voltage waveforms
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
VDD(I2C-bus)
RL = 1 kΩ
SDA
DUT
500 Ω
Pn
DUT
CL = 50 pF
2 × VDD(P)
CL = 50 pF
500 Ω
002aag977
002aag981
a. SDA load configuration
b. P port load configuration
START
SCL
ACK or read cycle
SDA
0.3 × VDD(I2C-bus)
trst
RESET
0.5 × VDD(I2C-bus)
trec(rst)
tw(rst)
trec(rst)
trst
Pn
0.5 × VDD(P)
002aag984
c. RESET timing
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
The outputs are measured one at a time, with one transition per measurement.
I/Os are configured as inputs.
All parameters and waveforms are not applicable to all devices.
Fig 38. Reset load circuits and voltage waveforms
PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
15. Package outline
HUQFN32: plastic thermal enhanced ultra thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.56 mm
terminal 1
index area
D
B
SOT1426-1
A
E
A
A1
c
detail X
e1
1/2 e
C
v
w
b
e
9
C A B
C
16
y1 C
y
L
17
8
e
Eh
e2
1/2 e
1
terminal 1
index area
24
32
25
X
Dh
0
5 mm
scale
Dimensions (mm are the original dimensions)
Unit
mm
A(1)
A1
b
max 0.60 0.05 0.30
nom 0.56 0.02 0.21
min 0.45 0.00 0.18
C
D
Dh
E
Eh
e
e1
e2
L
v
0.2
5.1
5.0
4.9
3.1
3.0
2.9
5.1
5.0
4.9
3.1
3.0
2.9
0.5
3.5
3.5
0.45
0.40
0.35
0.1
w
y
0.05 0.05
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline
version
References
IEC
JEDEC
JEITA
sot1426-1_po
European
projection
Issue date
14-08-06
14-08-07
SOT1426-1
Fig 39. Package outline SOT1426-1 (HUQFN32)
PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP
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627
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=
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9(56,21
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02
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Fig 40. Package outline SOT487-1 (TSSOP32)
PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 41) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 68 and 69
Table 68.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 69.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 41.
PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 41. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCAL6524
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Rev. 1 — 22 September 2015
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
17. Soldering: PCB footprints
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627
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RFFXSLHGDUHD
',0(16,216LQPP
3
3
$\
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*[
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+\
VRWBIU
Fig 42. PCB footprint for SOT487-1 (TSSOP32); reflow soldering
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
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PCAL6524
NXP Semiconductors
Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI+84)1SDFNDJH
627
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Fig 43. PCB footprint for SOT1426-1 (HUQFN32); reflow soldering
PCAL6524
Product data sheet
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Rev. 1 — 22 September 2015
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
18. Abbreviations
Table 70.
Abbreviations
Acronym
Description
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
GPIO
General Purpose Input/Output
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
LED
Light-Emitting Diode
LSB
Least Significant Bit
MSB
Most Significant Bit
NACK
Not ACKnowledge
PCB
Printed-Circuit Board
POR
Power-On Reset
PRR
Pulse Repetition Rate
SMBus
System Management Bus
19. Revision history
Table 71.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCAL6524 v.1
20150922
Product data sheet
-
-
PCAL6524
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Ultra low-voltage translating 24-bit Fm+ I2C-bus/SMBus I/O expander
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCAL6524
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 September 2015
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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22. Contents
1
2
2.1
2.2
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.3
6.3.1
6.3.2
6.4
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10
6.5.11
6.5.12
6.5.13
6.5.14
6.5.15
6.5.16
6.5.17
6.6
6.7
6.8
6.9
6.10
7
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Agile I/O features . . . . . . . . . . . . . . . . . . . . . . . 3
Additional Agile I/O Plus features . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 7
Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7
Interface definition . . . . . . . . . . . . . . . . . . . . . . 8
Software Reset Call, and device ID addresses 8
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . 8
Device ID (PCAL6524 ID field) . . . . . . . . . . . . . 9
Pointer register and command byte . . . . . . . . 11
Register descriptions . . . . . . . . . . . . . . . . . . . 15
Input port registers (00h, 01h, 02h) . . . . . . . . 15
Output port registers (04h, 05h, 06h) . . . . . . . 15
Polarity inversion registers (08h, 09h, 0Ah) . . 16
Configuration registers (0Ch, 0Dh, 0Eh). . . . . 16
Output drive strength registers (40h, 41h,
42h, 43h, 44h, 45h) . . . . . . . . . . . . . . . . . . . . 17
Input latch registers (48h, 49h, 4Ah) . . . . . . . 18
Pull-up/pull-down enable registers (4Ch,
4Dh, 4Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pull-up/pull-down selection registers (50h,
51h, 52h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Interrupt mask registers (54h, 55h, 56h). . . . . 20
Interrupt status registers (58h, 59h, 5Ah) . . . . 20
Output port configuration register (5Ch) . . . . . 21
Interrupt edge registers (60h, 61h, 62h and
63h, 64h, 65h) . . . . . . . . . . . . . . . . . . . . . . . . 21
Interrupt clear registers (68h, 69h, 6Ah) . . . . . 23
Input status registers (6Ch, 6Dh, 6Eh) . . . . . . 23
Individual pin output configuration registers
(70h, 71h, 72h) . . . . . . . . . . . . . . . . . . . . . . . . 24
Switch debounce enable registers (74h, 75h) 25
Switch debounce count register (76h) . . . . . . 25
I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 26
Reset input (RESET) . . . . . . . . . . . . . . . . . . . 27
Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 27
Switch debounce circuitry . . . . . . . . . . . . . . . . 28
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 31
7.1
7.2
8
8.1
8.2
8.3
8.4
9
10
11
12
12.1
13
14
15
16
16.1
16.2
16.3
16.4
17
18
19
20
20.1
20.2
20.3
20.4
21
22
Write commands . . . . . . . . . . . . . . . . . . . . . .
Read commands . . . . . . . . . . . . . . . . . . . . . .
Application design-in information. . . . . . . . .
Output drive strength control . . . . . . . . . . . . .
Power-on reset requirements. . . . . . . . . . . . .
Device current consumption with internal
pull-up and pull-down resistors . . . . . . . . . . .
I2C-bus error recovery techniques . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Recommended operating conditions . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Typical characteristics . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Parameter measurement information . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Soldering: PCB footprints . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
33
37
38
39
40
41
42
42
43
43
46
53
54
58
60
60
60
60
61
63
65
65
66
66
66
66
67
67
68
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 22 September 2015
Document identifier: PCAL6524