AN1068

Application Note 1068
Application Notes for AP3770 System Solution
Prepared by Su Qing Hua
System Engineering Dept.
suppress the audio noise, internal line compensation to
reduce the number of system components, fixed cable
compensation to compensate the voltage drop on different
output cable for achieving good CV regulation, better
undershoot results with AP4340 when dynamic occurs.
1. Introduction
The AP3770 uses Pulse Frequency Modulation (PFM)
method to realize Discontinuous Conduction Mode (DCM)
operation for FLYBACK power supplies. The principle of
PFM is different with that of Pulse Width Modulation
(PWM), so the design of transformer is also different.
The AP3770 can achieve low standby power less than
30mW.
The AP3770 can provide accurate constant voltage,
constant current (CV/CC) regulation by using Primary Side
Regulation (PSR). AP3770 has the special technique to
Figure 1. 5V/1A Output for Battery Charger of Mobile Phone
Figure 1 is AP3770 typical application circuit, which is a
FLYBACK converter controlled by AP3770 with a
3-winding transformer---Primary winding (Np), Secondary
winding (Ns) and Auxiliary winding (Na). The AP3770
senses the auxiliary winding feedback voltage at FB pin
and obtains power supply at VCC pin.
Vdri---A simplified driving signal of primary transistor
Ip---The primary side current
Is ---The secondary side current
VSEC---The voltage of secondary
tSW---The period of switching frequency
tONP ---The time of primary side “ON”
tONS ---The time of secondary side “ON”
tOFF ---The discontinuous time
tOFFS --- The time of secondary side “Off”
IPK---Peak current of primary side
IPKS---Peak current of secondary side
VS---the sum of Vo and forward voltage of rectification
diode
Figure 2 is the typical operation waveforms of PFM
controller. In this figure, a series of relative idea operation
waveforms are given to illustrate some parameters used in
following design steps. And the nomenclature of the
parameters in Figure 2 is illustrated.
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Application Note 1068
tONP
Vdri
tSW
IPK
IP
IPKS
IS
tONS
VS
VSEC
tOFFS
tOFF
Figure 2. Operation Waveforms
In order to achieve low standby power, AP3770 decreases
the minimum operating voltage. And due to proprietary
Zero-Startup-Current technique, the startup up resistors
R3+R4 should be higher to 10M to 14MΩ to further lower
the power loss. The recommended value of dummy load
resistor R13 is 4.7KΩ to 10KΩ for a model with 5V output
voltage. The selection of dummy load resistor is a tradeoff
between standby power and I-V Curve.
2. Six Aspects for System Design
1.
2.
3.
4.
5.
6.
Low Standby Power Design
Switching Frequency Design
Transformer and Power Devices Design
Feedback Resistors Design
Line Compensation Design
Dynamic Response
2.1 Low Standby Power Design
2.2 Switching Frequency Design
VH=0.5V
VCS_REF
1.4V
VCPC
fSW
fSW
47.6kHz
20kHz
IO
42%IO
Figure 3. Relationship Between VCPC, fSW and IO with Constant Peak Current
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Application Note 1068
Where, the fSW is the switching frequency. When the peak
current IPK is constant, the output power depends on the
switching frequency fSW. fSW is linearly increased with load
increasing.
When the constant peak current is adopted, the voltage of
CPC pin is increased linearly with load increasing. The
maximum value of VCPC is equal to
t ONS
4
⋅ VDD = ⋅ 3.5V = 1.4V
t SW
10
(1)
In AP3770, two-segmented peak current is used to realize
audio noise suppression. The peak current is about 0.5V
when IO>42%IOmax, and the peak current is about
0.5V/1.5 when IO<42%IOmax.
The primary current ip(t) is sensed by a current sense
resistor RCS as shown in Figure 2. The power transferring
from input to output is given by:
PO =
1
2
⋅ LP ⋅ I pk ⋅ f SW
2
(2)
VLOAD VCPC VH=0.5V VCS_REF VL=0.5V/1.5 0.42хIO_MAX
IO_MAX fSW
55kHz
52kHz
fSW 23.1kHz
20kHz
3.85kHz 0.42хIO_MAX
IO_MAX ISOURCE 2/3*I SOURCE 0.42хIO_MAX
IO_MAX Figure 4. Relationship Between VCPC, fSW and IO with Variable Peak Current
So, the voltage of CPC pin and switching frequency has a
mutation at about 42% of load. At the mutation point, if the
peak current is changed from 0.5V( high IPK) to 0.33V(low
IPK), the voltage of CPC pin at low IPK will be increased to
1.5 times of VCPC at high IPK and the switching frequency
fSW at low IPK will be increased to 2.25 times of fSW at high
IPK. So the range of load working in the audio frequency is
suppressed.
VCS_REF
VH=0.5V
VL=0.5V/1.5
39%IO
42%IO
IO
Figure 5. Hysteresis at Conversion Between Low IPK and High IPK
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Application Note 1068
in all working conditions.
In order to avoid oscillation, a hysteresis is added at the
conversion between low IPK and high IPK. Considering the
relationship between audio noise and flux density of
transformer, deltaB≤2500 gauss is better for audio noise
suppression.
t SW ≥ t ONS + t OFFS
(7)
For the primary side current,
The low limitation of maximum switching frequency is
given by audio noise suppression. And the upper limit of
the AP3770 can be up to 120kHz. But this is only the limit
of the IC; the finally designed maximum switching
frequency is determined by the tradeoff between the
efficiency,
mechanical
dimensions
and
thermal
performance.
t ONP = I pk ⋅
Lp
(8)
Vindc
Where LP is the inductance of primary winding.
Vindc is the rectified DC voltage of input.
When Vindc is the minimum value, the maximum tONP can
be obtained. So,
2.3 Transformer and Power Devices Design
t ONP_MAX = I pk ⋅
Lp
In Constant Current operation of AP3770, the CC loop
control function of AP3770 will keep a fixed proportion
between D1 (in Figure 1) on-time tONS and D1 off-time
tOFFS (in Figure 2) by discharging or charging a capacitor
embedded in the IC. The fixed proportion is
For the secondary side current,
t ONS
4
=
t OFFS 6
In (10), LS is the inductance of secondary winding.
t ONS = I pks ⋅
(3)
t ONS
1
⋅ I pks ⋅
2
t ONS + t OFFS
I pks
(4)
In FLYBACK converter, when the primary transistor turns
ON, the energy stored in the magnetizing inductance Lp.
So the power transferring from the input to the output is
given by,
t ONS
1 NP
1 N
⋅
⋅ I pk ⋅
= ⋅ P ⋅ I pk
2 NS
t ONS + t OFFS 5 N S
Pin = Pin ⋅ηin = Vin ⋅ I in ⋅ηin
(11)
1
2
⋅ L p ⋅ I pk
⋅ f SW
2
(12)
'
(5)
'
Pin =
Thus the output constant-current is given by:
IO =
(10)
For (10), in CV regulation, the VS is a constant voltage, so
tONS is a constant value with different input voltage.
At the instant of D1 turn-on, the primary current transfers
to the secondary at an amplitude of:
N
= P ⋅ I pk
NS
LS
VS
(9)
VS = VO + Vd , Vd is the forward voltage of secondary diode.
The relationship between the output constant-current and
secondary peak current IPKS is given by:
IO =
Vindc _ min
Here, Pin ' is input power of transformer, not including the
all of the power loss at primary side (Rectifier, RCD
snubber, BJT and so on).
(6)
Design Steps:
ηin is definition to the input efficiency of system, which is
about 0.9.
Step 1, a reasonable IPK of FLYBACK with AP3770
should be designed
Then,
1-1. Calculate the Max. turn ratio of XFMR
t SW =
The maximum turn ration of XFRM should be designed
first, which is to ensure that the system should work in
DCM in all working conditions, especially at the minimum
input voltage and full load.
(13)
2 ⋅ Pin ⋅ η in
tSW, tONP and tONS in (7) are replaced with (13), (9) and (10),
2
Lp ⋅ I pk
2 ⋅ Pin ⋅ ηin
As we know, if the system can meet equation (7) at
minimum input voltage and full load, it can work in DCM
Sep. 2011
2
L p ⋅ I pk
Rev. 1. 0
≥ I pks ⋅
Lp
Ls
+ I pk ⋅
Vs
Vindc_min
(14)
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Application Note 1068
Because the peak current and inductance of primary side
and secondary side have the following relationship,
RCS =
(15)
I pks = N ⋅ I pk ⋅ η i
From now on, IPK and RCS have been designed.
Lp
N2
Step 2, Design Transformer
(16)
2-1. Calculate the inductance of primary side---LP
Here, N is the turn ratio of primary and secondary sides.
The primary side inductance LP is relative with the stored
energy. LP should be big enough to store enough energy, so
that PO_Max can be obtained from this system.
With (14), (15) and (16), then,
I pk
2 ⋅ Pin ⋅ηin
≥
ηi
VS ⋅ N
+
1
Vin
(17)
From formula (18), the output power can be given by,
Because,
Pin =
η
(18)
Then, LP can be gotten by,
At full load, the system will work in the boundary of CC
regulation. IO can be given by,
1 t ONS
⋅
⋅ I pks
2 t SW
(19)
(20)
2 ⋅ t SW
=5
t ONS
N=
(21)
k ⋅η
ηi
)
−
2 ⋅ VO ⋅ ηin ⋅ ηi VO + Vd
k ⋅ IO
(k = 5 )
I pk ⋅η i
(27)
2-3. Calculate the turns of primary, secondary and
auxiliary sides
First, the reasonable core-type and ∆B should be selected.
Then, the turns of 3-winding transformer can be obtained
respectively.
The following can be obtained,
N ≤ Vindc_min ⋅ (
(26)
2
PK
2-2. Re-calculate the turn ratio of primary and
secondary side---N
From formula (24), the turn ratio of primary and secondary
side N can be re-calculated.
In the design of AP3770,
k=
2 ⋅ PO ηin
⋅
I ⋅ f SW η
LP =
Then, IPKS can be defined,
I pks = k ⋅ I O
(22)
The turns of primary winding,
LP ⋅ I PK
Ae ⋅ ∆B
1-2. Calculate the peak current of primary side and
current sensed resistor
Np =
IPK can be calculated by the output current.
The turns of secondary winding,
I pk ⋅η i =
I pks
N
=
k ⋅ IO
N
(23)
NS =
(28)
NP
N
(29)
Here, k=5.
The turns of auxiliary winding,
In AP3770, 0.5V is an internal reference voltage. If the
sensed voltage VCS reaches 0.5V, the power transistor will
be shut down and tONP will be ended.
NA =
Sep. 2011
(25)
Where fSW was set by the user based on definite
requirement.
is the system efficiency.
IO =
1
η
2
⋅ L p ⋅ I pk
⋅ f SW ⋅
2
ηin
PO =
VO ⋅ I O
η
(24)
So RCS can be obtained from (24) and selected with a real
value from the standard resistor series. After RCS is
selected, IPK should be modified based on the selected RCS.
η i = 0.9 , which is the efficiency of IPK and IPKS. N is the
calculated value of Nmax.
Ls =
0.5V
I pk
Rev. 1. 0
N S ⋅ VA
VS
(30)
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Application Note 1068
Ae can be gotten automatically after core-type is selected.
Other setting by users:
Switching frequency: fSW=54kHz (Should be equal to or
higher than 54kHz)
Forward voltage of secondary diode: Vd=0.4V
Forward voltage of auxiliary diode: Vda=1.1V
VCC voltage: VCC=12V
Core_type: EE16 (Ae=19.2mm2)
Set ∆B : ∆B <3000GS
Vdc_spike=100V (with snubber circuit)
2-4. Check the maximum duty cycle of primary side
Design Steps:
After turn ratio of primary side and secondary side is
designed, the maximum duty cycle of primary side at low
line voltage can be calculated again.
Step 1, a reasonable IPK of FLYBACK with AP3770
should be designed.
Where VA=VCC+ Vda, VCC is the set IC supply voltage and
Vda is the voltage drop of the auxiliary diode.
For AP3770, the typical value of UVLO is decreased to
5.5V, so the supply voltage of IC，VCC can be set to a
typical value---12V.
VS is equal to VO+Vd.
1-1. Calculate the maximum turn ratio of XFMR
Considering the Volt-second balance between magnetizing
and de-magnetizing, the formula of duty cycle is
D=
k ⋅η
ηi
(35)
−
)(k = 5 )
2 ⋅ VO ⋅ ηin ⋅ ηi VO + Vd
= Vinac_min ⋅ 2 − 40 , η = 0.75 , ηin = 0.9 , ηi = 0.9
N MAX = Vindc_min ⋅ (
(VO + Vd ) ⋅ N ⋅ 0.4
Vindc
(31)
Vindc_min
N MAX ≈ 22
The turn ratio is finally selected as: N = 18.5
Step 3, Select diode and primary transistor
(36)
3-1. Select diodes of secondary and auxiliary sides
1-2. Calculate the peak current of primary side and
current sensed resistor
Maximum reverse voltage of secondary side，
Vdr = VO +
Vindc_max ⋅ N S
NP
(32)
k ⋅ IO
( ηi = 0.9 , which is the transfer
=
N
N
efficiency of Ipk and Ipks)
(33)
I pk_max = 330 mA
I pk ⋅η i =
Maximum reverse voltage of auxiliary side,
Vdar = V A +
Vindc_max ⋅ N A
NP
RCS =
3-2. Select the primary side transistor
VS ⋅ N P
NS
(37)
Sensed current resistor,
In (32) and (33), the maximum DC input voltage should be
used.
Vdc_max = Vdc_spike + Vindc_max +
I pks
VCS
0.5V
=
I pk _ max 359m
(39)
R CS ≈ 1.5Ω
(34)
(38)
Re-calculate peak current of primary side,
Be careful that the value of Vdc_spike will be different with
different snubber circuit.
(40)
I pk_max = 333mA
Design Example:
Specification:
Input voltage: 85VAC to 265VAC
Output voltage: VO=5.3V (Considering
compensation)
Output current: IO=1.1A
Efficiency: 80%
the
Step 2, Design Transformer
2-1. Calculate the inductance of primary side---LP
cable
LP =
L p = 2.035 mH
It is higher than the total efficiency because the loss in the
input rectifier and the BJT are not included.
Sep. 2011
2 ⋅ PO ηin
⋅
2
⋅ f SW η
I PK
Rev. 1. 0
(41)
(42)
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Application Note 1068
2-4. Check the maximum duty cycle of primary side
The maximum duty cycle of primary side is calculated as
following,
2-2. Re-calculate the turn ratio of primary and
secondary side---N
N=
k ⋅ IO
(k = 5 )
I pk ⋅η i
D=
(43)
(44)
N = 18.3
D |Vindc _ min =
2-3. Calculate the turns of primary, secondary and
auxiliary sides
The turns of primary winding,
Np =
(VO + Vd ) ⋅ N ⋅ 0.4
Vindc
LP ⋅ I PK
Ae ⋅ ∆B
N P > 118T
(VO + Vd ) ⋅ N ⋅ 0.4 (5.3 + 0.4) ⋅ 18.3 ⋅ 0.4
=
= 0.528
Vindc _ min
80
(45)
Step 3, Select diode and primary transistor
3-1. Select diodes of secondary and auxiliary sides
Maximum reverse voltage of secondary side，
(46)
Vdr = VO +
NP
(55)
Vindc_m ax = 265V ⋅ 2
N
NS = P
N
(47)
N S ≈ 7T
Vdr = 5.4 +
(48)
Vdar = V A +
(49)
N P ≈ 128T
(50)
Vdar
The turns of auxiliary winding,
N S ⋅V A
Vo + Vd
N A ≈ 15T
(56)
375
≈ 28V
17
(57)
Maximum reverse voltage of auxiliary side,
Recalculate the primary winding,
N P = NS ⋅ N
(54)
Vindc_max ⋅ N S
The turns of secondary winding,
NA =
(53)
Vindc_max ⋅ N A
NP
(58)
375 ⋅ 15
= 12 +
≈ 56V
128
(59)
3-2. Select primary side transistor
VS ⋅ N P
NS
(51)
Vdc_max = Vdc_spike + Vindc_max +
(52)
Vdc _ max = 100 + 375 + 5.4 * 17 ≈ 567V
(60)
(61)
Design Results Summary:
1.Calculate the maximum peak current of primary side and RCS
IPK=
333
mA
Peak current of primary side
RCS=
1.5
Current sensed resistor
Ω
2.Design transformer
LP=
2
mH(+/-8%)
Inductance of primary side
N=
17
Turn ratio of primary and secondary
NP=
128
T
Turns of primary side
NS=
7
T
Turns of secondary side
N A=
15
T
Turns of auxiliary side
DMAX
0.52
Maximum duty cycle of primary side at VINDC=80V
3. Select diode and primary transistor
Vdr=
28
V
Maximum reverse voltage of secondary diode
Vdar=
56
V
Maximum reverse voltage of auxiliary diode
VdcMax=
567
V
Voltage stress of primary transistor
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Application Note 1068
2.4 Feedback Resistors Design
Figure 6. Feedback Resistors Circuit
From above Figure 6,
(R + RFB 2 ) N S
Vo = VFB ⋅ FB1
⋅
− VD
RFB 2
NA
2.5 Line Compensation Design
The internal line compensation function in AP3770 is
shown in Figure 7. S1 is closed when the primary switch is
“ON”. The line voltage can be detected from the FB pin.
The detected voltage internally compensates the peak
current. So the line compensation is determined by RLINE.
In different application, the value of RLINE is different.
(62)
Through adjusting RFB1 and R FB2, a suitable output voltage
can be achieved. The recommended values of RFB1 and R
FB2 are within 5kΩ to 50kΩ.
Figure 7. Line Compensation Circuit
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Application Note 1068
tSW
FB
tONP
t
VN
tOFF
Figure 8. Waveform of FB Pin
So, RLINE can be adjusted to achieve excellent line
regulation of output current.
The negative voltage VN of FB pin (in Figure 8) is linear to
line voltage. The AP3770 samples VN to realize the line
compensation.
2.6 Dynamic Response
N
RFB 2
VN =
⋅ a ⋅ Vindc
RFB1 + RFB 2 N p
AP4340 is an output voltage detector for Primary Side
Control System which is U2 in Figure 1. Excellent
dynamic response can be achieved with AP4340. The
principle is AP4340 provides a periodical signal when
detecting the output voltage is lower than certain level. The
periodical signal can be coupled by the transformer to the
primary side, and provided as a switch-opening signal for
the main controller. By fast response to secondary side
voltage, AP4340 and AP3770 can effectively improve the
transient performance for Primary Side Control System.
(63)
The compensated voltage of line compensation (VCS_LINE)
can be calculated by the following formula,
1
⋅ VN
670k
N
RFB 2
1
= Rline ⋅ 0.8 ⋅
⋅
⋅ a ⋅ Vindc
670k RFB1 + RFB 2 N p
Vcs _ line = Rline ⋅ K ⋅
(64)
VO
VTRIGGER_4340
IPULSE
30kHz
AP4340
working
VFB
VPULSE
VTRIGGER_3770
tD
Figure 9. The Principle of AP4340 and AP3770
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Application Note 1068
transformer and bipolar. The AP3770 can’t differentiate the
ring signal and VPULSE generated by AP4340. The delay
time tD is set to avoid a false detection of such ring signal.
So the peak voltage ring should be much less than
VTRIGGER_3770 after tD in the design.
The detail is shown in Figure 9. When AP4340 detects the
output voltage is lower than VTRIGGER_4340, a pulse current
(IPULSE) will be generated. Then, a pulse voltage (VPULSE)
can be seen on the feedback winding coupling from the
transformer. When AP3770 detects VPULSE (>0.15V is
valid), it will provide a switch-opening signal for the
primary side. VPULSE will be valid again after a delay time
(tD), which is determined by AP3770. Any VPULSE in tD is
invalid.
3. Summary
In order to get good performance of AP3770, it’s important
to design transformer, line compensation and feedback
resistance correctly. This application only gives a
preliminary design guideline about these aspects and
considers ideal conditions, so some parameters need to be
adjusted slightly on the basis of the calculated results.
Notes: There is a ringing signal on FB waveform after
Schottky diode current finishes, which is caused by
magnetizing inductance and parasitic capacitance of
FB Waveform
Ringing signal higher
than VTRIGGER
VTRIGGER
tD
Figure 10. The Ring Signal of FB Pin
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