Datasheet
Multi-Channel Power Supply LSI Series for Car Electronics
Multi-channel Power Supply IC
for Car Audio Systems
BD49101AEFS-M
General Description
Key Specifications
The BD49101AEFS-M LSI is a multi-channel power
supply IC that can provide all necessary supply voltages
for automobile audio systems. The IC has two Switching
Power Supplies (DCDC), five Regulators (REG) and a
High Side switch. This single power supply system can
provide the required voltages to all systems including the
MCU, CD, tuner, USB, illumination, audio circuits and
others.
The IC system is based on switching regulator which
has high efficiency then you can suppress heat of IC
than before. And it has low power mode operation or
voltage control function so that you can get ①High
Efficiency ②Low IQ and ③easiness of power supply
design.
Input Voltage Range:
5.5V to 25V(VIN0=BCAP)
DCDC1(controller):
DCDC2(with low power mode for MCU):
1A
REG1(output voltage variable):
500mA
REG2(output voltage variable):
100mA
REG3(output voltage variable):
300mA
REG4(output voltage variable for USB):
1.5A
REG5(output voltage variable):
50mA
High side SW:
500mA
Standby Current:
100µA(Typ)
REG4 Over Current Detect Accuracy:
±20%
Operating Temperature Range:
-40°C to +85°C
200kHz to 500kHz
DCDC Switching Frequency:
Package
Features
HTSSOP-A44
W(Typ) x D(Typ) x H(Max)
18.50mm x 9.50mm x 1.00mm
(Note1)
AEC-Q100 Qualified
Integrated 7 channels of Power Supply for Car Audio
・2 DCDC (Integrated 1 Controller )
・5 REG
1 High Side Switch channel
Integrated Low Power Standby REG for MCU Power
Supply
REG4 Cable Impedance Compensation
2
I C Interface
Selectable Oscillation Frequency using External
Resistance
External Clock Synchronization
Power Supply Control Function (Power on/off
Sequencer).
Low Voltage, Over Voltage and REG4 Over Current
Detect Flag
Integrated Protection Circuitry:
・Over Voltage Input Protection
・Over Current Protection
・Thermal Shutdown
HTSSOP-A44
(Note1:Grade3)
Applications
Car audio and infotainment
○Product structure:Silicon monolithic integrated circuit ○This product is not designed for protection against radioactive rays
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Pin Configuration
VOUT5
ADJ5
VIN0
EN
BCAP
REG4EN
VINSW
ECO
BSENS
N.C.
HSW
REG4 OCB
GND4
SDA
SW2
SCL
FB2
SYNC
INV2
GND1
VOUT0
RT
VIN1
GND2
ADJ1
VOUT3
VOUT1
ADJ3
ADJ2
VIN3
VOUT2
VIN4
GND3
CLCAL
N.C.
VOCAL
VIN2
ADJ4
SNSH
VOUT4
SNSL
INV1
GATE1
FB1
Figure 1. Pin Configuration(s)
Pin Description
Pin
NO
1
REG5 voltage output
Pin
NO
23
VIN0
Battery power supply connection pin
3
BCAP
4
VINSW
5
N.C.
6
HSW
7
Symbol
Symbol
Function
FB1
DCDC1 Error Amp output
24
INV1
DCDC1 Error Amp Input
Back-up capacity connection pin
25
VOUT4
Power supply for high side switch
26
ADJ4
27
VOCAL
High side switch output
28
CLCAL
GND4
Ground
29
VIN4
Power supply for built-in FET REG4
8
SW2
DCDC2 switching output
30
VIN3
Power supply for built-in FET REG3
9
FB2
DCDC2 Error Amp output
31
ADJ3
REG3output voltage adjustment
10
INV2
DCDC2 Error Amp Input
32
VOUT3
REG3 voltage output
Ground
2
VOUT5
Function
－
REG4 voltage output
REG4 output voltage adjustment
REG4 output USB cable impedance
calibration setting
REG4 over current protection setting
11
VOUT0
STBREG voltage output
33
GND2
12
VIN1
Power supply for built-in FET REG1
34
RT
13
ADJ1
REG1 output voltage adjustment
35
GND1
Ground
14
VOUT1
REG1 voltage output
36
SYNC
External synchronization signal input
15
ADJ2
REG2 output voltage adjustment
37
SCL
I C-bus clock input
16
VOUT2
REG2 voltage output
38
SDA
I C-bus data input
17
GND3
Ground
39
REG4OCB
Error flag output
18
N.C.
40
BSENS
Error flag output
19
VIN2
Power supply for built-in FET REG2
41
ECO
20
SNSH
DCDC1 current detection
42
REG4EN
21
SNSL
DCDC1 current detection
43
EN
22
GATE1
DCDC1 outside FET gate drive
44
ADJ5
－
Oscillation frequency setting
2
2
Low power mode switch
REG4 Enable
Enable
REG5 output voltage adjustment
“N.C” pins are not connected into internal circuits.
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Block Diagram
SNSH
20
TSD
SYNC
Ext CLK
RT
36
34
DCDC1
(Controller)
OSC
21
SNSL
22
GATE1
output
FB1
23
INTERNAL
REGULATOR
VIN0
24
2
DCDC1
INV1
SW2
8
DCDC2
output
BCAP
9 FB2
3
DCDC2
BCLDET
/BCOVP
VIN2
REG2
output
10
INV2
11
19
VOUT0
STB_REG
VOUT2
16
ADJ2
15
REG2
LDET/OVP
12
REG5
VOUT5
14
1
output
ADJ5
44
REG1
REG5
13
VINSW
4
Hi-side SW
6
output
HSW
30
Hside
SW
32
REG3
31
BSENS
REG4OCB
ECO
EN
REG4EN
40
29
39
25
41
26
43
REG4
42
VIN1
VOUT1
ADJ1
REG1
output
VIN3
VOUT3
ADJ3
REG3
output
VIN4
VOUT4
ADJ4
REG4
output
VOCAL
(calibrate) 27
SDA
SCL
38
37
I2C I/F
35
GND1
・Each ch on/off
・LDET setting
28
CLCAL
33
17
7
GND2 GND3 GND4
Figure 2. Block Diagram
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Description of Blocks
・DCDC2 – STBREG switch function
The ECO input is used to switch between operating mode and low power standby mode.
(This function is for a 3.3V I/O microcomputer because of the 3.3V fixed STBREG output)
The function of the ECO input is as follows:
ECO = H – Normal Operating Mode (DCDC2 operating).
ECO = L – Low Power Standby mode (STBREG operating).
・Sequence of VIN0 start up, Low Power Standby mode
VIN0
8.3V
BCAP
4.7V
①
Soft start
Max 5ms
DCDC2/
STBREG
=VIN1
REG1
STBREG
DCDC2
DCDC2
STBREG
1.25V
1.25V
②
ECO
BSENS
EN
ACK
SCL
SDA
Slave Address A
Figure 3. Timing Chart of VIN0 start up, Low Power Standby mode
①
When BD49101AEFS starts up, it starts in the normal operation mode (DCDC2 operation), independent of ECO
setting. An internal regulator, the reference voltage circuit, and the OSC circuit start up when the voltage of the
BCAP pin exceeds low voltage protection release voltage (4.7V).
2
② Following the first access to the I C interface, the ECO input is able to control the operating mode (normal or low
2
power standby). ECO must be set to the desired operating mode prior to accessing the I C interface for the first
time.
③ The conditions of independent of ECO setting is shown below.
Input power supply for VIN0 at the first time
BCAP voltage becomes under 4.5V
DCDC2 detects over current and DCDC2 restarts
2
At each condition ECO setting become effective after you send I C command and receive ACK.
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・Relation of BCAP voltage and operating mode
When the voltage of the BCAP pin decreases under BCAP low voltage detection voltage (4.5V),
the registers are initialized and the ECO pin setting becomes invalid and forcibly changed to low power mode.
Afterwards, when BCAP voltage increases over BCAP low detection release voltage (4.7V)
without under POWER ON reset voltage (3.1V), the mode change to DCDC2 mode. (ECO pin setting is invalid.)
If BCAP voltage increases with under POWER ON reset voltage, the operation is same as VIN0 start up.
BCAP voltage
4.7V
4.5V
BCLDET release
BCLDET detect
3.1V
POWER_ON reset voltage
0V
μ-con 3.3V supply
voltage
DCDC2
OFF
STBREG
DCDC2
STBREG
OFF
DCDC2
Figure 4. Relation of BCAP voltage and operating mode
・Mode changing (Normal operation mode ⇔ low power mode)
When the ECO pin is changed from 0V to 3.3V, it changes from the low power mode to the normal operation mode.
When it changes from the low power mode to the normal operation mode, the output voltage drops according to the
load current. (Figure 5)
(ex.) ：Supply voltage 14.4V, output capacitor 100uF, load current 200mA : Output drop voltage=-80mV(Typ)
We recommend that you save consumption current of the microcomputer in 200mA within 1ms when the mode is
changed to normal operation mode (Figure 6).
3.3V
ECO
0V
3.3V
VOUT0
～80mV
（Output Capa=100uF,Load Current 200mA）
Figure 5. Timing Chart of mode changing (Normal operation mode ⇔ low power mode)
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more than 1ms
μ-con
consumption
200mA
0mA
3.3V
ECO voltage
0V
Low power mode
normal operation mode
Figure 6. Image of increasing consumption current when switching
from low power mode to normal operation mode
USB Supply calibration (REG4).
The VOCAL input is used to adjust for cable impedance between the supply and USB connector. This
adjustment will correct for voltage drop across the cable as a function of the current flow thus maintaining a
constant voltage at the connector. Compensation of up to 0.5Ω of cable impedance can be achieved.
The CLCAL input is used to set the over current threshold, up to a maximum of 1.5A.Please refer 2-(3)-②
Setting of cable impedance calibration
REG1 to 5, STBREG
Current at
shorted
VOUT
VOUT
Over Current Protection (OCP)
All regulators and high side switch have over current protection. When OCP is detected, the following
conditions will apply:
DCDC1: After disabled for a certain period, it will attempt to restart automatically.
DCDC2 : After disabled for a certain period, it will attempt to restart automatically
and the register will be initialized.
REG4 – Current limit circuit will operate and REG4OCB is activated (Low).
Other regulators and a high side switch – Current limit circuit will operate.
High side switch
Current at
shorted
IOUT
IOUT
Figure 7. Reg, High side switch example of the characteristics about Output voltage- Output current
Battery voltage monitoring function and BSENS output
The BSENS output is active (High) when over voltage protection(OVP) is active. OVP becomes active when
VIN0 exceeds 20.2V(Typ) OVP is cleared when VIN0 falls below 18.2V(Typ).
BSENS is also active (High) when VIN0 falls below 7.8V(Typ, initial register condition), afterwards BSENS is
cleared when VIN0 exceeds 8.3V (Typ, initial register condition).
This low detection(LDET) voltage can change from 5.7V to 6.4V, and from 7.7V to 8.4V with writing register
(Initial setting is 7.8V).
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VIN0 Voltage
20.2V
18.2V
Variable in15 steps
by I2 C register setting
8.3V
7.8V
LDET detect→H
3.3
LDET detect→H
OVP detect→H
BSENS
0
Figure 8. Timing Chart of OVP/LDET detection
REG4OCB Output
3.3V
REG4EN
0V
5.2V
VOUT4
0V
TSS4
3ms(typ)
Soft start time
short output
short output
short output
OCP threshold
IOCP(variable)
IOUT4
1.5A
(Load current =1.5A)
0A
3.3V
short current
(100mA typ)
OCP delay time
TDELAY4
13.7ms(typ)
short current
(100mA typ)
13.7ms(typ)
REG4OCB
0V
Figure 9. Timing Chart of REG4OCB output
REG4 starts by a soft start in 3ms(Typ). And when detecting over current detection the REG4OCB output is
active (Low) after 13.7ms continuous over current condition.
External Synchronization
The SYNC input is used to synchronize the switching frequency of DCDC1 and DCDC2. A signal in the
range of 200kHz – 500kHz can be input. The input signal must be at a higher frequency than that set by the
resistor on RT input and should be configured between 0.6 to 1.5 times the set frequencies.(when SYNC
Duty=45 to 55%)
When it changes from internal oscillation mode to external synchronization mode, it changes after it is inputted
continuously 3 pulses.
When it changes from external synchronization mode to internal oscillation mode, it changes within a period of
internal oscillation frequency after SYNC input sets L. When SYNC input sets H, it doesn’t change to internal
oscillation mode.
At first applying of power on VIN0(BCAP), SYNC pin must be under “input L level” max value until VODC2
rises up. If it is not so, the IC could not start normally.
It can adjust to the phase of switching pulse between DCDC1 and DCDC2 by the duty of SYNC input.
The switching positive edge timing of DCDC1,2 is below.
DCDC1: synchronized the negative edge of SYNC input.
DCDC2 : synchronized the positive edge of SYNC input
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Enable Inputs
The EN input controls the output of the high side switch and regulators with the exception of DCDC2-STBREG
and REG1. REG4 can also be controlled independently with the REG4EN input.
OUTPUTS
Input pin
Register
EN
STBREG
DCDC2
REG1
－
－
－
L=STBREG
H=DCDC2
ECO
－
REG4EN
－
DCDC1
REG2,3,5
REG4
HSW
L=OFF
need resetting when turning ON
Reset(input"L")
－
－
－
－
－
－
－
－
－
L=OFF
H=ON
－
－
Figure 10. Table of EN control
2
I C Interface
2
The I C interface allows access to the internal registers. The internal registers are used for the following
functions:
Enable the high side switch and power supplies except for DCDC2-STBREG.
Setting LDET – VIN0 low voltage detection threshold.
Detecting high side switch over current condition (address 0x04)
For Protect and Detect Functions and Enable Function
OUTPUTS
ERROR flag
Register
over
current
detection
STBREG
DCDC2
REG1
DCDC1
REG2,3,5
REG4
HSW
BSENS
REG4OCB
STBREG
fold back
limit
－
－
－
－
－
－
－
－
DCDC2
－
restart
(Note 1)
－
－
－
Reset
－
REG1
－
－
fold back
limit
DCDC1
－
－
－
REG2,3,5
REG4
tharmal
power
supply
voltage
detection
－
－
－
－
－
(Note 1)
－
－
－
－
－
－
restart
(Note 1)
－
－
－
－
－
－
－
fold back
limit
－
－
－
－
－
－
fold back
limit
－
○
－
－
－
－
－
－
－
○
－
－
－
－
－
－
TSD
－
－
－
LDET
－
－
－
－
－
－
－
OVP
－
－
－
－
－
－
－
－
OFF
(Note 1)
－
－
Reset
－
OFF(Note 2)
－
－
－
BCLDET
ON
OFF
(Note 3)
(Note 3)
－
－
－
－
－
fold back
limit
HSW
BCOVP
(Note 1)
(Note 2)
(Note 3)
(Note 4)
－
OFF
(Note 5)
－
OFF(Note 2)
When detecting each output is limited in minimum duty and dropping output and INV voltage then restarts after 1024clk.
When detecting each output doesn’t restart.
When detecting each output restarts.
When detecting BCAP low voltage the operation mode switches to standby mode without depending on the ECO setting.
Figure 11. Table of EN Protect and Detect Functions
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Absolute Maximum Ratings(Ta=25°C)
Parameter
Symbol
Limits
Unit
Power Supply Voltage (PIN2,4,19)
VCC
-0.3 to +42
V
Input Voltage (PIN37,38,41-43)
Vin
-0.3 to +7
V
Pin Voltage 1(PIN1,3,6,8,16,22)
VPIN1
-0.3 to +42
V
Pin Voltage 2(PIN20,21)
VPIN2
VIN0 – 7 to VIN0
V
Pin Voltage 3(PIN9-15,23-32,34,36,39,40,44)
VPIN3
-0.3 to +7
V
Operating Temperature Range
Topr
-40 to +85
°C
Storage Temperature Range
Tstg
-55 to +150
°C
Power Dissipation
Pd
Maximum Junction Temperature
Tjmax
6.19
(Note 1)
W
150
3
°C
2
(Note 1) Reduce by 49.5mW/°C, when mounted on 4-layer PCB of 70x70x16mm (Copper foil area on the reverse side of PCB: 70x70mm ).
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated
over the absolute maximum ratings.
Recommended Operating Ratings
Parameter
Symbol
Limits
Unit
VINopr
5.5 to 25
V
Output Voltage Range 1(DCDC1/2)
VOUTopr1
0.8 to VINopr
V
Output Voltage Range 2(REG1/3/4)
VOUTopr2
Output Voltage Range 3(REG2/5)
VOUTopr3
Operating Power Supply Voltage1(VIN0,BCAP)
0.8 to 2.4
(REG1)
0.8 to VIN3,4 - VSATRG3,4
(REG3.4)
0.8 to 10.5 (REG2)
0.8 to 8.5
(REG5)
V
V
Oscillating Frequency
fSW
200 to 500
kHz
Oscillating Frequency Set Resistance
RT
27 to 82
kΩ
External Sync Frequency
fCLK
200 to 500
kHz
External Synchronization Pulse Duty
DCLK
20 to 80
%
REG4 Over Current Detection Set Resistance
RCLCAL
5 to 50
kΩ
REG4 Cable Impedance Compensation Set Resistance
RVOCAL
0 to 230
Ω
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Electrical Characteristics
(Unless otherwise specified, Ta= 25°C, VIN0=BCAP=14.4V, EN=3.3V, VOUT1=1.25V, VOUT2=5.78V, VOUT3=3.3V,
VOUT4=5.2V, VOUT5=5.0V)
Spec Values
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
【Consumption Current】
ISTB
－
100
150
μA
ECO=0V, EN=0V
IQ
－
5.0
7.5
mA
ECO=3.3V, EN=3.3V, Io=0A
ENABLE=0x7F
Detection Threshold Voltage
VOVPON
18.2
20.2
22.2
V
Release Threshold Voltage
VOVPOFF
16.2
18.2
20.2
V
Detection Threshold Voltage
VLDETON
7.5
7.8
8.1
V
Release Threshold Voltage
VLDETOFF
8.0
8.3
8.6
V
FOSC
285
300
315
kHz
VREF1_DC1
0.784
0.800
0.816
V
Over current Detection
Threshold voltage
VOCP_TH_DC1
-
0.1
-
V
SNSH-SNSL
Maximum FB1 Voltage
VFB1H
-
3.0
-
V
INV1=0V
Minimum FB1 Voltage
VFB1L
-
0.8
-
V
INV1=2V
IFB1SINK
-800
-400
-200
µA
FB1=1V, INV1=1V
IFB1SOURCE
50
100
200
µA
FB1=1V, INV1=0.6V
Maximum GATE1 Voltage
VGT1H
-
-
VIN
+0.3V
V
INV1=2V
Minimum GATE1 Voltage
VGT1L
8.1
-
-
V
INV1=0V
Soft Start
TSS1
-
-
5
ms
VREF1_DC2
0.784
0.800
0.816
V
Output Current Capacity
IODC2
1
-
-
A
Maximum FB2 Voltage
VFB2H
-
3.0
-
V
INV2=0V
Minimum FB2 Voltage
VFB2L
-
0.8
-
V
INV2=2V
IFB2SINK
-800
-400
-200
µA
FB2=1V, INV2=1V
IFB2SOURCE
50
100
200
µA
FB2=1V, INV2=0.6V
TSS2
-
-
5
ms
RON
125
250
500
mΩ
Standby Current
Circuit Current
【Over Voltage Detection】
【Low Voltage Detection】
LDET_SETTING=0x09
【OSC】
Oscillating Frequency
RT=51kΩ
【DCDC1】
Reference Voltage
FB1 Sink Current
FB1 Source Current
【DCDC2】
Reference Voltage
FB2 Sink Current
FB2 Source Current
Soft Start
Power MOS FET ON
Resistance
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Parameter
Symbol
Spec Values
Unit
Conditions
Min
Typ
Max
VREF_STLD
3.234
3.300
3.366
V
IOSTLD
200
-
-
mA
Line Regulation
⊿VISTLD
-
-
15
mV
VIN0=7 to 18V, Io=5mA
Load Regulation
⊿VLSTLD
-
-
30
mV
IO=5m to 200mA
Ripple Rejection
RRSTLD
-
70
-
dB
Frp=100Hz, VIN0rp=1Vpp
VSATSTLD
-
-
0.6
V
IO=100mA
VREF_LD1
0.588
0.600
0.612
V
IOLD1
500
-
-
mA
VIN1=3.3V
Line Regulation
⊿VILD1
-
-
10
mV
VIN1=3 to 6V, Io=5mA
Load Regulation
⊿VLLD1
-
-
20
mV
IO=5m to 500mA
Ripple Rejection
RRLD1
-
70
-
dB
Frp=100Hz, VIN1rp=1Vpp
VSATLD1
-
-
1.0
V
IO=250mA
VREF_LD2
0.777
0.793
0.809
V
IOLD2
100
-
-
mA
Line Regulation
⊿VILD2
-
-
25
mV
VIN2=9 to 18V, Io=5mA
Load Regulation
⊿VLLD2
-
-
50
mV
IO=5mA to 100mA
Ripple Rejection
RRLD2
-
70
-
dB
Frp=100Hz, VIN2rp=1Vpp
VSATLD2
-
-
0.65
V
IO=50mA
VREF_LD3
0.784
0.800
0.816
V
IOLD3
300
-
-
mA
VIN3=6V
Line Regulation
⊿VILD3
-
-
20
mV
VIN3=4.0 to 6.5V, Io=5mA
Load Regulation
⊿VLLD3
-
-
40
mV
IO=5m to 300mA
Ripple Rejection
RRLD3
-
70
-
dB
Frp=100Hz, VIN3rp=1Vpp
VSATLD3
-
-
0.6
V
IO=150mA
【STBREG】
Reference Voltage
Load Current Capacity
I/O Voltage Difference
【REG1】
Reference Voltage
Load Current Capacity
I/O Voltage Difference
【REG2】
Reference Voltage
Load Current Capacity
I/O Voltage Difference
【REG3】
Reference Voltage
Load Current Capacity
I/O Voltage Difference
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TSZ02201-0V3V0AP00060-1-2
06.Apr.2015 Rev.001
BD49101AEFS-M
Parameter
Spec Values
Symbol
Unit
Conditions
Min
Typ
Max
VREF_RG4
0.784
0.800
0.816
V
IORG4
1.5
－
－
A
Line Regulation
⊿VIRG4
－
－
50
mV
VIN4=5.6 to 6.5V, Io=5mA
Load Regulation
⊿VLRG4
－
－
40
mV
Io=5m to 1.5A
Ripple Rejection
RRRG4
－
55
－
dB
Frp=100Hz, VIN4rp=1Vpp
VSATRG4
－
－
0.4
V
Io=1.5A
IOCP1
1.18
1.47
1.76
A
IOCP2
534
667
800
mA
Vcal
5.32
5.46
5.60
V
TSS4
－
3
－
ms
TDELAY4
8.7
13.7
18.7
ms
VREF_RG5
0.784
0.800
0.816
V
IORG5
50
－
－
mA
Line Regulation
⊿VIRG5
－
－
25
mV
VIN0=9 to 18V, Io=5mA
Load Regulation
⊿VLRG5
－
－
50
mV
Io=5mA to 50mA
Ripple Rejection
RRRG5
－
70
－
dB
Frp=100Hz, VIN5rp=1Vpp
VSATRG5
－
－
0.65
V
Io=25mA
IOSW1
500
-
-
mA
RON_SW1
－
-
3
Ω
【REG4】
Output Voltage
Load Current Capacity
I/O Voltage Difference
Over current Detection
Threshold 1
Over current Detection
Threshold 2
Voltage Adjusted For Cable
Impedance(0.26Ω)
Soft Start Time
OCP Delay Time
VIN4=6V,VOCAL=0Ω
VIN4=6V, CLCAL=6.8kΩ,
VOCAL=0Ω
VIN4=6V, CLCAL= 15kΩ,
VOCAL=0Ω
VIN4=6.5V,Io=1.0A,
VOCAL=120Ω
fsw = 300kHz
【REG5】
Reference Voltage
Load Current Capacity
I/O Voltage Difference
【High Side SW】
Output Current Capacity
ON Resistance
IO=500mA
【Digital IO】
(EN,REG4EN,ECO,SYNC,BSENS,REG4OCB)
For pin EN, REG4EN,
ECO,SYNC
For pin EN, REG4EN,
ECO,SYNC
Input H level
VIH
2.6
-
-
V
Input L level
VIL
-
-
0.8
V
Input pulldown Resistance1
RIND1
－
100k
－
Ω
For pin REG4EN, ECO,SYNC
Input pulldown Resistance2
RIND2
－
660k
－
Ω
For pin EN
Output H level
VOH
2.6
-
-
V
Output L level
VOL
-
-
0.8
V
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For pin BSENS,REG4OCB
IO=1mA
For pin BSENS,REG4OCB
IO= -1mA
TSZ02201-0V3V0AP00060-1-2
06.Apr.2015 Rev.001
BD49101AEFS-M
200
200
150
150
Standby Current[μA]
Standby Current[μA]
Typical Performance Curves(reference)
100
100
50
50
0
0
-20
0
20
40
60
80
0
5
10
15
20
25
Ambient Temperature:Ta[°C]
Input Voltage:VIN[V]
Figure 12. Standby Current vs Temperature
Figure 13. Standby Current vs Input Voltage
8
8
7
7
6
6
Circuit Current:ICC[mA]
Circuit Current:ICC[mA]
-40
5
4
3
5
4
3
2
2
1
1
0
0
-40
-20
0
20
40
60
80
0
Ambient Temperature:Ta[°C]
10
15
20
25
Input Voltage:VIN[V]
Figure 14. Circuit Current vs Temperature
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Figure 15. Circuit Current vs Input Voltage
13/41
TSZ02201-0V3V0AP00060-1-2
06.Apr.2015 Rev.001
315
0.816
312
0.812
309
Reference Voltage:VREF[V]
Oscillating Frequency:fosc[kHz]
BD49101AEFS-M
306
303
300
297
294
0.808
0.804
0.8
0.796
0.792
291
0.788
288
RT=51kΩ
0.784
285
-40
-20
0
20
40
60
-40
80
-20
0
20
40
60
80
Ambient Temperature:Ta[℃]
Ambient Temperature:Ta[°C]
Figure 16. Oscillating Frequency vs Temperature
Figure 17. DCDC1 Reference Voltage vs Temperature
6.09
100
90
6.06
Output Voltage:Vo[V]
80
Efficiency[%]
70
60
50
40
30
20
6.00
5.97
5.94
VIN0 =14.4V
VO=6.0V
f=300kHz
10
6.03
VIN0 =14.4V
VO=6V
0
5.91
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
Output Current:lo[A]
1.0
1.5
2.0
2.5
3.0
Output Current:lo[A]
Figure 18. DCDC1 Efficiency vs Output Current
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Figure 19. DCDC1 Output Voltage vs Output Current
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06.Apr.2015 Rev.001
BD49101AEFS-M
0.816
100
90
80
0.808
70
Efficiency[%]
Reference Voltage:VREF[V]
0.812
0.804
0.800
0.796
60
50
40
30
0.792
20
0.788
VIN0=14.4V
VO=3.3V
f=300kHz
10
0.784
0
-40
-20
0
20
40
60
80
0.0
0.2
Ambient Temperature:Ta[°C]
0.4
0.6
0.8
1.0
Output Current:lo[A]
Figure 20. DCDC2 Reference Voltage vs Temperature
Figure 21. DCDC2 Conversion Efficiency vs Output Current
3.42
525
475
ON Resistance:Ron[mΩ]
Output Voltage:Vo[V]
3.40
3.38
3.36
425
375
325
275
225
3.34
175
VIN0=14.4V
f=300kHz
Io=800mA
3.32
125
0.0
0.2
0.4
0.6
0.8
1.0
-40
Output Current:lo[A]
0
20
40
60
80
Ambient Temperature:Ta[°C]
Figure 22. DCDC2 Output Voltage vs Output Current
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Figure 23. DCDC2 FETON Resistance vs Temperature
15/41
TSZ02201-0V3V0AP00060-1-2
06.Apr.2015 Rev.001
BD49101AEFS-M
525
3.366
Reference Voltage:VREF[V]
ON Resistance:Ron[mΩ]
475
425
375
325
275
3.344
3.322
3.300
3.278
225
3.256
175
Io=800mA
3.234
125
0
5
10
15
20
-40
25
-20
0
20
40
60
80
Ambient Temperature:Ta[°C]
Input Voltage:VIN[V]
Figure 24. DCDC2 FETON Resistance vs Input Voltage
Figure 25. STBREG Reference Voltage vs Temperature
3.50
90
Io=5mA
80
Ripple Rejection:RR[dB]
Output Voltage:Vo[V]
3.00
2.50
2.00
1.50
1.00
Io=20mA
70
60
50
40
30
Io=200mA
20
0.50
VIN0 =14.4V
Vrp=1Vpp
10
0.00
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
1k
10k
100k
Frequency:f[Hz]
Output Current:lo[A]
Figure 26. STBREG Output Voltage vs Output Current
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Figure 27. STBREG Ripple Rejection vs Frequency
TSZ02201-0V3V0AP00060-1-2
06.Apr.2015 Rev.001
BD49101AEFS-M
3.5
0.612
0.608
Reference Voltage:VREF[V]
Output Voltage:Vo[V]
3.0
2.5
2.0
1.5
1.0
0.604
0.600
0.596
0.592
0.5
Io=100mA
0.0
0.588
0
5
10
15
20
25
-40
Input Voltage:VIN[V]
-20
0
20
40
80
Ambient Temperature:Ta[°C]
Figure 28. STBREG Output Voltage vs Input Voltage
Figure 29. REG1 Reference Voltage vs Temperature
90
1.4
VIN1 =3.3V
Vrp=1Vpp
80
Ripple Rejection:RR[dB]
1.2
Output Voltage:Vo[V]
60
1.0
0.8
0.6
0.4
70
60
50
Io=5mA
40
Io=100mA
30
20
0.2
10
VIN1=3.3V
VO=1.25V
Io=1000mA
0
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1k
10k
100k
Frequency:f[Hz]
Output Current:lo[A]
Figure 30. REG1 Output Voltage vs Output Current
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Figure 31. REG1 Ripple Rejection vs Frequency
TSZ02201-0V3V0AP00060-1-2
06.Apr.2015 Rev.001
BD49101AEFS-M
0.816
2.0
Reference Voltage:VREF[V]
Output Voltage:Vo[V]
0.812
1.5
1.0
0.808
0.804
0.800
0.796
0.792
0.5
VO=1.25V
Io=250mA
0.788
0.784
0.0
0
1
2
3
4
5
6
-40
7
0
20
40
60
80
Ambient Temperature:Ta[°C]
Input Voltage:VIN[V]
Figure 32. REG1 Output Voltage vs Input Voltage
Figure 33. REG1 Reference Voltage vs Temperature
10
90
9
80
8
70
Ripple Rejection:RR[dB]
Output Voltage:Vo[V]
-20
7
6
5
4
3
Io=5mA
60
50
Io=10mA
40
30
Io=100mA
20
2
VIN2 =14.4V
Vrp=1Vpp
10
VIN2=14.4V
VO=8.8V
1
0
0
0.00
0.05 0.10
0.15 0.20
0.25 0.30
0.35
100
1k
10k
100k
Output Current:lo[A]
Frequency:f[Hz]
Figure 34. REG2 Output Voltage vs Output Current
Figure 35. REG2 Ripple Rejection vs Frequcenty
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BD49101AEFS-M
0.816
10
0.812
Reference Voltage:VREF[V]
Output Voltage:Vo[V]
8
6
4
0.808
0.804
0.800
0.796
0.792
2
0.788
VO=8.8V
Io=50mA
0.784
0
0
5
10
15
20
-40
25
0
20
40
60
80
Ambient Temperature:Ta[°C]
Input Voltage:VIN[V]
Figure 36. REG2 Output Voltage vs Input Voltage
Figure 37. REG3 Reference Voltage vs Temperature
90
3.5
80
Ripple Rejection:RR[dB]
3.0
Output Voltage:Vo[V]
-20
2.5
2.0
1.5
1.0
70
Io=5mA
60
50
40
30
Io=30mA
Io=300mA
20
0.5
10
VIN3=6V
VO=3.3V
0.0
VIN3 =6V
Vrp=1Vpp
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1k
10k
100k
Frequency:f[Hz]
Output Current:lo[A]
Figure 38. REG3 Output Voltage vs Output Current
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Figure 39. REG3 Ripple Rejection vs Frequency
TSZ02201-0V3V0AP00060-1-2
06.Apr.2015 Rev.001
BD49101AEFS-M
6.0
0.816
5.5
0.812
Reference Voltage:VREF[V]
Output Voltage:Vo[V]
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
0.808
0.804
0.800
0.796
0.792
1.0
0.788
VO=3.3V
Io=150mA
0.5
0.0
0.784
0
1
2
3
4
5
6
7
-40
Input Voltage:VIN[V]
-20
0
20
40
60
80
Ambient Temperature:Ta[°C]
Figure 40. REG3 Output Voltage vs Input Voltage
Figure 41. REG4 Reference Voltage vs Temperature
6
90
VIN4=6V
Vrp=1Vpp
80
Ripple Rejection:RR[dB]
Output Voltage:Vo[V]
5
4
3
2
Io=5mA
60
50
Io=150mA
40
30
Io=1500mA
20
VIN4=6V
VO=5.2V
CLCAL=6.8kΩ
VOCAL=0Ω
1
70
10
0
0
0.0
0.4
0.8
1.2
1.6
1k
10k
100k
Frequency:f[Hz]
Output Current:Io[A]
Figure 42. REG4 Output Voltage vs Output Current
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Figure 43. REG4 Ripple Rejection vs Frequency
TSZ02201-0V3V0AP00060-1-2
06.Apr.2015 Rev.001
BD49101AEFS-M
6.0
5.19
5.5
5.17
4.5
Output Voltage:Vo[V]
Output Voltage:Vo[V]
5.0
4.0
3.5
3.0
2.5
2.0
1.5
5.15
5.13
5.11
5.09
5.07
1.0
5.05
Io=1.5A
RVOCAL=0Ω
0.5
0.0
VIN4=6V
RVOCAL=120Ω
5.03
0
1
2
3
4
5
6
7
0.0
0.5
Input Voltage:VIN[V]
1.5
Output Current:lo[A]
Figure 44. REG4 Output Voltage vs Input Voltage
Figure 45. Voltage Adjusted For Cable Impedance
vs Output Current
0.816
6
0.812
5
0.808
Output Voltage:Vo[V]
Reference Voltage:VREF[V]
1.0
0.804
0.800
0.796
4
3
2
0.792
1
0.788
VIN5=14.4V
VO=5V
0.784
0
-40
-20
0
20
40
60
80
0.00
Ambient Temperature:Ta[°C]
0.04
0.06
0.08
0.10
0.12
Output Current:lo[A]
Figure 46. REG5 Reference Voltage vs Temperature
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Figure 47. REG5 Output Voltage vs Output Current
TSZ02201-0V3V0AP00060-1-2
06.Apr.2015 Rev.001
BD49101AEFS-M
90
6.0
5.5
80
Output Voltage:Vo[V]
Ripple Rejection:RR[dB]
5.0
70
Io=5mA
60
50
Io=10mA
40
30
20
Io=50mA
10
VIN5=14.4V
Vrp=1Vpp
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Io=25mA
0.0
0
100
1k
10k
0
100k
5
Frequency:f[Hz]
10
15
20
25
Input Voltage:VIN[V]
Figure 48. REG5 Ripple Rejection vs Frequency
Figure 49. REG5 Output Voltage vs Input Voltage
3.0
16
ON Resistance:Ron[Ω]
Output Voltage:Vo[V]
14
12
10
8
6
2.5
2.0
1.5
4
2
VIN0=14.4V
VIN0=14.4V
1.0
0
0
200
400
600
800
1000
1200
Output Current:lo[mA]
-20
0
20
40
60
80
Ambient Temperature:Ta[°C]
Figure 50. HSW Output Voltage vs Output Current
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Figure 51. HSW ON Resistance vs Input Voltage
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BD49101AEFS-M
ON Resistance:Ron[Ω]
3.0
2.5
2.0
1.5
1.0
0
5
10
15
20
25
Input Voltage:VIN[V]
Figure 52. HSW ON Resistance vs Input Voltage
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BD49101AEFS-M
2
I C-bus Block
(1) Electrical specifications and timing for bus lines and I/O stages
SDA
tBUF
tLOW
tHD;STA
T
tF
tR
tSP
SCL
tHD;STA
P
tHD;DAT
tHIGH
tSU;DAT
S
tSU;STO
T
tSU;STA Sr
T
P
2
Figure 53. Definition of timing on the I C-bus
2
Table 1. Characteristics of the SDA and SCL bus lines for I C-bus devices
(Unless specified particularly, Ta=25°C, VIN0=14.4V)
2
Parameter
1
2
Symbol
Unit
kHz
μs
4
5
6
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition. After this period, the first clock
pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
7
Data hold time:
tHD;DAT
(Note 1)
－
μs
8
9
Data set-up time
Set-up time for STOP condition
tSU;DAT
tSU;STO
120
0.6
－
－
ns
μs
3
fSCL
tBUF
Fast-mode I C-bus
Min
Max
400
0
1.3
－
tHD;STA
0.6
－
μs
tLOW
tHIGH
tSU;STA
1.3
0.6
0.6
0.06
－
－
－
μs
μs
μs
All values referred to VIH min. and VIL max. Levels (see Table 2).
(Note 1) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min. of the SCL signal) in order to bridge the
undefined region of the falling edge of SCL.
About 7(tHD;DAT), 8(tSU;DAT), make it the setup which a margin is fully in .
2
Table 2. Characteristics of the SDA and SCL I/O stages for I C-bus devices
Parameter
10
11
12
13
14
Symbol
LOW level input voltage:
HIGH level input voltage:
Pulse width of spikes which must be suppressed by the input filter.
LOW level output voltage: at 3mA sink current
Input current each I/O pin with an input voltage between 0.4V and 4.5V.
ｔHD;STA
：2us
ｔHD;DAT
：1us
VIL
VIH
tSP
VOL1
Ii
ｔSU;DAT
：1us
Fast-mode devices
Min.
Max.
-0.3
1
2.3
5
0
50
0
0.4
-10
10
Unit
V
V
ns
V
μA
ｔSU;STO
：2us
SCL
ｔBUF
：4us
ｔLOW
：3us
ｔHIGH
：1us
SDA
SCL clock frequency：250kHz
Figure 54. A command timing example in the I2C data transmission
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BD49101AEFS-M
2
(2)I C BUS Format
S
1bit
MSB
LSB
Slave Address
8bit
S
Slave Address
A
A
Select Address
Data
P
MSB
LSB
MSB
LSB
A
Select Address
A
Data
A
P
1bit
8bit
1bit
8bit
1bit 1bit
= Start conditions (Recognition of start bit)
= Recognition of slave address. 7 bits in upper order are voluntary.
The least significant bit is “L” due to writing.
= ACKNOWLEDGE bit (SDA “L”)
= NOT ACKNOWLEDGE bit (SDA “H”)
= Select ENABLE/LDET SETTING/REG1 SETTING/HSW OCP.
= Data on ENABLE/LDET SETTING/REG1 SETTING/HSW OCP
= Stop condition (Recognition of stop bit)
2
(3)I C BUS Interface・Protocol
1)Write Mode Fundamental
S
Slave Address
A
Select Address
MSB
LSB
MSB
LSB
A
Data
A
MSB
LSB
P
2)Auto Increment(The selection address does increment(+1) the number of data.)
S
Slave Address
A
Select Address
A
Data1
A
Data2
A ････
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
(Example)①Data 1 is set as data of the address specified in the selection address.
②Data 2 is set as data of the address specified in the selection address +1.
③Data N is set as data of the address specified in the selection address +N-1
DataN
MSB
3)Composition that cannot be transmitted(In this case, the selection address only 1 is set.)
S Slave Address A
Select Address1 A Data
A Select Address 2 A Data
A
MSB
LSB MSB
LSB MSB LSB MSB
LSB MSB LSB
(Attention)
When you transmit data as selection address 2 next to data,
it doesn't recognize as selection address 2, and it recognizes it as
data.
4)Read Mode Protocol(Address 0x04 Read)
S Slave Address A
REQ Address
A
Select Address
A
MSB 0xD8 LSB MSB
0xD0 LSB MSB
0x04 LSB
S
A
※READ DATA
Slave Address A
MSB 0xD9 LSB
MSB
LSB
A
P
LSB
P
P
P
Because read data outputs with synchronizing with falling edge
of SCL, it latches with synchronizing with rising edge of SCL.
(4)Slave address
MSB
A6
1
A5
1
A4
0
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A2
1
A1
0
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A0
0
LSB
R/W
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BD49101AEFS-M
Register Map
Items
ENABLE
LDET
SETTING
HSW
OCP
Select
Address
init
01
DATA
0x02
D7
－
D6
HSW_EN
D5
REG5_EN
D4
REG4_EN
02
0x0B
－
－
－
－
04
0x00
－
－
－
－
D3
REG3_EN
D2
REG2_EN
D1
REG1_EN
D0
DCDC1_EN
LDET[3:0]
－
－
－
HSW
OCP
D2
REG2_EN
D1
REG1_EN
D0
DCDC1_EN
・Select Address 01 : ENABLE
Items
Select
Address
init
ENABLE
01
0x02
DATA
D7
－
D6
HSW_EN
D5
REG5_EN
D4
REG4_EN
D[0]: DCDC1_EN ・・・DCDC1 enable control.
“0”: OFF (Initial Value)
“1”: ON
D[1]: REG1_EN ・・・REG1 enable control.
“0”: OFF
“1”: ON (Initial Value)
D[2]: REG2_EN ・・・REG2 enable control.
“0”: OFF (Initial Value)
“1”: ON
D[3]: REG3_EN ・・・REG3 enable control.
“0”: OFF (Initial Value)
“1”: ON
D3
REG3_EN
D[4]: REG4_EN ・・・REG4 enable control.
“0”: OFF (Initial Value)
“1”: ON
D[5]: REG5_EN ・・・REG5 enable control.
“0”: OFF (Initial Value)
“1”: ON
D[6]: HSW_EN ・・・HSW enable control.
“0”: OFF (Initial Value)
“1”: ON
・Select Address 02 : LDET SETTING
Items
Select
Address
DATA
init
D7
D6
D5
D4
D3
D2
D1
D0
LDET
02
0x0B
－
－
－
－
LDET[3:0]
SETTING
D[3:0]: LDET ・・・ The low voltage detect threshold of the pin VIN0 is set. When the pin VIN0 becomes below the set
threshold, the pin BSENS becomes L.
“0000”: 5.7V
“1000” : 7.7V
“0001”: 5.8V
“1001” : 7.8V (Initial Value)
“0010”: 5.9V
“1010” : 7.9V
“0011”: 6.0V
“1011” : 8.0V
“0100”: 6.1V
“1100” : 8.1V
“0101”: 6.2V
“1101” : 8.2V
“0110”: 6.3V
“1110” : 8.3V
“0111”: 6.4V
“1111” : 8.4V
・Select Address 04 : HSW OCP (Read only)
Items
Select
Address
Init
DATA
D7
D6
D5
HSW
04
0x00
－
－
－
OCP
D[0]: HSW OCP ・・・ Detecting HSW over current condition
“0”: No detected (Initial Value)
“1”: Detected
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D4
D3
D2
D1
－
－
－
－
D0
HSW
OCP
TSZ02201-0V3V0AP00060-1-2
06.Apr.2015 Rev.001
BD49101AEFS-M
Application Example
TSD
SYNC
Ext CLK
RT
51kΩ
(fosc=300kHz)
24mΩ(OCP:4.2A)
36
34
DCDC1
(Controller)
OSC
VIN0
DCDC2
VIN2
REG2
output
130kΩ
1%
390pF
6.3V
75kΩ
470pF
6.3V
20kΩ
1%
1kΩ
1%
VOUT0
STB_REG
VOUT2
16
1uF 390kΩ
1%
ADJ2
16V
REG2
LDET/OVP
15
39kΩ
1%
12
VIN1
1uF
10V
REG5
VOUT5
LCD
14
1
output
output
3.3V
μ-con
75kΩ
INV2
11
390pF
10V
240kΩ
220pF
6.3V
10
19
output
1kΩ
DCDC2
100uF
10V
6.0V
CD-Drive
1%
9 FB2
BCLDET
/BCOVP
DCDC1
560pF
16V
47uH
4.7uF
50V
1000uF
50V
10uF
50V
5.0V
SW2
8
3
Audio
39kΩ
24 6.3V
INV1
BCAP
8.8V
100uF
16V
FB1
680pF
INTERNAL
REGULATOR
2
220uF
50V
21
SNSL
22
22uH
GATE1
23
1%
VBAT
4.7uF
50V
SNSH
20
1uF 430kΩ
1%
ADJ5
16V
REG1
REG5
1%
ADJ1
1.25V
μ-con RAM
470kΩ
13
44
82kΩ
REG1
VOUT1
output
4.7uF
10V
430kΩ
1%
1%
VINSW
4
ILM
Hi-side SW
6
output
30
VIN3
1uF
10V
4.7uF
50V
HSW
Hside
SW
32
REG3
REG3
VOUT3
470kΩ
31
1%
ADJ3
3.3V
Tuner
output
4.7uF
10V
150kΩ
1%
BSENS
REG4OCB
ECO
EN
REG4EN
40
29
39
25
VIN4
REG4
VOUT4
USB
880kΩ
41
26
43
ADJ4
1%
160kΩ
120uF
10V
SCL
VOCAL
1%
38
37
output
1%
REG4
42
(calibrate) 27
SDA
5.2V
I2C I/F
35
GND1
・Each ch on/off
・LDET setting
28
120Ω
(VCAL:0.26Ω setting)
4.7uF
6.3V
CLCAL
1%
5.1kΩ
(OCP:1.96A setting)
33
17
7
GND2 GND3 GND4
Please put this BCAP capacitor near BCAP pin as much as possible.
※ We recommend you use less than 1% accuracy resistor with voltage, frequency, OCP datect and cable compensation setting.
※ This in an example. Please decide all parts after enough evaluations and verifications.
Figure 55. Application Example
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Selection of Components Externally Connected
1. Setting external components for DCDC
Vin
Cbulk
SNSH Cin
Rcl
SNSL
GATE1
L
DCDC
(Controller)
D
Vo
Co
R1
FB1
R3
C2
C1
Rs
R2
INV1
Figure 56. External components for DCDC
(1) Setting output voltage
To set output voltage, connect R1 between VOUT and INV, R2 between INV and GND.
Furthermore, set the R1 and R2 to 10k–1MΩ.
VOUT = VINV x (R1 + R2)/R2 [V]
VADJ : REG3,REG4,REG5: 0.8V(Typ),
REG1: 0.6V(Typ)
REG2: 0.793V(Typ)
(2) Selection of coil L
The value of the coil can be obtained by the formula shown below:
L =
( V IN - VO ) × VO
V IN × f × Δ I O
△IO: Output ripple current
△IO should typically be approximately 20 to 30% of Io
If this coil is not set to the optimum value, normal (continuous) oscillation may not be achieved. Furthermore, set the
value of the coil with an adequate margin so that the peak current passing through the coil will not exceed the rated
current of the coil.
(3) Selection of output capacitor
The output capacitor can be determined according to the output ripple voltage△VO(p-p) required. Obtain the required
ESR value by the formula shown below and then select the capacitance.
Δ IL =
( V IN - VO ) × VO
L × f × VIN
Δ Vpp = Δ IL × ESR +
Δ IL × VO
2 × Co × f × VIN
Set the rating of the capacitor with an adequate margin to the output voltage. Also, set the maximum allowable ripple
current with an adequate margin to ⊿IL. Furthermore, the output rise time should be shorter than the soft start time.
Select the output capacitor having a value smaller than that obtained by the formula shown below.
C MAX =
1.7ms × { ILIMIT - I O(Max) }
ILIMIT :0.1/Rcl[A]
3.6 [A]
VO
(DCDC1)
(DCDC2)
If these capacitances are not optimum, faulty startup may result.
(※1.7m is soft start time(min)）
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(4) Selection of diode
Set diode rating with an adequate margin to the maximum load current. Also, make setting of the rated inverse voltage
with an adequate margin to the maximum input voltage.
A diode with a low forward voltage and short reverse recovery time will provide high efficiency.
(5) Selection of input capacitor
Be sure to insert a ceramic capacitor of 2 to 10uF for Cin
Furthermore, connect the capacitor Cbulk to keep input voltage.
The capacitor Cbulk should have a low ESR and a significantly large ripple current. The ripple current IRMS can be
obtained by the following formula:
IRMS =
2
IO ×
VO × ( V IN - VO ) / V IN
Select capacitors that can accept this ripple current.
If the capacitance of CIN and C28 is not optimum, the IC may malfunction.
(6) Setting of phase compensation
The following section summarizes the targeted characteristics of this application for the stability condition of DCDC.
・At a 1(0dB)gain, the phase delay is 150°or less(i.e. the phase margin is 30° or more).
・The GBW for this occasion is 1/10 or less of the switching frequency.
Vin
L
Vo
Re
D
Co
Figure 57. LC filter of DCDC
1
fr =
fESR =
2π ×
L × Co
[Hz] (LC resonance point)
1
2π × Re × Co
[Hz](Phase lead)
Replace a secondary phase delay(-180°) with a secondary phase lead by inserting two-phase leads, to ensure
the stability through the phase compensation.
Vo
C3
C2
C1
R1
R2
R3
Rs
INV1
ERR1
FB1
Figure 58. Phase compensation
f z1 =
f z2 =
1
2π × R1 × C1
[Hz](phase lead)
1
2π × R3 × C2 [Hz](phase lead)
Setting fz1,fz2 to be half to 2 times a frequency as large as fr provides an appropriate phase margin.
For output capacitors that have high ESR, because fESR(phase lead) occurs near LC resonance point,
it is unnecessary to insert fz1(phase lead).
For output capacitors that have low ESR, inserts fz1(phase lead) and fp1 obtained by the following formula
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and adjust frequency response.
f p1 =
C1 + C3
[Hz] (Phase delay)
2π × R3 × C1 × C3
The setting above have is estimated. Consequency, the setting may be adjusted on the actual system.
Furthermore, since these characteristics vary with the layout of PCB loading conditions, precise calculations
should be made on the actual system.
To check on the actual frequency characteristics, use a FRA or a gain-phase analyzer. Moreover, there is a
method of guessing the room degree by the loading response, too, when these measuring instruments do not
exist. The response is low when the change of the output when it is made to change under no load to the
maximum load is monitored, and there are a lot of variation quantities. It can be said that the phase margin
degree is little when there are a lot of ringing frequencies after it changes. As the standard, it is two times or
more of ringing. However, a quantitative phase margin degree cannot be confirmed.
Maximum load
Load
0
Inadequate phase margin
Output voltage
Adequate phase margin
t
Figure 59. Load response
(7) Setting of the threshold for DCDC1 over current protection
When the peak of the inductor current gets over the over current protection values, over current protection circuit
operates. The over current protection values can be obtained by the following formula:
Iocp =
100mV
Rcl
Rcl : Resistance between SNSH and SNSL
(8) Selection of the Pch FET for DCDC1
・VDS＜-Vin
・VGS＜-5V(Typ)
・allowable current ＞ Output current + Ripple current
※Recommended more than the threshold for over current protection
※The FET with low on resistance will provide high efficiency.
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2. Setting external components for REG
VIN
Cin
REG
VOUT
ADJ
R1
Co
R2
Figure 60. External components for REG
ch
OUTPUT
VOLTAGE[V]
REG1
1.25
INPUT VOLTAGE
RANGE[V]
Min
Typ
Max
Min
Typ
Max
OUTPUT
CAPACITANCE[uF]
Min
Typ
Max
6.5
0.5
1.0
1.5
4.7
-
-
14.4
25
0.15
0.30
0.45
1
-
-
6
6.5
0.3
0.6
0.9
4.7
-
-
6
6.5
Typ-20%
Variable
Typ+20%
47
-
-
14.4
25
0.05
0.10
0.15
1
-
-
2.25
(Note 1)
3.3
(Note 1)
REG2
8.8
9.45
REG3
3.3
3.9
(Note 1)
(Note 1)
REG4
5.2
5.6
REG5
5
5.65
(Note 1)
OCP THRESHOLD[A]
(Note 1) the value when Output Voltage is indicated above
Figure 61. Each REG’s specification of BD49101AEFS
(1) Setting output voltage
To set output voltage, connect R2 between ADJ and GND, R1 between VOUT and ADJ.
Furthermore, set the R1 to 100kΩ or more.
VOUT = VADJ x (R1+R2)/R2 [V]
VADJ : REG3,REG4,REG5: 0.8V(Typ),
REG1: 0.6V(Typ),
REG2: 0.793V(Typ)
(2) Selection of output capacitor
To prevent from oscillation, insert output capacitor. Check to Figure 61 about minimum capacitance of each REG.
(Temperature characteristic is excluded) It may be use ceramic capacitor.
Because steep change and input voltage change have effect on output voltage change, please confirm output
capacitance in actual application.
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(3) Setting of REG4 over current protection threshold and cable impedance calibration
① Setting of over current protection threshold
The over current protection threshold can be set by the resistance connected with CLCAL.
The threshold can be obtained by the following formula (typical characteristic):
RCLCAL[Ω] = 5.1k x 1.96A / IRG4OCP[A]
The relation between resistance and the threshold is decided as shown in the figure below.
Figure 62. Setting of over current protection threshold
②
Setting of cable impedance calibration
The cable impedance calibration value can be set by the resistance connected with VOCAL
This value can be obtained by the following formula (typical characteristic):
RVOCAL[Ω] = RCABLE[Ω] x 2400 / VOUT4
VOUT4－REG4 Output setting value(Typ)
Figure 63. Setting of cable impedance calibration
When you set cable impedance, please assume VOUT4 absolute maximum rating(7.0V) and I/O voltage difference(0.4V max)
so that the cable impedance calibration cause rising output voltage.
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③Setting of the VOCAL capacitance
VIN4
Vin
Cin
REG4
VOUT4
Vo
Co
VOCAL
Cvocal
Rvocal
Figure 64. Capacitance CVOCAL of VOCAL
For the oscillation of REG4 cable impedance calibration circuit, insert more than 4.7uF capacitor to VOCAL
as shown above.
(4) VOUT0 pin setting
Be sure to connect DCDC2 output with VOUT0 pin.
VOUT0 pin serves both as STBREG voltage output and as power supply for I/O pin(36-43pin). Therefore, if VOUT0
and VODC2 output would not be connected, you could not set external synchronization, register or DCDC2/STBREG
and also get BSENS or REG4OCB output signal.
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3. Setting the oscillating frequency(fosc)
An internal oscillating frequency can be set by the resistance connected with RT.
The relation between resistance and the oscillation frequency is decided as shown in the figure below.
OSCILLATING FREQUENCY:fosc[kHz]
550
500
450
400
350
300
250
200
150
20
30
40
50
60
70
80
90
100
OSCILLATIONG FREQUENCY SETTING
RESISTANCE: RT [kΩ]
RT[kΩ]
27
30
33
36
39
43
47
51
56
62
68
75
82
91
fosc[kHz]
537
489
449
415
386
353
324
300
275
250
229
209
192
174
Figure 65. Oscillating Frequency vs RT
Thermal reduction characteristics
POWER DISSIPATION : PD [W]
10
9
8
7
6.19W
6
5
※Reduce by 49.5 mW/°C,when mounted on 4-layer PCB
3
of 70 x 70 x 16 mm
2
(Copper foil area on the reverse side of PCB: 70 x 70mm ).
4
3
2
1
0
25
50
75
100
125
150
AMBIENT TEMPERATURE : Ta [℃]
Figure 66. Thermal reduction characteristics
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BD49101AEFS-M
I/O equivalence circuit(s)
Pin
No.
Pin
Name
14
VOUT1
Equivalent Circuit
Pin
No.
Pin
Name
Equivalent Circuit
VINSW
16
VOUT2
32
VOUT3
BCAP VIN 1,2,3,0 Internal
Regulator
Internal
Regulator
10kΩ
VOUT1,2,3,5
6
HSW
HSW
700kΩ
1
VOUT5
BCAP
20kΩ
600kΩ
91kΩ
115kΩ
9kΩ
35kΩ
BCAP Internal
Regulator
BCAP
FB1,2
8
SW2
23
FB1
9
FB2
SW2
Internal
Regulator
20kΩ
Internal
Regulator
20Ω
1kΩ
100kΩ
BCAP
12
INV1
19
INV2
BCAP
Internal
Regulator
BCAP
11
INV1,2
VOUT0
VOUT0
2500kΩ
5kΩ
800kΩ
13
Internal
Regulator
ADJ1
BCAP
15
ADJ2
31
ADJ3
26
ADJ4
44
ADJ5
10kΩ
ADJ1,2,3,4,5
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SNSH
SNSH
21
SNSL
SNSH
5kΩ
SNSL
2kΩ
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BD49101AEFS-M
Pin
No.
Pin
Name
Pin
No.
Equivalent Circuit
SNSH
Pin
Name
Equivalent Circuit
SNSH
VIN4
SNSH
VOUT4
22
GATE1
25
GATE1
VOUT4
60.125kΩ
40kΩ
VIN4
5kΩ
150kΩ
VIN4
Internal
Regulator
27
10kΩ
350kΩ
Internal
Regulator
Internal
Regulator
VOCAL
28
Internal
Regulator
CLCAL
VOCAL
CLCAL
500kΩ
5kΩ
500kΩ
Internal
Regulator
34
Internal
Regulator
RT
BCAP
36
RT
SYNC
SYNC
VOUT0
2kΩ
30kΩ
50Ω
100kΩ
VOUT0
37
SCL
2kΩ
SCL
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VOUT0
38
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SDA
2kΩ
SDA
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BD49101AEFS-M
Pin
No.
Pin
Name
BCAP
40
39
Pin
No.
Equivalent Circuit
Equivalent Circuit
BCAP
VOUT0
43
BSENS
REG4
OCB
Pin
Name
42
BSENS,
REG4OCB
41
VOUT0
EN
REG4
EN
EN,REG4EN,
ECO
2kΩ
100kΩ
ECO
(EN:660kΩ)
Figure 67. I/O equivalence circuit(s)
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Operational Notes
1. Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2. Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4. Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the board size
and copper area to prevent exceeding the Pd rating.
6. Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
7. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush
current may flow instantaneously due to the internal powering sequence and delays, especially if the IC
has more than one power supply. Therefore, give special consideration to power coupling capacitance,
power wiring, width of ground wiring, and routing of connections.
8. Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9. Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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Operational Notes – continued
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
C
E
Pin A
N
P+
P
N
N
P+
N
Pin B
B
Parasitic
Elements
N
P+
N P
N
P+
B
N
C
E
Parasitic
Elements
P Substrate
P Substrate
GND
GND
Parasitic
Elements
GND
Parasitic
Elements
GND
N Region
close-by
Figure 68. Example of monolithic IC structure
13. Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
14. Area of Safe Operation (ASO)
Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe
Operation (ASO).
15. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins except DCDC2/STBREG
and REG1. When the Tj falls below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
16. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
17. DCDC2 Short Current Protection (SCP)
While OCP operates, if the output voltage falls below 70%, SCP will start up. If SCP operates, the output will be OFF
period of 1024 pulse. It extends the output OFF time to reduce the average output current. In addition, when power
start-up this feature is masked until it reaches the output voltage is set to prevent the startup imperfection.
18. BCAP over voltage protection (BCOVP)
The output except DCDC2/STBREG and REG1 will be turned OFF when BCAP voltage exceeds 30V(Typ).
When the voltage falls under 28V(Typ), those outputs restarts. Please care the range of use voltage.
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BD49101AEFS-M
Ordering Information
B
D
4
9
1
0
1
A
Part Number
E
F
S
Package
EFS: HTSSOP-A44
-
ME2
M: for
Automotive
Packaging and forming specification
E2: Embossed tape and reel
Physical Dimension, Tape and Reel Information
Marking Diagrams
HTSSOP-A44 (TOP VIEW)
Part Number Marking
D49101AEFS
LOT Number
1PIN MARK
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BD49101AEFS-M
Revision History
Date
Revision
06.Apr.2015
001
Changes
First Draft
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Datasheet
Notice
Precaution on using ROHM Products
1.
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1),
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001