1/4 Structure Silicon Monolithic Integrated Circuit Product Series 7-Channel Switching Regulator Controller for Digital Camera Type ＢＤ９７５９ＭＷＶ Package Pin Assignment Block Diagram Application Function Fig.1 Fig.2 Fig.3 Fig.4 ● 3.3V minimum input operating ● Contains cross converter(1ch),step-down converter(3ch),inverting(1ch),step-up converter(1ch),step-up converter for LED(1ch), ● Contains LDO(1ch),constant current driver for LED(1ch) ● Contains load switch for step-up converter ● Contains output interception circuit when over load ● It is possible separately control except CH1,CH2,CH3 ● Thermally enhanced UQFN056V7070 package(7mm x 7mm, 0.4mm pitch) ○ Absolute maximum ratings（Ta＝25℃） Parameter Power Supply Voltage Power Input Voltage Limits Units VCC,PVCC PVCCH,PVCCL HX2,3,4 LX11 VOUT1,LX12 －0.3～12 -0.3～15 －0.3～12 －0.3～12 －0.3～7 V V V V V LX6,7 －0.3～20 V SWIN6,7 REGIN,LEDIN －0.3～20 －0.3～12 420(*1) 930(*2) －25～+85 －55～+150 V V mW mW ℃ ℃ Power Dissipation Pd Operating Temperature Topr Tstg Junction Temperature ○ Recommended operating conditions Symbol MAX CVREF CVREGA CSCP CREGOUT CLEDOUT 0.47 0.47 0.001 0.47 0.47 1.0 1.0 － 1.0 1.0 4.7 4.7 2.2 10 10 μF μF μF μF μF Fosc RT 0.6 47 1.2 68 1.5 120 MHz kΩ － － － － － － － － － － － － － － － 10 5.5 10 1 600 500 100 50 V V V A mA mA mA mA － － － － 100 50 mA mA VREF Pin Connecting Capacitor SCP Pin Connecting Capacitor REGOUT Pin Connecting Capacitor LEDOUT Pin Connecting Capacitor 【Oscillator】 Oscillator Frequency OSC Timing Resistor 【Driver】 LX11 Pin Input Voltage CH1 Output set up area HX2,3,4 Pin Input Voltage CH1 Output Current CH2 Output Current CH3,4 Output Current CH6 Output Current CH7 Output Current 【SW Circuit】 (*2) Reduced by 9.3mW/℃ over 25℃, when mounted on a PCB (70.0mm×70.0mm×1.6mm). Recommended operating conditions Limits TYP Symbol VREGA Pin Connecting Capacitor (*1)Without external heat sink, the power dissipation reduces by 4.2mW/℃ over 25℃. MIN Parameter SWOUT6 Pin Source Current SWOUT7 Pin Source Current VLX11 VVOUT1 VHX2,3,4 Ioutch1 Ioutch2 Ioutch3,4 Ioutch6 Ioutch7 ISWOUT6 ISWOUT7 3.9 Units ◎ It is strongly recommended that a capacitor be connect to VREF,VREGA pin to prevent oscillation. ※）The IC may not operate correctly by an unsettled state of the internal logic when voltage is applied on VCC rapidly while STB pin is ON. Make sure STB pin is OFF in this case. ○ Recommended operating conditions Parameter Power Supply Voltage Symbol Limit Unit VCC,PVCC 3.3 ～ 10 V PVCCL 3.75 ～ 14 V PVCCH VCC+3.75 ～ 14 V Status of this document The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version. If these are any uncertainty in translation version of this document, official version takes priority. REV. A 2/4 ○ Electrical characteristics（Ta=25℃，VCC=5V, RT=68kohm, STB1～7=3V） Standard value Parameter Symbol Units MIN TYP MAX 2.4 2.5 2.6 V 3.65 V Conditions 【Internal Regulator】 Output Voltage Threshold Voltage１ Vstd1 3.35 Threshold Voltage 2 Vstd2 2.85 3.0 3.15 V Threshold Voltage 3 Vstd3 － 2.15 2.30 V Vtc 2.1 3.50 2.2 2.3 V Iscp 0.5 1.0 1.5 μA SCP Threshold Voltage Vtsc 0.45 0.50 0.55 V Stand by Voltage Vssc － 22 170 mV Ireg=1mA PVCCL Monitor PVCC Monitor VREGA Monitor FB Pin Monitor Symbol Units MIN TYP MAX PVCC-1.0 PVCC-0.5 - fosc1 1.0 1.2 Frequency CH5～7 fosc2 0.5 Max duty 2,3,4（Step Down） Dmax1d - Max duty 5,6,7 Dmax2 Max duty CH1 Lx11 Max duty CH1 Lx12 OUT1H Driver Output Voltage H Vout1H V INV Threshold Voltage 1 INV Threshold Voltage 2 INV Threshold Voltage 3 IOUT1H=50mA OUT1H Driver Output Voltage L Vout1L - 0.5 1.0 V CH1 Lx11 Pin Lowside SW ON Resistance RON11N - 300 450 mΩ PVCC=5V CH1 Lx12 Pin Highside SW ON Resistance RON12p - 250 400 mΩ VOUT1=5.0V CH1 Lx12 Pin Lowside SW ON Resistance RON12N - 150 300 mΩ IOUT1L=50mA PVCC=5V CH2,3,4 Highside SW ON Resistance RON2345p - 300 450 mΩ Hx=5V, PVCC=5V PVCCH=10V CH2,3,4 Lowside SW ON Resistance RON2345N - 300 450 mΩ Hx=5V, PVCC=5V PVCCH=10V CH6 NMOS SW ON Resistance RON6N - 500 700 mΩ PVCCL=5V CH7 NMOS SW ON Resistance RON7N - 700 900 mΩ CH5 Driver Output Voltage H Vout5H PVCC-1.0 PVCC-0.5 - V RT=68kΩ CH5 Driver Output Voltage L Vout5L - 0.5 1.0 V 0.98 1.0 1.02 V PVCCL=5V IOUT5=50mA, NON5=0.2V PVCC=5V IOUT5=-50mA, NON5=-0.2V 1.4 MHz 0.6 0.7 MHz RT=68kΩ 【Regulator】 - 100 % Vscp=0V ※ Feed back voltage 1 VNF1 86 92 96 % Maximum output current 1 Imax1 - - 150 mA Dmax3 - - 100 % Difference of input/output voltage 1 ΔV1 - 150 300 mV Dmax4 78 84 90 % Δvol1 - 10 50 mV Io=0.1～10mA dB f=120Hz, VRR=-20dBV, Io=1mA Load stability 1 【Error AMP】 Input Bias Current Conditions VSCP=0.1V 【Oscillator】 Frequency CH1～4 Parameter 【Output Driver】 VREGA 【Prevention Circuit of Miss Operation by Low Voltage Input】 【 Short Circuit Protection】 Timer Start Threshold Voltage SCP Out Source Voltage Standard value Test circuit IINV - 0 50 nA INV1～7, NON5=7.0V VINV1 0.79 0.80 0.81 V CH1～4 VINV2 0.99 1.00 1.01 V CH6,7V VINV3 380 400 420 mV CH7I 【Base Bias Voltage Vref for Inverted Channel】 CH5 Output Voltage VOUT5 -6.09 -6.00 -5.91 V Line Regulation DVLi - 4.0 12.5 mV NON5 12kΩ, 72kΩ VBAT=4.8～ 8.4V Load Regulation DVLo - 1.0 7.5 mV Iref=10μA～ 100μA Output Current when shorted Ios 0.2 1.0 - mA Vref=0V Ripple rejection RR1 40 50 - Feed back Voltage 2 VNF2 380 400 420 mV Maximum output current 2 Imax2 - - 50 mA Difference of input/output voltage 2 ΔV2 - 100 200 mV Io=10mA VSAT VSWIN6 -0.3 VSWIN6 -0.1 - V Io=20mA VSWIN6=5V 【Constant current driver】 【Power on switch】 SWOUT6 SWOUT7 【Soft Start】 Driver Voltage Output OFF Leak Current ILEAK - 0 5 μA Driver Voltage VSAT VSWIN7 -0.3 VSWIN7 -0.1 - V ILEAK - 0 5 μA Output OFF Leak Current CH1,2 Soft Start Time Tss1,Tss2 3.4 4.4 5.4 msec RT=68kΩ CH3,4 Soft Start Time Tss3、Tss4 1.2 2.2 3.2 msec RT=68kΩ CH5 Soft Start Time Tss5 4.4 5.4 6.6 msec RT=68kΩ CH6,7 Soft Start Time Tss6,Tss7 4.4 5.4 6.6 msec RT=68kΩ Io=50mA STB6=0V Io=10mA VSWIN7=10V STB7=0V 【ＳＴＢ】 STB control Voltage 1 Active VSTBH1 2.0 - 11 V Non Active VSTBL1 -0.3 - 0.3 V STB123,4,5,6,7 STB Pull down Resistance 1 STB control Voltage 2 RSTB1 250 400 700 kΩ Active VSTBH2 2.0 - 11 V Non Active VSTBL2 -0.3 - 0.3 V RSTB2 250 400 700 kΩ STBREG,LED ISTB1 - - 5 μA STB1～7=0V Icc1 - 10 15 mA INV=2.5V, NON=-0.3V Icc2 - 95 150 ΜA Icc3 - 150 300 μA STB123,4,5,6,7 STBREG,LED STB Pull down Resistance 2 【Circuit Current】 STAND-by Current 1 Circuit Current 1 （ VCC,PVCC current when voltage supplied for the terminal） Stand-by Current 2 （PVCCL current when voltage supplied for the terminal） Circuit Current 3 （PVCCH current when voltage supplied for the terminal） INV=2.5V, NON=-0.3V PVCCL=5.0V INV=2.5V, NON=-0.3V PVCCH=10V (※1)The protective circuit start working when circuit is operated by 100% duty. So it is possible to use only for transition time shorter than charge time for SCP. ◎This product is not designed for normal operation with in a radioactive environment. REV. A Test circuit 3/4 ○ Block Diagram ○ Package BD9759MW LOT No. Fig.1 Fig.2 35 34 33 32 31 30 29 SCP VCC VREGA RT INV4 INV3 INV2 INV1 PVCC 43 STB7 44 STB6 OUT1H 27 45 STB5 LX11 26 46 OUT5 47 PGND56 28 LX11 25 PGND1 24 PGND1 23 LX12 22 NON5 Error AMP non inverted input 48 LX6 Ground terminal VREGA output Lx11 Lx12 Terminal for connecting inductor for CH1 input 49 SWIN6 Terminal for connecting inductor for CH1 output 50 SWOUT6 LX12 21 51 SWOUT7 VOUT1 20 Input terminal for LED LEDOUT LEDREF Hx2,3,4 CH1～CH7 ON/OFF switch Active ‘H’ Output terminal for LED Feed back terminal for LED Input terminal for synchronous High side switch CMINUS Terminal for connecting capacitor for Charge Pump Base bias voltage - Input terminal for Lord SW Output Terminal for Load SW 19 LX4 18 54 PGND7 PGND4 17 55 LEDREF CMINUS 16 56 LEDOUT 1 2 3 4 5 6 7 8 9 10 11 Fig.3 - REV. A STB123 LEDIN REG ON/OFF switch Active ‘H’ LED ON/OFF switch Active ‘H’ STBREG STBLED STB123, 4,5,6,7 SWIN6,7 SWOUT6,7 HX4 LX7 STBLED Output terminal for REG Feed back terminal for REG SWIN7 STB4 REGOUT REGADJ 52 53 STBREG For connecting a capacitor to set up the delay time of the SCP HX2 SCP LX2 Input terminal for REG PGND23 REGIN LX3 For connecting a register to set the OSC freqency BD9759MWV PVCCL RT VREF5 36 Ground terminal for internal FET Terminal for connecting gate of OUT1H, OUT5 PMOS OUT1H,OUT5 GND Error AMP inverted input 37 INV7 INV7I 38 INV6 Error AMP inverted input 39 INV7I INV 1～4,6,7 40 NON5 CH1 output voltage Terminal for connecting inductors 41 HX3 GND VREGA Power supply for the output circuit (High side) Power supply for the output circuit (Low side) VOUT1 Lx2,3,4,6,7 42 REGIN PVCCL PGND1,23,4,56 ,7 Power supply for the output circuit Description REGOUT PVCCH Power supply Pin Name REGADJ VCC PVCC Description LEDIN Pin Name VREF5 ○ Pin Assignment ○ Pin Description 12 13 14 PVCCH 15 4/4 ○ Operation Notes １.) Absolute maximum ratings This product is produced with strict quality control. However, the IC may be destroyed if operated beyond its absolute maximum ratings. If the device is destroyed by exceeding the recommended maximum ratings, the failure mode will be difficult to determine. (E.g. short mode, open mode) Therefore, physical protection counter-measures (like fuse) should be implemented when operating conditions beyond the absolute maximum ratings anticipated. ２.) GND potential Make sure GND is connected at lowest potential. All pins except NON5, must not have voltage below GND. Also, NON5 pin must not have voltage below - 0.3V on start up. ３.) Setting of heat Make sure that power dissipation does not exceed maximum ratings. ４.) Pin short and mistake fitting Avoid placing the IC near hot part of the PCB. This may cause damage to IC. Also make sure that the output-to-output and output to GND condition will not happen because this may damage the IC. ５.) Actions in strong magnetic field Exposing the IC within a strong magnetic field area may cause malfunction. ６.) Mutual impedance Use short and wide wiring tracks for the main supply and ground to keep the mutual impedance as small as possible. Use inductor and capacitor network to keep the ripple voltage minimum. ７.) Voltage of STB pin The threshold voltages of STB pin are 0.3V and 1.5V. STB state is set below 0.3V while action state is set beyond 1.5V. The region between 0.3V and 1.5V is not recommended and may cause improper operation. The rise and fall time must be under 10msec. In case to put capacitor to STB pin, it is recommended to use under 0.01μF. ８.) Thermal shutdown circuit (TSD circuit) The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. ９.)Rush current at the time of power supply injection. An IC which has plural power supplies, or CMOS IC could have momentary rush current at the time of power supply injection. Please take care about power supply coupling capacity and width of power Supply and GND pattern wiring. １０.)IC Terminal Input This IC is a monolithic IC that has a P- board and P+ isolation for the purpose of keeping distance between elements. A P-N junction is formed between the P-layer and the N-layer of each element, and various types of parasitic elements are then formed. For example, an application where a resistor and a transistor are connected to a terminal (shown in Fig.15): ○When GND > (terminal A) at the resistor and GND > (terminal B) at the transistor (NPN), the P-N junction operates as a parasitic diode. ○When GND > (terminal B) at the transistor (NPN), a parasitic NPN transistor operates as a result of the NHayers of other elements in the proximity of the aforementioned parasitic diode. Parasitic elements are structurally inevitable in the IC due to electric potential relationships. The operation of parasitic elements Induces the interference of circuit operations, causing malfunctions and possibly the destruction of the IC. Please be careful not to use the IC in a way that would cause parasitic elements to operate. For example, by applying a voltage that is lower than the GND (P-board) to the input terminal. Transistor (NPN) B （Terminal B）C Resistor （Terminal A） E GND （TerminalＡ） P P＋ N N P-board P P＋ P＋ N N Ｎ Parasitic element ～ ～ N P＋ Parasitic element N P-board Parasitic element GND Fig . 3 Simplified structure of a Bipolar IC REV. A GND Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. 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