SiA511DJ-DS

SPICE Device Model SiA511DJ
Vishay Siliconix
N- and P-Channel 12-V (D-S) MOSFET
CHARACTERISTICS
• N- and P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n- and p-channel vertical DMOS. The
subcircuit model is extracted and optimized over the
−55 to 125°C temperature ranges under the pulsed 0-V to 4.5-V
gate drive. The saturated output impedance is best fit at the gate
bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 69663
S-72405Rev. A, 19-Nov-07
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SPICE Device Model SiA511DJ
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Simulated
Data
Test Condition
Measured
Data
Unit
Static
Gate Threshold Voltage
Drain-Source On-State Resistancea
VGS(th)
rDS(on)
Forward Transconductancea
gfs
Diode Forward Voltagea
VSD
VDS = VGS, ID = 250 µA
N-Ch
0.55
VDS = VGS, ID = −250 µA
P-Ch
0.84
VGS = 4.5 V, ID = 4.2 A
N-Ch
0.034
0.033
VGS = −4.5 V, ID = − 3.3 A
P-Ch
0.058
0.058
VGS = 2.5 V, ID = 3.8 A
N-Ch
0.041
0.039
VGS = −2.5 V, ID = − 2.8 A
P-Ch
0.085
0.082
VGS = 1.8 V, ID = 1.6 A
N-Ch
0.051
0.051
VGS = −1.8 V, ID = − 0.70 A
P-Ch
0.121
0.111
VDS = 10 V, ID = 4.2 A
N-Ch
14
13
VDS = −10 V, ID = −3.3 A
P-Ch
15
9
IS = 4.4 A, VGS = 0 V
N-Ch
0.95
0.80
IS = −3.4 A, VGS = 0 V
P-Ch
0.70
−0.80
Ω
S
V
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Gate-Source Charge
Gate-Source Charge
Qg
Qgs
Qgs
N-Channel
VDS = 6 V, VGS = 0 V, f = 1 MHz
P-Channel
VDS = −6 V, VGS = 0 V, f = 1 MHz
N-Ch
448
400
P-Ch
429
400
N-Ch
117
120
P-Ch
142
140
N-Ch
57
70
P-Ch
101
100
VDS = 6 V, VGS = 8 V, ID = 5.5 A
N-Ch
6.5
7.5
VDS = −6 V, VGS = −8 V, ID = −4.3 A
P-Ch
5.6
8
N-Ch
3.9
4.5
P-Ch
3.5
5
N-Ch
0.60
0.60
N-Channel
VDS = 6 V, VGS = 4.5 V, ID = 5.5 A
P-Channel
VDS = −6 V, VGS = −4.5 V, ID = −4.3 A
P-Ch
0.80
0.80
N-Ch
0.80
0.80
P-Ch
1.4
1.4
pF
nC
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
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Document Number: 69663
S-72405Rev. A, 19-Nov-07
SPICE Device Model SiA511DJ
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
N-Channel MOSFET
Document Number: 69663
S-72405Rev. A, 19-Nov-07
www.vishay.com
3
SPICE Device Model SiA511DJ
Vishay Siliconix
P-Channel MOSFET
www.vishay.com
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Document Number: 69663
S-72405Rev. A, 19-Nov-07
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Document Number: 91000