LT1619 Low Voltage Current Mode PWM Controller U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LT ®1619 is a fixed frequency PWM controller for implementing current mode DC/DC converters with minimum external parts. The LT1619 operates with input voltages ranging from 1.9V to 18V and is suitable for a variety of battery-powered and distributed DC/DC converters. The internal rail-to-rail N-channel MOSFET driver operates either from the input in the nonbootstrapped mode or from the output in bootstrapped operation. The driver is designed to drive a low side power transistor in boost, SEPIC, flyback and other topologies. Wide VIN Range: 1.9V to 18V 300kHz Fixed Frequency Current Mode Control 1A Rail-to-Rail N-Channel MOSFET Driver Low 53mV Current Limit Threshold Voltage Improves Efficiency Implements Boost, SEPIC and Flyback Converters Requiring Low Side Power Transistors Internal Current Sense Amplifier with Leading Edge Blanking Up to 500kHz External Synchronization Burst Mode® Operation for High Efficiency at Light Load 140µA Quiescent Current 15µA Shutdown Current 8-Lead MSOP and SO Packages Converter efficiency is improved at heavy loads with a 53mV current sense voltage and at light load with Burst Mode operation. The operating frequency is internally set at 300kHz. The oscillator can also be synchronized externally up to 500kHz. No load quiescent current is 140µA and shutdown current is 15µA. U APPLICATIO S ■ ■ ■ The LT1619 is available in 8-lead MSOP and SO packages. 3.3V to 5V DC/DC Converters Distributed Power Supplies Isolated Power Supplies , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. U TYPICAL APPLICATIO Efficiency VIN 3.3V 12.4k 2 3 75k 220pF 4 VIN S/S FB DRV LT1619 VC GATE GND 15nF SENSE 8 7 6 + 0.1µF C1 22µF 90 L1 5.6µH 5A VOUT 5V 2.2A 0.1µF M1 Si9804 5 D1 + RSENSE 0.01Ω C1: PANASONIC EEFCDOK220R COUT: KEMET T495X227K010AS (×2) D1: MBRD835L L1: COILCRAFT DO5022P-562 1619 F01 COUT 440µF EFFICIENCY (%) 1 37.4k 95 85 80 75 70 1 10 100 LOAD CURRENT (mA) 1000 1619 F01a Figure 1. High Efficiency 3.3V to 5V DC/DC Converter 1619fa 1 LT1619 W W W AXI U U ABSOLUTE RATI GS (Note 1) Input Voltage (VIN) ................................... – 0.3V to 20V Gate Drive Supply Voltage (DRV) ............. – 0.3V to 20V Shutdown/Synch Voltage (S/S) ................ – 0.3V to 20V Feedback Voltage (FB) .............................................. VIN Compensation Voltage (VC) ...................................... 3V Gate Drive Output Current (GATE) ........................ ±1.5A Current Sense Voltage (SENSE) ................. – 0.5V to VIN Operating Temperature Range (Note 2) .. – 40°C to 85°C Junction Temperature (Note 3) ............................. 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C U U W PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW S/S FB VC GND 1 2 3 4 8 7 6 5 VIN DRV GATE SENSE LT1619EMS8 MS8 PACKAGE 8-LEAD PLASTIC MSOP MS8 PART MARKING TJMAX = 125°C, θJA = 200°C/ W LTHC ORDER PART NUMBER TOP VIEW S/S 1 8 VIN FB 2 7 DRV VC 3 6 GATE GND 4 5 SENSE LT1619ES8 S8 PART MARKING S8 PACKAGE 8-LEAD PLASTIC SO 1619 TJMAX = 125°C, θJA = 120°C/ W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = VDRV = 2.5V, VS/S = VIN, COMP open, VSENSE = 0V unless otherwise noted. PARAMETER CONDITIONS Reference Voltage Measured at the FB Pin Reference Line Regulation 1.9V ≤ VIN ≤ 18V FB Input Bias Current VFB = VREF MIN ● Error Amplifier Transconductance 1.22 TYP MAX UNITS 1.24 1.26 V 0.004 0.05 %/V 10 25 nA 80 170 260 µΩ –1 Error Amplifier Output Source Current VFB = 1V, VCOMP = 1V 4 8.7 14 µA Error Amplifier Output Sink Current VFB = 1.5V, VCOMP = 1V 4 8.7 14 µA Error Amplifier Clamp Voltage VFB = 1V 1.6 2.2 V 1.65 1.85 V ● 1.9 18 V ● 220 360 kHz 500 kHz Undervoltage Lockout Threshold Input Voltage Range Switching Frequency 1.9V ≤ VIN ≤ 18V Synchronization Frequency Range 300 370 Maximum Duty Cycle ● 88 92 Current Limit Threshold ● 40 53 Burst Mode Operation Current Limit 10 % 66 mV mV 1619fa 2 LT1619 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = VDRV = 2.5V, VS/S = VIN, COMP open, VSENSE = 0V unless otherwise noted. PARAMETER CONDITIONS Current Sense Input Current VSENSE = 0V ● MIN TYP MAX UNITS – 90 – 120 – 150 µA Current Limit Delay 150 ns Driver Output Rise Time CL = 3300pF 30 ns Driver Output Fall Time CL = 3300pF 35 ns Driver Output High Level IOUT = – 20mA IOUT = – 200mA VDRV – 0.35 VDRV – 1.2 V V Driver Output Low Level IOUT = 20mA IOUT = 200mA 100 0.5 200 0.7 mV V Shutdown Driver Output Level VS/S = 0V, IOUT = 20mA 100 200 mV Idle Mode Driver Output Level VS/S = VIN, VFB = 1.5V, IOUT = 20mA 100 200 mV S/S Pin Current VS/S = VIN VS/S = 0V 4 –2 µA µA Operating Supply Current VFB = 1V Quiescent Supply Current VS/S = VIN, VFB = 1.5V Shutdown Supply Current VS/S = 0V VS/S = 0V, VIN = 18V, TA = 85°C VDRV – 0.6 VDRV – 1.6 9 ● Shutdown Threshold mA 140 220 µA 15 40 19 µA µA 1.2 V 33 µs 0.45 Shutdown Delay 12 Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: The LT1619E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. 17 Note 3: TJ is calculated from the ambient temperature TA, the power dissipation PD and the thermal resistance θJA of the package according to the formula: TJ = TA + PD • θJA U W TYPICAL PERFOR A CE CHARACTERISTICS Bandgap Voltage vs Temperature VIN = 2.5V 5 TA = –40°C 1.243 4 1.241 4 1.239 TA = 85°C 2 1.237 1.235 1.233 VS/S = 2.5V TA = 25°C 3 IS/S (µA) BANDGAP VOLTAGE (V) S/S Pin Current vs Temperature IS/S vs VS/S 5 S/S PIN CURRENT (µA) 1.245 1 0 1.231 –1 1.229 –2 1.227 1.225 –40 –20 20 40 60 80 100 120 TEMPERATURE (°C) 1619 G01 2 1 0 VS/S = 0V –1 –2 –3 0 3 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VS/S (V) 1619 G02 –3 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 1619 G03 1619fa 3 LT1619 U W TYPICAL PERFOR A CE CHARACTERISTICS 45 200 IDLE MODE SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 40 35 TA = –40°C 30 TA = 25°C 25 TA = 85°C 20 15 10 2 4 VIN = 2.5V 190 180 170 160 150 140 –40 –20 5 0 Frequency Deviation from Nominal vs Temperature Idle Mode Supply Current vs Temperature 6 8 10 12 14 16 18 20 INPUT VOLTAGE (V) DEVIATION FROM NOMINAL FREQUENCY (%) Shutdown Supply Current vs Input Voltage 20 40 60 80 TEMPERATURE (°C) 0 100 120 Maximum Duty Ratio vs Temperature 92 91 6 4 2 0 –2 80 –4 100 0 2 4 –6 –8 –10 – 40 – 20 –115 VIN = 2.5V 12 DUTY CYCLE = 0 –117 6 4 2 100 1619 G10 VIN = 2.5V 56 55 54 53 52 51 60 40 20 TEMPERATURE (°C) 0 80 – 90 VSENSE = 0V TA = 25°C – 95 –119 –121 –123 –125 –127 –129 –131 –135 –40 –20 100 SENSE Pin Input Bias Current vs Sense Voltage –100 –105 –110 –115 –120 –125 –133 80 100 1619 G09 SENSE PIN CURRENT (µA) SENSE PIN CURRENT (µA) 14 8 80 57 SENSE Pin Input Bias Current vs Temperature 10 60 40 20 TEMPERATURE (°C) 0 1619 G08 Burst Mode Operation Current Limit Threshold vs Temperature CURRENT LIMIT THRESHOLD (mV) –4 50 –40 – 20 6 8 10 12 14 16 18 20 INPUT VOLTAGE (V) 1619 G07 40 20 60 0 TEMPERATURE (°C) 0 –2 58 CURRENT LIMIT THRESHOLD (mV) FREQUENCY DEVIATION (%) DUTY RATIO (%) 93 0 –40 –20 2 Current Limit Threshold vs Temperature TA = 25°C NOMINAL FREQUENCY = 300kHZ 40 20 0 60 TEMPERATURE (°C) 4 1619 G06 8 VIN = 2.5V 94 VIN = 2.5V NOMINAL FREQUENCY = 300kHz 6 Deviation from Nominal Frequency vs Input Voltage 95 –20 8 1619 G05 1619 G04 90 –40 10 40 0 60 20 TEMPERATURE (°C) 80 100 –130 –10 0 10 20 30 40 50 60 VSENSE (mV) 1619 G11 1619 G12 1619fa 4 LT1619 U U U PI FU CTIO S S/S (Pin 1): Shutdown and Synchronization. Shutdown is active low with a typical threshold voltage of 0.9V. For normal operation, the S/S pin is tied to VIN. To externally synchronize the controller, drive the S/S pin with pulses. SENSE (Pin 5): The Input of the Current Sense Amplifier. The SENSE pin is connected to the source of the N-channel MOSFET and to a sense resistor to the ground. The current limit threshold is internally set at 53mV, giving a maximum switch current of 53mV/RSENSE. FB (Pin 2): The inverting Input of the Error Amplifier. Connect the resistor divider tap here. Set VOUT according to VOUT = 1.24(1 + R1/R2). See Figure 1. GATE (Pin 6): The Output of the MOSFET Driver. DRV (Pin 7): The Pull-Up Supply of the MOSFET Driver. Tie this pin to VIN (Pin 8) for nonbootstrapped operation or to the converter output for bootstrapped operation. VC (Pin 3): Compensation Pin for the Error Amplifier. VC is the output of the transconductance amplifier. Overall loop is compensated with an RC network from this pin to the ground. VIN (Pin 8): Supply or Battery Input. Must be closely bypassed to the ground plane. GND (Pin 4): Ground. Connect to local ground plane. W BLOCK DIAGRA VC VIN 3 8 – UVLO A2 1.24V + 1.8V ERROR AMPLIFIER + – gm FB 2 – IDLE A1 + VB VIN DRV 7 – + C1 S DRIVER Q 6 GATE R RAMP COMP 300kHz SYNC OSCILLATOR 5 CLK CURRENT SENSE AMP + S/S 1 Σ + – + + SHUTDOWN DELAY REF/BIAS CURRENT LIMIT COMPARATOR – 4 LOAD SENSE GND RSENSE 280ns LEADING EDGE BLANKING ILIM 1619 F02 Figure 2. LT1619 Block Diagram 1619fa 5 LT1619 U OPERATIO The LT1619 is a fixed frequency current mode switching regulator PWM controller that can be used in boost, SEPIC or flyback modes. The device operates from an input supply range of 1.9V to 18V, and has a separate supply pin (DRV) for the gate driver. The DRV pin can be bootstrapped to VOUT for additional gate enhancement in low voltage applications like 3.3V to 5V boost converters, or connected to the input supply for higher voltage inputs. To best understand operation of the LT1619, please refer to Figure 2, the Block Diagram. The gate drive circuit turns on the external MOSFET at the trailing edge of oscillator output signal CLK. MOSFET current is sensed with an external resistor (RSENSE of Figure 1). A leading edge blanking circuit disables the current sense amplifier for 280ns immediately following switch turn-on, preventing gate charging current from prematurely tripping the PWM comparator. A slope compensating ramp, derived from the oscillator, is added to the current sense output. The driver turns off the MOSFET when this sum exceeds the error amplifier output VC. The switch current is limited with a separate comparator. The compensating ramp is a progressive nonlinear function of the operating duty ratio whereas the current limit does not vary with the duty ratio. Error amplifier output VC determines the peak switch current required to regulate the output voltage. VC can be considered a measure of output current. At heavy loads, VC is in its upper range. Average and peak inductor currents are high. In this range, the inductor tends to run in continuous conduction mode (CCM), where current is always flowing in the inductor. As load current decreases, average and peak inductor current decreases. When the average inductor current falls below 1/2 of the peak-to-peak inductor current ripple, the converter enters discontinuous conduction mode (DCM), where current in the inductor reaches zero sometime during the discharge phase. Further reduction in output current moves VC towards its lower operating range, decreasing inductor current. Hysteretic comparator A1 determines if VC is too low for the LT1619 to operate efficiently. As VC falls below the trip voltage VB, A1’s output goes high, turning off all blocks except the error amplifier, A1 and A2. The LT1619 enters the idle state and switching stops. The device draws just 140µA from the input in the idle state. Output load current discharges the output capacitor, causing the output voltage to decrease. As VOUT decreases, VC increases. As VC increases above VB, switching action begins, delivering power to the output. The switch current sense threshold is about 10mV in this VC region. If the output load remains light, the output voltage will rise and VC will fall, causing the converter to idle again. This is known as Burst Mode operation. The burst frequency depends on input voltage, output voltage, inductance and output capacitance. Output voltage ripple during Burst Mode operation is usually higher than when the converter is switching continuously. Burst Mode operation increases light load efficiency because it delivers more energy per clock cycle than possible with discontinuous mode operation and extremely low peak switch current, allowing fewer switching cycles to maintain a given output. IC supply current therefore becomes a small fraction of the total input current. Setting Output Voltage The output voltage of the LT1619 is set with resistive divider R1 and R2 connected from the output to ground as detailed in Figure 3. The divider tap is tied to the device FB pin. Current through R2 should be significantly higher than the FB pin bias current of 25nA. With R2 = 10k, the input bias current of the error amplifier is 0.02% of the current in R2. VO LT1619 FB R1 R2 ( ) ( ) VO = 1.24V 1 + R1 R2 VO –1 R1 = R2 1.24 1619 F03 Figure 3. Feedback Resistive Divider Synchronization and Shutdown The S/S pin (Pin 1) can be used to synchronize the oscillator to an external source. The S/S pin is tied to the input (VIN > 1.9V) for normal operation. The oscillator in the LT1619 can be externally synchronized by driving the S/S pin with a pulse train with an amplitude of at least 1V. The maximum allowable rise time is a function of the pulse amplitude, as shown in Table 1. Rise times equal to 1619fa 6 LT1619 U OPERATIO or less than the number specified in Table 1 are acceptable. The maximum duty cycle is essentially unaffected by synchronization. The device will go into shutdown mode if the S/S pin voltage stays below the shutdown threshold of 0.45V for Table 1. Maximum Allowable Rise Time of Synchronization Pulse. Rise Time Can Be Slower if Clock Amplitude is Higher SYNCHRONIZATION AMPLITUDE (V) MAXIMUM ALLOWABLE RISE TIME (ns) 1.2 120 1.5 220 2.0 350 2.5 470 3.0 530 more than 33µs. This shutdown delay is reset whenever the S/S pin voltage rises above the shutdown threshold. Applying a logic low signal at the S/S pin causes the gate drive output to go low. Although all circuits in the LT1619 are disabled, the pull-down circuit in the MOSFET buffer is still biased on. It is capable of shunting any leakage or transient current at the GATE pin to ground, eliminating the need for an external bleed resistor. The LT1619 consumes 15µA in shutdown. The LT1619 is guaranteed to start with a minimum VIN of 1.85V. Comparator A2 senses the input voltage and generates an undervoltage lockout (UVLO) signal if VIN falls below this minimum. While in undervoltage lockout, VC is pulled low and the LT1619 stops switching. The supply current drawn by the device falls to 140µA. U W U U APPLICATIO S I FOR ATIO The value of the inductor is usually selected so that the peak-to-peak ripple current is less than 30% of the maximum inductor current. The inductor should be able to handle the maximum inductor current at full load without saturation. Powder iron cores are not suitable for high frequency switch mode power supply applications because of their high core losses. Ferrite cores have very low core losses and are the material of choice for high frequency DC/DC converters. Power MOSFET Driver The LT1619 is capable of driving a low side N-channel power MOSFET with up to 60nC of total gate charge (Qg). An external driver is recommended for MOSFETs with greater than 80nC of total gate charge. The peak gate drive current varies from 0.5A with VDRV = 2.5V to 1.2A with VDRV = 10V. The MOSFET driver is capable of charging the gate of the power MOSFET to within 350mV of the upper gate drive supply rail (DRV). It can also pull the gate of the MOSFET to within 100mV of ground during turnoff. The upper supply rail of the gate drive is brought out as a device pin (DRV) for design flexibility. In a boost converter design, the DRV pin can be tied to the converter output if the minimum input voltage is insufficient to fully enhance the power MOSFET. During start-up, the MOSFET is driven with a gate voltage starting from VIN – VD (VD is the forward voltage of the rectifying diode). As the output voltage rises, the gate drive also increases until steady state is reached. If the steady-state converter output voltage exceeds the maximum allowable gate source voltage and the input voltage is sufficient to enhance the MOSFET, the DRV pin is tied to the input supply. For a SEPIC converter, the DRV pin can be tied to the input or diode OR’ed from the input and the output (Figure 4). • VOUT + Inductor VIN DRV + LT1619 GND RS • 1619 F03 Figure 4. SEPIC Converter with Diode OR’ed Gate Drive Supply 1619fa 7 LT1619 U W U U APPLICATIO S I FOR ATIO Power MOSFET MOSFET power dissipation can be separated into frequency independent and frequency dependent components. The RDS(ON) loss in the switch is the product of the mean square switch current and switch RDS(ON) and it does not vary with the operating frequency. The frequency-dependent switching losses consist of 1) switch transition loss due to finite rise and fall times of the drain source voltage and the drain current 2) gate switching loss, i.e., a packet of charge Qg (the total gate charge) which is moved from the gate drive power supply to ground in every switch cycle, and 3) the drain switching loss, charge stored on the parasitic drain capacitance, COSS is dumped to ground as the switch is turned on. The transistor loss can be expressed as: PLOSS = IDRMS2 RDS(ON) + transition loss + QgVGfS + 1/2COSSVDS(OFF)2fS where the transition loss can be estimated with: 2 Transition Loss = ID CRSSVDS(OFF) fS IG(AVG) Qg = The total gate charge VG = Gate drive voltage ≈ VDRV IG(AVG) = The average MOSFET buffer output current fS = Operating frequency CRSS = The average CGD between VDS = 0V and VDS = VDS(OFF) At low VDS(OFF) (≤12V) and operating frequencies below 500kHz, the ohmic losses often dominate. For high voltage converters, the transition loss and COSS charge dumping loss can dramatically impact the converter efficiency. MOSFETs with lower parasitic capacitances but higher RDS(ON) may actually provide better efficiency in these situations. Capacitors In a switch mode DC/DC converter, output ripple voltage is the product of the equivalent series resistance (ESR) of the output capacitor and the peak-to-peak capacitor current. Depending on topology, current feeding the output capacitor can be continuous or discontinuous. The input current can also be continuous or discontinuous even if the inductor current itself is continuous. In boost topology, the inductor is in series with the input source so the input current is continuous and the output current is discontinuous. In buck-boost or flyback converters, the inductor is not in series with the input source nor the output, so neither the input current nor output current is continuous. Whenever a terminal current is discontinuous, the capacitor at that terminal should be chosen to handle the ripple current. Capacitor reliability will be adversely affected if the ripple current exceeds the maximum allowable ratings. This maximum rating is specified as the RMS ripple current. Several capacitors may be mounted in parallel to meet the size and ripple current requirements. Besides the ripple voltage requirements, the output capacitor also needs to be sized for acceptable output voltage variation under load transients. Current Sensing Resistor RSENSE The LT1619 drives a low side N-channel MOSFET switch. The switch current is sensed with an external resistor RSENSE connected between the source of the MOSFET and ground. The internal blanking circuit blocks the voltage spike developed across RSENSE for 280ns at switch turnon. The switch is turned off when the instantaneous voltage across RSENSE exceeds the current limit threshold, VSENSE. Allowing variations in VSENSE yields: RSENSE = VSENSE(MIN) IL(MAX) The current limit threshold is constant and does not vary with duty ratio. Due to low signal level of the sense voltage, low inductance sense resistors are required to reduce switching noise. Low TC resistors maintain constant current limit over temperature. Dale WSL and IRC series sense resistors meet these criteria. 1619fa 8 LT1619 U W U U APPLICATIO S I FOR ATIO Diode Schottky diodes are recommended for low output voltage applications because of their low forward voltage. Since Schottky diodes have negligible stored charge, charge dumping loss is also reduced. The reverse breakdown voltage of the diode should exceed the maximum reverse voltage stress of the topology used. The diode should also be able to carry the peak diode current with acceptable foward voltage. For the boost converter in Figure 1, the peak inductor current is approximately 5A. A Motorola MBRD835 is used due to its low forward voltage. Lowering Burst Mode Operation Current Limit The LT1619 automatically enters Burst Mode operation as VC voltage falls below VB. The corresponding switch current is the Burst Mode operation switch current threshold, ID(BURST). tolerance of ±25% and is temperature stable, develops an offset voltage at the sense input. The value of ROS required for non-Burst Mode operation can be obtained with the expression: IBIASROS ≥ VSENSE(BURST) where VSENSE(BURST) = (Burst Mode operation peak switch current, ID(BURST)) • RSENSE For example, if IBIAS = 120µA and VSENSE(BURST) = 10mV: ROS ≥ 10mV = 83Ω 120µA Allowing for 25% and 30% variations in IBAIS and VSENSE(BURST) respectively: ROS = (1.25)(1.3)(83Ω) The effective Burst Mode operation current threshold can be lowered by adding an offset to the input of the current sense amplifier so that the switch current appears higher to the PWM comparator. This has the effect of shifting the VC operating range above VB. Although Burst Mode operation is not entirely disabled, the peak switch current before entering Burst Mode operation is greatly reduced due to the offset of the current sense amplifier. The peak switch current is also determined by the current sense amplifier blanking. Choose ROS = 137Ω to completely disable Burst Mode operation. Lower values of ROS (for example, 50Ω to 100Ω) can be used to lower the effective Burst Mode current limit. To lower the Burst Mode operation current sense threshold, a resistor ROS is added between the SENSE pin and the sense resistor RSENSE (Figure 5). The input bias current IBIAS of the current sense amplifier, which has a In a current mode converter, the current sense circuit senses the switch current and terminates the switch conduction. In the LT1619, the current sense amplifier has a full-scale input voltage range from the ground to the current limit threshold (53mV). Due to high speed switching transients and parasitic trace inductances, the current sense signal VSENSE tends to be noisy. If the VSENSE switching transient is excessive, the current sense amplifier will amplify the spurious transient instead, resulting in jittery operation. In situations where the internal leading edge blanking is inadequate, a lowpass filter (Figure 6) with corner frequency about 5 times the switching frequency can be used to further attenuate high speed switching transients. In Figure 6 the lowpass filter ROS and CS has a corner frequency of: CURRENT SENSE AMPLIFIER ID + – IBIAS = 120µA IBIAS = 120µA 5 SENSE 4 GND ROS RSENSE 1619 F05 The value of the sense resistor is then adjusted to compensate for the reduced full-scale sense voltage. IBIASROS + IL(MAX)RSENSE = 40mV Filtering Current Sense Signal Figure 5. Lowering Burst Mode Operation Current Limit 1619fa 9 LT1619 U W U U APPLICATIO S I FOR ATIO fCORNER = 1 ≈ 5fS 2πROSCS VIN VZ (The input impedance of the sense amplifier at the SENSE pin is 2500Ω and ROS is typically less than 137Ω.) Typical values for ROS and CS are 100Ω and 1nF. The 100Ω value for ROS reduces Burst Mode threshold; use 10Ω and 10nF when this is not desireable. 1 IS/S R3 2 3 4 S/S VIN FB DRV 8 7 LT1619 6 GATE VC 5 SENSE GND ( IS/S VS/S = 0 ) R3 < SHUTDOWN THRESHOLD UVLO THRESHOLD = VZ + SHUTDOWN THRESHOLD ≈ VZ + VBE IS/S ≈ –2µA VS/S = 0 1619 F07 Figure 7. Implementing Undervoltage Lockout ID LT1619 PWM COMPARATOR CURRENT SENSE AMPLIFIER I + 5 SENSE ROS + CS RSENSE – 4 GND VSENSE – ZENER DIODE + I – AVALANCHE DIODE V 1619 F06 V Figure 6. Current Sense Filter for Improving Jitter Performance Use of Shutdown Function to Modify Undervoltage Lockout The LT1619 is designed to operate from an input supply with voltage as low as 1.85V. Shutdown is activated when the S/S pin is pulled below 0.45V. The shutdown threshold is slightly greater than one junction diode forward voltage and has the temperature characteristics of a junction diode. The S/S pin is normally tied to the input when operating from a low voltage input source. Consider the 12V to – 65V isolated flyback converter (see Typical Applications). The converter draws 3A at low line while delivering 0.4A to the output. If the S/S pin is tied to the input, then the LT1619 will start switching as soon as VIN exceeds the internal UVLO threshold. With full load, the converter can draw much higher than the steady-state 3A from the input source during start-up. If the input source is current limited, the input voltage will collapse and latch low. The start-up problem can be prevented by adding a zener diode and a resistor to the S/S pin (Figure 7). This is equivalent to increasing undervoltage lockout voltage of the controller. Before VIN exceeds the zener voltage VZ, the S/S pin current is shunted to the ground through the 0 BV < 5V Figure 8. I-V Characteristics of Zener and Avalanche Breakdown Diodes VIN R4 1 2 C1 R3 3 4 S/S VIN FB DRV LT1619 VC GND GATE SENSE 8 7 6 5 1619 F09 Figure 9. Filtering Input Voltage Ripple in UVLO Circuit resistor R3. The voltage developed across R3 due to IS/S should be less than the shutdown threshold. The LT1619 remains off until VIN exceeds the sum of VZ and the shutdown threshold. True zener diodes (BV < 5V) and higher voltage avalanche diodes have different I-V characteristics (Figure 8). They need to be biased appropriately (value of R3) in order to obtain correct UVLO threshold. When implementing UVLO with converters with high input ripple voltages (such as flyback and forward), the circuit in Figure 7 is modified and shown in Figure 9. 1619fa 10 LT1619 U W U U APPLICATIO S I FOR ATIO Here the input voltage ripple is filtered with R3, R4 and C1 so as to prevent the input ripple from falsely tripping the LT1619 synchronization circuit. It is recommended that: and 1 R4 ≈ R3 5 1 ( Trickle Current Start from High Voltage Supplies ) 2π R3 || R4 C1 << fOSC Implementation of Hysteretic UVLO with External Synchronization The UVLO circuit shown in Figure 10 operates down to 0.9V supply voltage. Algebraically the UVLO trip points are: R5 VINH = VZ + VBE 1 + R6 || R7 and ( ) VZ + VBE ( ) R5 || R6 || R7 + R9 R5 R5 UVLO Hysteresis = VINH – VINL = VZ + R5 + R7 + R9 R5 || R7 + R9 R5 VBE – R6 || R7 R6 VINL = R5 || R7 + R9 R5 || R7 + R9 ( ( ) ) VIN The low shutdown and idle mode quiescent supply currents of the LT1619 can be utilized to implement trickle current start from high voltage input sources (such as a 36V to 72V telecom bus). The trickle current start-up circuit in Figure 11 is modified from the UVLO circuit of Figure 10. R10 is a high value resistor that charges the storage capacitor C2 during start-up. Before VCC reaches the upper UVLO trip point, Q2 holds the S/S pin low. The LT1619 draws shutdown mode current (≈15µA) from VCC. Q2 collector can also be tied to the VC pin through a diode as in Figure 10. The LT1619 will then draw idle mode quiescent current (≈140µA) from VCC. R10 should be able to charge C2 while supplying current to the UVLO circuit and the LT1619. Maximizing R5 to R9 values reduces power dissipation in R10. When VCC crosses the upper UVLO threshold, the LT1619 starts switching and its current consumption increases. Before the bootstrap takes over, the LT1619 draws its current from C2. VCC ramps towards the lower UVLO threshold. Increasing the value of C2 allows more time for the bootstrap circuit to establish itself before the converter enters undervoltage lockout. HV VIN R8 30k 8.2V The collector votage of Q2 is made about 1.4V at the VIN lower trip voltage. This is necessary to prevent the UVLO circuit from interfering with the feedback amplifier in the LT1619. + – R9 510k R7 51k CLK 1 2 D1 BAT85 3 Q2 2N2222 R5 51k Q1 2N2222 R6 51k S/S VIN FB DRV LT1619 VC GATE 8 VCC 7 C2 R8 1 R9 GND SENSE S/S VIN FB DRV 6 2 R7 4 BOOTSTRAP WINDING R10 5 1619 F10 VIN UPPER TRIP POINT = 10V VIN LOWER TRIP POINT = 8.4V Figure 10. Addition of Hysteresis UVLO While Synchronizing the LT1619. Component Values Shown are for the Upper and the Lower VIN Trip Points of 10V and 8.4V. In UVLO, the Gate Drive is Disabled by Pulling the VC Pin Low. Disabling the Clock Shuts Down the LT1619. If Not Synchronized, the Collector of Q2 Can Be Tied to the S/S Pin and the Diode D1 Can Be Eliminated 3 R5 Q2 Q1 R6 4 LT1619 VC GND GATE SENSE 8 D2 7 T1 6 5 1619 F11 Figure 11. Trickle Current Start-Up with Bootstrapped VCC 1619fa 11 LT1619 U W U U APPLICATIO S I FOR ATIO Increasing Ramp Compensation While Synchronizing The LT1619 is synchronized by forced discharge of the internal timing ramp. The timing ramp amplitude decreases as the synchronization frequency increases. Since the internal compensation ramp is derived from the timing ramp, reduced timing ramp results in diminished compensating ramp. If the LT1619 is synchronized at frequencies 20% to 30% higher than the free-running frequency, external ramp compensation will be required. Figures 12 and 13 show two such schemes. In both figures the compensating ramps are kept linear by making R11-C1 and R14-C2 products substantially higher than the synchronizing period. The compensation ramps, 1 CLK 2 3 4 S/S 8 VIN 7 DRV FB LT1619 6 GATE VC GND R11 100k D2 1N4148 Q1 2N2222 R12 2200Ω 5 SENSE MAIN POWER TRANSISTOR C1 220pF R13 51Ω RSENSE 1619 F12 Figure 12. Increasing Ramp Compensation. Q1 Buffers the C1 Ramp. D2 Discharges C1. Values Shown are for 10V Gate Drive and 15mV Ramp Across R13 at 90% Duty Cycle and 500kHz CLK 1 2 3 4 S/S VIN FB DRV LT1619 VC GND GATE SENSE PC Board Layout and Other Practical Considerations The following is recommended for PC board layout: 1. Trace lengths of the branches carrying switched current should be kept short. For example, in the boost converter of Figure 1, the circuit loop formed by M1, RSENSE, D1 and COUT carries switched current. The size of this loop must be minimized. RSENSE and COUT should be grounded to a single point on a large ground plane. This reduces switching noise and overall converter jitter. It is also preferable to ground the input capacitor C1 close to the common point between COUT and RSENSE although this is less important. 2. Keep the trace between the sense resistor and the SENSE pin short. When sensing high switch current, Kelvin connection to RSENSE is necessary. 3. Bypass both the VIN and DRV pins with ceramic capacitors next to the IC and the ground plane. 4. Keep high voltage switching nodes, such as the drain and gate of the MOSFET, away from the FB and VC pins. 8 5. Use inductor so that its ripple current is between 1/4 and 1/3 of its peak current. Steeper inductor current ramp results in sharper PWM comparator switching, hence less jitter. R14 8200Ω 7 6 whose peak amplitudes are made between 1/4 to 1/3 of the current limit threshold, are developed across R13. As a result, the effective current limit threshold is reduced by the sum of the compensating ramp and the offset voltage developed across R13 due to the SENSE pin input bias current (see Figure 5). Moreover, the current limit threshold becomes duty cycle dependent. D2 1N4148 D3 1N4148 R15 2400Ω 5 C2 2.2nF R13 51Ω RSENSE 6. In most cases, filtering the current sense signal is not necessary for jitter-free operation. 1619 F13 Figure 13. Externally Increasing Ramp Compensation. Similar to Figure 12 Except That C2 is Not Buffered with Transistor Figure 14 is the PC board layout for the 5V/8A and 12V/5A boost converters shown in Figures 15a and 16a. 1619fa 12 LT1619 U W U U APPLICATIO S I FOR ATIO CDRV CIN2 R1 RC 1 8 2 7 S LT1619 R2 CZ CP 3 6 4 5 G M1 D G S M1 D RSENSE CIN1 GND COUT1, 2 VOUT D1 L1 VIN 1619 F14 Figure 14. Recommended Component Placement for the Boost Converters in Figures 15a and 16a 1619fa 13 LT1619 U W U U APPLICATIO S I FOR ATIO VIN 3.3V 1 2 3 CP 150pF RC 75k 4 S/S VIN FB DRV LT1619 VC GND GATE SENSE 8 CIN2 1µF CERAMIC 7 CDRV 0.1µF CERAMIC 6 L1 1µH + CIN1 300µF 5 CZ 15nF M1 D1 FDS6680A ×2 COUT1 RSENSE 220µF ×4 5V 8A + COUT2 10µF CERAMIC R1 37400Ω R2 12400Ω 1619 F15a CIN1: SANYO POSCAP 6TPB150M ×2 COUT1: SANYO POSCAP 10TPB220M ×4 D1: MOTOROLA MBRB1545CT L1: SUMIDA CEPH149-1R0 RSENSE: PANASONIC 0.002Ω 1W Figure 15a. 3.3V to 5V/8A Boost Converter 89 VIN = 3.3V EFFICIENCY (%) 88 87 86 85 84 83 0.01 0.1 1 LOAD CURRENT (A) 10 1619 F15b Figure 15b. Efficiency of the 5V/8A Boost Converter 1619fa 14 LT1619 U W U U APPLICATIO S I FOR ATIO VIN 5V 1 2 3 CP 47pF RC 68.1k 4 S/S VIN FB DRV LT1619 VC GND GATE SENSE 8 CIN2 1µF CERAMIC 7 CDRV 0.1µF CERAMIC 6 L1 1.8µH + CIN1 100µF 5 CZ 2200pF M1 D1 FDS6690A ×2 COUT1 RSENSE 600µF 12V 5A + COUT2 10µF CERAMIC R1 107k R2 12400Ω 1619 F15a CIN1: SANYO OS-CON 10SA100M COUT1: SANYO OS-CON 16SA150M ×4 D1: MOTOROLA MBRB1545CT L1: SUMIDA CDEP149-1R8 RSENSE: PANASONIC 0.002Ω 1W Figure 16a. 5V to 12V/5A Boost Converter 95 94 VIN = 5V EFFICIENCY (%) 93 92 91 90 89 88 87 86 85 0.01 0.1 1 LOAD CURRENT (A) 10 1619 F16b Figure 16b. Efficiency of the 12V/5A Boost Converter 1619fa 15 LT1619 U TYPICAL APPLICATIO S VIN 4.75V TO 5.25V T1 –48V/0.5A • • 470µF 35V SANYO MV-GX + • + MBRS340T3 470µF 35V SANYO MV-GX 1µF + 1500µF 6.3V SANYO MV-GX • 1N749 4.3V • 4.7µF FILM 15Ω • 1 1.1k 2 3 2.2nF 36k 4 S/S VIN FB DRV LT1619 VC GATE GND SENSE 8 4.7µF FILM MBRS340T3 7 6 10µF SUD45N05-20L 50V, 0.018Ω 43nC 1M 30Ω 5 12k 220pF 2N5210 10.5k 1% 0.007Ω 22nF 2N5210 432k 1% 1619 F17a T1: COILTRONICS CTX02-14261, EFD20-3F3, 6 WINDINGS EACH, 12µH Figure 17a. 5V to – 48V Cuk Converter 90 VIN = 5.25V 89 88 EFFICIENCY (%) 87 86 VIN = 5V 85 VIN = 4.75V 84 83 82 81 80 79 10 100 LOAD CURRENT (mA) 1000 1619 F17b Figure 17b. Efficiency of the 5V to – 48V Cuk 1619fa 16 LT1619 U TYPICAL APPLICATIO S 10k CNY17-3 6.2V VIN 10.5V TO 13.7V 330pF 100V 43Ω 1/4W T1 • 0.22µF 50V 8.1V 1k 1W 43Ω W1 2.2µF 40V 470pF • • MBRS1100T3 330pF W4 50V 1 –32.5V 82k 2 10k 150µF 20V SANYO 20SV150M (OS-CON) 3 100Ω 4 FB DRV LT1619 VC GND GATE SENSE 1µF 50V 2.2µF 40V • 470Ω 2.49k 121Ω LT1431 1 8 COLL REF 2 7 NC NC 3 6 V+ FGND 4 5 NC SGND –65V MBRS1100T3 8 7 6 10µF T1 PHILIPS EFD20-3F3-A100-S CORE SET (0.013" GAP, AI = 100nH/T2 IRLR024N 55V, 0.065Ω QG = 15nC W4 6T TRIFILAR 28AWG W3 24T 28AWG W2 24T 28AWG W1 6T TRIFILAR 28AWG 5 1µF 0.008Ω 2mil POLYESTER FILM 1619 F18a Figure 18a. Isolated Local SLIC Power Supply (Flyback) 20W Total Output Power (65V/0.3A or 32.5V/0.6A) 90 85 80 EFFICIENCY (%) 0.1µF VIN S/S W2 220pF 62k W3 MBRS1100T3 20k 100Ω 75 70 65 60 VIN = 13.7V VIN = 12V VIN = 10.5V 55 50 10 100 LOAD CURRENT (mA) 1000 1619 F18b Figure 18b. Efficiency of the Isolated Local SLIC (Flyback) 1619fa 17 LT1619 U PACKAGE DESCRIPTION MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.2 – 3.45 (.126 – .136) 0.42 ± 0.04 (.0165 ± .0015) TYP 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.65 (.0256) BSC 8 7 6 5 0.52 (.206) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 ± 0.102 (.118 ± .004) NOTE 4 4.90 ± 0.15 (1.93 ± .006) DETAIL “A” 0° – 6° TYP GAUGE PLANE 0.53 ± 0.015 (.021 ± .006) DETAIL “A” 1 2 3 4 1.10 (.043) MAX 0.86 (.034) REF 0.18 (.077) SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 0.65 (.0256) BSC 0.13 ± 0.076 (.005 ± .003) MSOP (MS8) 0802 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 1619fa 18 LT1619 U PACKAGE DESCRIPTION S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 .050 BSC 8 7 6 5 N N .245 MIN .160 ±.005 1 .030 ±.005 TYP .150 – .157 (3.810 – 3.988) NOTE 3 .228 – .244 (5.791 – 6.197) 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° (0.254 – 0.508) .008 – .010 (0.203 – 0.254) 2 3 4 .053 – .069 (1.346 – 1.752) .004 – .010 (0.101 – 0.254) 0°– 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN 1 .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) .050 (1.270) BSC SO8 0502 1619fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LT1619 U TYPICAL APPLICATIO VIN 4V TO 28V T1 7 C4 1.5µF 100V R3 5.6k 9 10 • • 12 2 1 5• •4 8 3 6• • 11 C5 1.5µF 100V VOUT 5V 0.5A D3 MBRS0530T1 Q1 FMMT3904 D4 1N4687 4.3V LOW LEVEL (IZT = 50µA) D2 MBRS340T3 8 7 Q3 MMFT3055VL 6 VIN DRV GATE 5 R7 30Ω SENSE LT1619 2 FB S/S GND 1 4 C8 1µF 16V R5 100Ω R6 3.74k 1% C1 0.022µF C6 10µF 10V VC 3 R9 2.2k C9 2.2nF C7 220pF R8 0.015Ω R10 1.24k 1% C4, C5: VITRAMON VJ1825Y155MXB (1825/X7R) C6: TAIYO YUDEN LMK325BJ106MN (1210/X7R) C8: TAIYO YUDEN EMK316BJ105ML (1206/X7R) T1: COILTRONICS VP1-0190 (ER11/5, 6 WINDINGS EACH 12.2µH) 1619 TA01 Figure 19. 2.5W, 4VIN-28VIN to 5V/0.5A Nonisolated Supply RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1370 500kHz, 6A Switching Regulator Boost, Buck, Flyback, Forward, Inverting; 42V Switch Voltage LT1372 500kHz, 1.5A Switching Regulator SO-8, 2.7V ≤ VIN ≤ 30V, 42V Switch Voltage LT1613 1.4MHz, SOT-23 DC/DC Converter Fixed Frequency, 0.9V ≤ VIN ≤ 10V, 36V Switch Voltage LTC1624 Switching Regulator Controller SO-8, Drives N-Ch MOSFET, 3.5V ≤ VIN ≤ 36V LT1680 Synchronous Boost Controller Synchronous Operation for High Current/High Efficiency LT1698 Isolated or Nonisolated 10W to 100W Power Supply Solution with Multiple Outputs 50% Lower Cost than Quarter Brick and Half Brick Modules Fits the Foot Print LTC1871 No RSENSE Boost, Flyback, SEPIC Controller 2.5V ≤ VIN ≤ 36V, Current Mode Control, 50kHz to 1MHz Adjustabe Frequency, MSOP-10 LTC1872 SOT-23 Boost Controller 550kHz Fixed Frequency, Current Mode LT1946 1.2MHz, 65A DC/DC Converter MSOP-8, 5V to 12V/400mA LT3710/LT3781 Isolated or Nonisolated 10W to 100W Power Supply Solution with Multiple Outputs 50% Lower Cost than Quarter Brick and Half Brick Modules Fits the Foot Print 1619fa 20 Linear Technology Corporation LT/TP 1002 1K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2000