LT1952 Single Switch Synchronous Forward Controller U FEATURES DESCRIPTIO ■ The LT®1952 is a current mode PWM controller optimized to control the forward converter topology, using one primary MOSFET. The LT1952 provides synchronous rectifier control, resulting in extremely high efficiency. A programmable Volt-Second clamp provides a safeguard for transformer reset that prevents saturation. This allows a single MOSFET on the primary side to reliably run at greater than 50% duty cycle for high MOSFET, transformer and rectifier utilization. The LT1952 includes soft-start for controlled exit from shutdown, overcurrent conditions and undervoltage lockout. A precision 100mV current limit threshold, independent of duty cycle, combines with soft-start to provide hiccup short circuit protection. Micropower start-up allows the LT1952 to be efficiently started from high input voltages. Programmable slope compensation and leading edge blanking allow optimization of loop bandwidth with a wide range of inductors and MOSFETs. The LT1952 can be programmed over a 100kHz to 500kHz frequency range and the part can be synchronized to an external clock. The error amplifier is a true op amp, allowing a wide range of compensation networks. The LT1952 is available in a small 16-pin SSOP package. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Synchronous Rectifier Control for High Efficiency Programmable Volt-Second Clamp Output Power Levels from 25W to 500W Low Current Start-Up True PWM Soft-Start Low Stress Short Circuit Protection Precision 100mV Current Limit Threshold Adjustable Delay for Synchronous Timing Accurate Shutdown Threshold with Programmable Hysteresis Programmable Slope Compensation Programmable Leading Edge Blanking Programmable Frequency (100kHz to 500kHz) Synchronizable to an External Clock up to 1.5 • fOSC Internal 1.23V Reference 2.5V External Reference Current Mode Control Small 16-Pin SSOP Package U APPLICATIO S ■ ■ Telecommunications Power Supplies Industrial and Distributed Power Isolated and Non-Isolated DC/DC Converters , LTC and LT are registered trademarks of Linear Technology Corporation. U ■ TYPICAL APPLICATIO 36V to 72V Input, 12V at 20A Semi-Regulated Bus Converter 40k SUPPLY FROM BIAS WINDING OF T1 16V L1 PA1494.242 T1 PA0905 Si7370 ×2 COMP LT1952 340k 13k PH4840 ×2 OC ISENSE 0.005Ω SD_VSEC LTC3900 FB FG T2 SYNC SOUT GND ROSC 40k 12 10 CG 220pF 560Ω 8 36 0.1µF 40k 14 SYNC PGND BLANK DELAY 0.1µF 16 47µF 16V X5R ×2 VOUT (V) VIN 100k Si7450 OUT SS_MAXDC 12V Bus Converter VOUT vs VIN VOUT 12V 20A 10µF VIN VREF 52.3k VIN 42 48 54 VIN (V) 60 66 72 1952 TA01b 178k 1952 TA01 1952f 1 LT1952 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) ORDER PART NUMBER TOP VIEW VIN (Note 8) ............................................... –0.3V to 25V SYNC, SS_MAXDC, SD_VSEC, ISENSE, OC, COMP, BLANK, DELAY ......................... –0.3V to 6V FB ................................................................ –0.3V to 3V ROSC ...................................................................................... –50µA VREF .................................................................... –10mA Operating Junction Temperature Range (Notes 2, 5) ....................................... –40°C to 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C COMP 1 16 SOUT FB 2 15 VIN ROSC 3 14 OUT SYNC 4 13 PGND SS_MAXDC 5 12 DELAY VREF 6 11 OC SD_VSEC 7 10 ISENSE GND 8 9 LT1952EGN LT1952IGN GN PART MARKING BLANK 1952E 1952I GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 110°C/W, θJC = 40°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. COMP = open, FB = 1.4V, ROSC = 178k, SYNC = 0V, SS_MAXDC = VREF, VREF = 0.1µF, SD_VSEC = 2V, BLANK = 40k, DELAY = 40k, ISENSE = 0V, OC = 0V, OUT = 1nF, VIN = 15V, SOUT = open, unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER Operational Input Voltage I(VREF) = 0µA VIN Quiescent Current I(VREF) = 0µA, FB = 0V, ISENSE = OC = Open VIN Startup Current FB = 0V, SS_MAXDC = 0V (Notes 4, 9) VIN Shutdown Current SD_VSEC = 0V SD_VSEC Threshold 10V < VIN < 25V SD_VSEC (ON) Current SD_VSEC = SD_VSEC Threshold + 100mV SD_VSEC (OFF) Current SD_VSEC = SD_VSEC Threshold – 100mV ● VIN OFF ● ● 1.261 25 V 5.2 6.5 mA 460 700 µA 240 350 µA 1.32 1.379 0 V µA 9.5 11.2 12.9 µA VIN ON ● 12.75 14.25 15.75 V VIN OFF ● 8.0 8.75 9.25 V VIN HYSTERESIS ● 3.75 5.5 6.75 V ● 2.425 2.5 2.575 V VREF Output Voltage I(VREF) = 0µA Line Regulation I(VREF) = 0µA, 10V < VIN < 25V 1 10 mV Load Regulation 0µA < I(VREF) < 2.5mA 1 10 mV 165 200 240 kHz 80 440 100 500 120 560 kHz kHz OSCILLATOR Frequency: fOSC ROSC = 178k, FB = 1V Minimum Programmable fOSC Maximum Programmable fOSC ROSC = 365k ROSC = 64.9k, COMP = 2.5V, SD_VSEC = 2.64V SYNC Input Resistance ● 18 kΩ SYNC Switching Threshold FB = 1V 1.5 2.2 SYNC Frequency/fOSC FB = 1V (Note 7) 1.25 1.5 fOSC Line Reg FB = 1V, ROSC = 178k; 10V < VIN < 25V, SS_MAXDC = 1.84V 0.05 0.33 VROSC ROSC Pin voltage 1 V %/V V 1952f 2 LT1952 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. COMP = open, FB = 1.4V, ROSC = 178k, SYNC = 0V, SS_MAXDC = VREF, VREF = 0.1µF, SD_VSEC = 2V, BLANK = 40k, DELAY = 40k, ISENSE = 0V, OC = 0V, OUT = 1nF, VIN = 15V, SOUT = open, unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNITS 1.201 1.226 1.250 V –75 –200 nA ERROR AMPLIFIER FB Reference Voltage 10V < VIN < 25V, VOL + 0.2V < COMP < VOH – 0.2 FB Input Bias Current FB = FB Reference Voltage Open Loop Voltage Gain VOL + 0.2V < COMP < VOH – 0.2 ● 65 85 dB Unity Gain Bandwidth (Note 6) 3 MHz COMP Source Current FB = 1V, COMP = 1.6V –4 –9 mA COMP Sink Current COMP = 1.6V 4 10 mA COMP Current (Disabled) FB = VREF, COMP = 1.6V 18 23 COMP High Level: VOH FB = 1V, I(COMP) = –250µA 2.7 3.2 28 V COMP Active Threshold FB = 1V, SOUT Duty Cycle > 0 % 0.7 1.0 V COMP Low Level: VOL I(COMP) = 250µA µA 0.15 0.4 V 220 243 mV CURRENT SENSE ISENSE Maximum Threshold COMP = 2.5V, FB = 1V ISENSE Input Current (Duty Cycle = 0%) ISENSE Input Current (Duty Cycle = 80%) COMP = 2.5V, FB = 1V (Note 4) COMP = 2.5V, FB = 1V (Note 4) 197 –8 –35 ● OC Threshold 98 µA µA 107 116 mV –100 nA OC Input Current (OC = 100mV) –50 Default Blanking Time COMP = 2.5V, FB = 1V (Note 10) 180 ns Adjustable Blanking Time COMP = 2.5V, FB = 1V, RBLANK = 120k 540 ns 1 V VBLANK SOUT DRIVER SOUT Clamp Voltage I(GATE) = 0µA, COMP = 2.5V, FB = 1V 10.5 SOUT Low Level I(GATE) = 25mA SOUT High Level I(GATE) = –25mA, VIN = 12V, COMP = 2.5V, FB = 1V 10 SOUT Active Pull-Off in Shutdown VIN = 5V, SD_VSEC = 0V, SOUT = 1V 1 SOUT to OUT (Rise) DELAY (tDELAY) COMP = 2.5V, FB = 1V (Note 10) RDELAY = 120k VDELAY 12 13.5 V 0.5 0.75 V V mA 40 120 ns ns 0.9 V 50 ns OUT DRIVER OUT Rise Time FB = 1V, CL = 1nF (Notes 3, 6) OUT Fall Time FB = 1V, CL = 1nF (Notes 3, 6) OUT Clamp Voltage I(GATE) = 0µA, COMP = 2.5V, FB = 1V OUT Low Level I(GATE) = 20mA I(GATE) = 200mA OUT High Level I(GATE) = –20mA, VIN = 12V, COMP = 2.5V, FB = 1V I(GATE) = –200mA, VIN = 12V, COMP = 2.5V, FB = 1V OUT Active Pull-Off in Shutdown VIN = 5V, SD_VSEC = 0V, OUT = 1V 30 11.5 ns 13 14.5 V 0.45 1.25 0.75 1.8 V V 9.9 V 9.75 V 20 mA 1952f 3 LT1952 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. COMP = open, FB = 1.4V, ROSC = 178k, SYNC = 0V, SS_MAXDC = VREF, VREF = 0.1µF, SD_VSEC = 2V, BLANK = 40k, DELAY = 40k, ISENSE = 0V, OC = 0V, OUT = 1nF, VIN = 15V, SOUT = open, unless otherwise specified. PARAMETER CONDITIONS MIN TYP OUT Max Duty Cycle COMP = 2.5V, FB = 1V, RDELAY = 10k (fOSC = 200kHz) SD_VSEC = 1.4V, SS_MAXDC = VREF 83 90 OUT Max Duty Cycle Clamp COMP = 2.5V, FB = 1V, RDELAY = 10k (fOSC = 200kHz) SD_VSEC = 1.32V, SS_MAXDC = 1.84V SD_VSEC = 2.64V, SS_MAXDC = 1.84V 63.5 25 72 33 MAX UNITS % 80.5 41 % % SOFT-START SS_MAXDC Low Level: VOL I(SS_MAXDC) = 150µA, OC = 1V 0.2 V SS_MAXDC Soft-Start Reset Threshold Measured on SS_MAXDC 0.45 V SS_MAXDC Active Threshold FB = 1V, DC > 0% 0.8 V SS_MAXDC Input Current (Soft-Start Pulldown: Idis) SS_MAXDC = 1V, SD_VSEC = 1.4V, OC = 1V 800 µA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1952EGN is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT1952IGN is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 3: Rise and Fall times are measured at 10% and 90% levels. Note 4: Guaranteed by correlation to static test. Note 5: This IC includes over-temperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when over-temperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 6: Guaranteed but not tested. Note 7: Maximum recommended SYNC frequency = 500kHz. Note 8: In applications where the VIN pin is supplied via an external RC network from a SYSTEM VIN > 25V, an external zener with clamp voltage VIN ON(MAX) < VZ < 25V should be connected from the VIN pin to ground. Note 9: VIN start-up current is measured at VIN = VIN ON – 0.25V and scaled by x 1.18 (to correlate to worst case VIN start-up current at VIN ON). Note 10: Timing for R = 40k derived from measurement with R = 240k. 1952f 4 LT1952 U W TYPICAL PERFOR A CE CHARACTERISTICS Switching Frequency vs Temperature FB Voltage vs Temperature 500 245 1.24 1.23 1.22 1.21 1.20 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 VIN = 15V 450 SD_VSEC = 0V 230 VIN SHUTDOWN CURRENT (µA) SWITCHING FREQUENCY (kHz) 1.25 FB VOLTAGE (V) VIN Shutdown Current vs Temperature 215 200 185 170 –25 50 25 0 75 TEMPERATURE (°C) 100 VIN Start-up Current vs Temperature VIN IQ (mA) VIN STARTUP CURRENT (µA) 350 5.0 4.5 300 4.0 250 100 3.5 –50 125 –25 50 25 0 75 TEMPERATURE (°C) 100 1952 G04 100 12 1952 G07 6 –50 RISENSE = 0k 1.0 0.8 0.6 0.4 8 125 125 1.2 COMP (V) VIN (V) SD_VSEC PIN CURRENT (µA) VIN TURN ON VOLTAGE VIN TURN OFF VOLTAGE 50 25 0 75 TEMPERATURE (°C) 100 1.4 10 0µA PIN CURRENT AFTER PART TURN ON 50 25 0 75 TEMPERATURE (°C) COMP Active Threshold vs Temperature 14 5 –25 1952 G06 1.6 16 10 –25 1.27 1.22 –50 125 18 PIN CURRENT BEFORE PART TURN ON 0 –50 1.32 VIN Turn ON/OFF Voltage vs Temperature 15 125 1.37 1952 G05 SD_VSEC Pin Current vs Temperature 100 1.42 5.5 400 50 25 0 75 TEMPERATURE (°C) 1952 G03 OC = OPEN 6.0 450 –25 SD_VSEC Turn ON Threshold vs Temperature 500 50 25 0 75 TEMPERATURE (°C) 200 100 –50 125 SD_VSEC TURN ON THRESHOLD (V) 6.5 550 –25 250 VIN IQ vs Temperature SD_VSEC = 1.4V 200 –50 300 1952 G02 1952 G01 600 350 150 155 –50 125 400 0.2 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1952 G08 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1952 G09 1952f 5 LT1952 U W TYPICAL PERFOR A CE CHARACTERISTICS 12.5 FB = 1V COMP = 1.6V COMP SINK CURRENT (mA) COMP SOURCE CURRENT (mA) • (–1) 12.5 COMP Sink Current vs Temperature 10.0 7.5 CURRENT OUT OF PIN 5.0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 10.0 7.5 –25 50 25 0 75 TEMPERATURE (°C) 80 40 1.0 2.0 1.5 COMP (V) 3.0 2.5 –25 210 30 20 10 0 –25 50 25 0 75 TEMPERATURE (°C) 100 125 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 1952 G15 OC (Over-Current) Threshold vs Temperature 120 125 TA = 25°C 1952 G14 225 100 1952 G12 40 220 1952 G13 Blank Duration vs Temperature 800 PRECISION OVER-CURRENT THRESHOLD INDEPENDENT OF DUTY CYCLE RSLOPE = 470Ω 195 110 BLANK DURATION (ns) 205 OC THRESHOLD (mV) RSLOPE = 0Ω 215 100 90 RBLANK = 120k 600 400 200 185 175 50 25 0 75 TEMPERATURE (°C) ISENSE Pin Current (Out of Pin) vs Duty Cycle 230 ISENSE Maximum Threshold vs Duty Cycle (Programming Slope Compensation) ISENSE MAX THRESHOLD (mV) 20 0 –50 125 COMP = 2.5V RISENSE = 0k 200 –50 0 0.5 100 ISENSE PIN CURRENT (µA) OC THRESHOLD ISENSE MAX THRESHOLD (mV) ISENSE MAX THRESHOLD (mV) 240 160 0 30 ISENSE Maximum Threshold vs Temperature TA = 25°C RISENSE = 0k 120 40 1952 G11 ISENSE Maximum Threshold vs COMP 200 FB = VREF COMP = 1.6V 10 1952 G10 240 50 FB = 1.4V COMP = 1.6V 5.0 –50 125 (Disabled) COMP Pin Current vs Temperature COMP PIN CURRENT (µA) COMP Source Current vs Temperature TA = 25°C COMP = 2.5V 0 RBLANK = 40k RSLOPE = 1k 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 1952 G16 80 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1952 G17 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1952 G18 1952f 6 LT1952 U W TYPICAL PERFOR A CE CHARACTERISTICS tDELAY: SOUT Rise to OUT Rise vs Temperature BLANK Duration vs RBLANK 1000 tDELAY: SOUT Rise to OUT Rise vs RDELAY 200 200 TA = 25°C 800 TA = 25°C 160 150 400 tDELAY (ns) tDELAY (ns) BLANK (ns) RDELAY = 120k 600 100 50 200 120 80 40 RDELAY = 40k 0 0 20 40 0 –50 60 80 100 120 140 160 RBLANK (k) 0 –25 50 25 0 75 TEMPERATURE (°C) 100 1952 G26 OUT MAX DUTY CYCLE CLAMP (%) OUT DUTY CYCLE (%) OUT RISE/FALL TIME (ns) 90 100 tf 50 90 80 25 TA = 25°C SS_MAXDC = 2.5V SD_VSEC = 1.4V 0 0 70 100 5000 2000 1000 3000 4000 OUT LOAD CAPACITANCE (pF) 200 300 fOSC (kHz) 400 1952 G20 30 20 1.60 SD_VSEC = 2.64V 1.84 SS_MAXDC (V) 1952 G23 20 10 TA = 25°C SS_MAXDC = 1.84V fOSC = 200kHz RDELAY = 10k 1.65 1.98 SD_VSEC (V) 2.64 2.31 1.2 1.0 2.08 1.96 1.84 ACTIVE THRESHOLD 0.8 0.6 0.4 RESET THRESHOLD 0.2 1.72 1.60 100 2.08 30 SS_MAXDC Reset and Active Thresholds vs Temperature SS_MAXDC (mV) SS_MAXDC (V) OUT MAX DUTY CYCLE CLAMP (%) 40 40 1952 G22 TA = 25°C SD_VSEC = 1.32V 2.20 RDELAY = 10k SD_VSEC = 1.32V SD_VSEC = 1.98V 50 0 1.32 500 2.32 70 50 60 SS_MAXDC Setting vs fOSC (for OUT DC = 72%) 90 60 80 70 1952 G21 OUT: Max Duty Cycle CLAMP vs SS_MAXDC TA = 25°C fOSC = 200kHz 80 R DELAY = 10k 60 80 100 120 140 160 RDELAY (k) OUT: Max Duty Cycle CLAMP vs SD_VSEC 100 tr 40 1952 G27 OUT: Max Duty Cycle vs fOSC TA = 25°C 75 20 1952 G19 OUT Rise/Fall Time vs OUT Load Capacitance 125 0 125 200 300 fOSC (kHz) 400 500 1952 G24 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1952 G25 1952f 7 LT1952 U U U PI FU CTIO S COMP (Pin 1): Output Pin of the Error Amplifier. The error amplifier is an op amp, allowing various compensation networks to be connected between the COMP pin and FB pin for optimum transient response. The voltage on this pin corresponds to the peak current of the external FET. Full operating voltage range is between 0.8V and 2.5V corresponding to 0mV to 220mV at the ISENSE pin. For applications using the 100mV OC pin for over-current detection, typical operating range for the COMP pin is 0.8V to 1.6V. For isolated applications where COMP is controlled by an opto-coupler, the COMP pin output drive can be disabled with FB = VREF, reducing the COMP pin current to (COMP – 0.7)/40k. FB (Pin 2): Monitors the output voltage via an external resistor divider and is compared with an internal 1.23V reference by the error amplifier. FB connected to VREF disables error amplifier output. ROSC (Pin 3): A resistor to ground programs the operating frequency of the IC between 100kHz and 500kHz. Nominal voltage on the ROSC pin is 1.0V. SYNC (Pin 4): Used to Synchronize the Internal Oscillator to an External Signal. It is directly logic compatible and can be driven with any signal between 10% and 90% duty cycle. If unused, the pin can be left open or connected to ground. SS_MAXDC (Pin 5): External resistor divider from VREF sets maximum duty cycle clamp (SS_MAXDC = 1.84V, SD_VSEC = 1.32V gives 72% duty cycle). Capacitor on SS_MAXDC pin in combination with external resistor divider sets soft-start timing. VREF (Pin 6): The output of an internal 2.5V reference which supplies control circuitry in the IC. Capable of sourcing up to 2.5mA drive for external use. Bypass to ground with a 0.1µF ceramic capacitor. SD_VSEC (Pin 7): The SD_VSEC pin, when pulled below its accurate 1.32V threshold, is used to turn off the IC and reduce current drain from VIN. The SD_VSEC pin is connected to system input voltage through a resistor divider to define undervoltage lockout (UVLO) and to provide a Volt-Second clamp on the OUT pin. A 10µA pin current hysteresis allows external programming of UVLO hysteresis. GND (Pin 8): Analog Ground. BLANK (Pin 9): A resistor to ground adjusts the extended blanking period of the over-current and current sense amplifier outputs during FET turn on — to prevent false current limit trip. Increasing the resistor value increases the blanking period. ISENSE (Pin 10): The Current Sense Input for the Control Loop. Connect this pin to the sense resistor in the source of the external power MOSFET. A resistor in series with the ISENSE pin programs slope compensation. OC (Pin 11): An accurate 100mV threshold, independent of duty cycle, for over-current detection and trigger of soft-start. Connect this pin directly to the sense resistor in the source of the external power MOSFET. DELAY (Pin 12): A resistor to ground adjusts the delay period between SOUT rising edge and OUT rising edge. Used to maximize efficiency in forward converter applications by adjusting the control timing of secondary side synchronous rectifier MOSFETs. Increasing the resistor value increases the delay period. PGND (Pin 13): Power Ground. OUT (Pin 14): Drives the Gate of an N-channel MOSFET between 0V and VIN. OUT is actively clamped to 13V. Active pull-off exists in shutdown (see electrical specification). VIN (Pin 15): Input Supply for the Part. It must be closely decoupled to ground. An internal undervoltage lockout threshold exists for VIN at approximately 14.25V on and 8.75V off. SOUT (Pin 16): Switched Output in Phase with OUT Pin. Provides sync signal for control of secondary side FETs in forward converter applications requiring highly efficient synchronous rectification. SOUT is actively clamped to 12V. Active pull-off exists in shutdown (see electrical specification). 1952f 8 LT1952 W UW TI I G DIAGRA tDELAY: PROGRAMMABLE SYNCHRONOUS DELAY SOUT OUT SS_MAXDC FAULTS TRIGGERING SOFT-START VIN < 8.75V OR SD_VSEC < 1.32V (UVLO) OR OC > 100mV (OVER-CURRENT) 0.8V (ACTIVE THRESHOLD) 0.45V (RESET THRESHOLD) 0.2V SOFT-START LATCH RESET: SOFT-START LATCH SET VIN > 14.25V (> 8.75V IF LATCH SET BY OC) AND SD_VSEC > 1.32V AND OC < 100mV AND SS_MAXDC < 0.45V 1952 F01 Figure 1. Timing Diagram W BLOCK DIAGRA VIN VREF SS_MAXDC 15 6 5 460µA START-UP INPUT CURRENT 14.25V ON 8.75V OFF 0.45V VREF >90% + SOFT-START CONTROL – + 2.5V – R SOURCE 2.5mA Q – S + ±50mA 1.23V – IHYST 11µA SD_VSEC = 1.32V 0µA SD_VSEC > 1.32V – ADAPTIVE MAXIMUM DUTY CYCLE CLAMP 16 SOUT 12V + + (TYPICAL 200kHz) SD_VSEC 7 OSC 1.32V ROSC 3 S (LINEAR) SLOPE COMP 8µA 0% DC 35µA 80% DC (100 TO 500)kHz RAMP Q ON DELAY DRIVER ±1A 14 OUT R 13 PGND SYNC 4 13V 1.23V + BLANK (VOLTAGE) ERROR AMPLIFIER SENSE OVER –CURRENT+ –CURRENT+ – 0mV TO 220mV 100mV 11 OC 10 ISENSE 2 1 8 FB COMP GND 12 9 DELAY BLANK 1952 BD Figure 2. Block Diagram 1952f 9 LT1952 U OPERATIO Introduction The LT1952 is a current mode synchronous PWM controller optimized for control of the simplest forward converter topology — using only one primary MOSFET. The LT1952 is ideal for 25W to 500W power systems where very high efficiency and reliability, low complexity and cost are required in a small space. Key features of the LT1952 include an adaptive maximum duty cycle clamp for the single primary MOSFET. An additional output signal is included for synchronous rectifier control. A precision 100mV threshold senses over-current conditions and triggers Soft-Start for low stress short circuit protection and control. The key functions of the LT1952 are shown in the Block Diagram in Figure 2. Part Startup In normal operation the SD_VSEC pin must exceed 1.32V and the VIN pin must exceed 14.25V to allow the part to turn on. This combination of pin voltages allows the 2.5V VREF pin to become active, supplying the LT1952 control circuitry and providing up to 2.5mA external drive. SD_VSEC threshold can be used for externally programming an undervoltage lockout (UVLO) threshold on the system input voltage. Hysteresis on the UVLO threshold can also be programmed since the SD_VSEC pin draws 11µA just before part turn on and 0µA after part turn on. With the LT1952 turned on, the VIN pin can drop as low as 8.75V before part shutdown occurs. This VIN pin hysteresis (5.5V) combined with low 460µA start-up input current allows low power start-up using a resistor/capacitor network from system VIN to supply the VIN pin (Figure 3). The VIN capacitor value is chosen to prevent VIN falling below 8.75V before an auxiliary winding in the converter takes over supply to the VIN pin. Output Drivers The LT1952 has two outputs, SOUT and OUT. The OUT pin provides a ±1A peak MOSFET gate drive clamped to 13V. The SOUT pin has a ±50mA peak drive clamped to 12V and provides sync signal timing for synchronous rectification control. For SOUT and OUT turn on, a PWM latch is set at the start of each main oscillator cycle. OUT turn on is delayed from SOUT turn on by a time tDELAY (Figure 2). tDELAY is programmed using a resistor from the DELAY pin to ground and is used to set the timing control of the secondary synchronous rectifiers for optimum efficiency. SOUT and OUT turn off at the same time each cycle by one of three methods: (1) MOSFET peak current sense at ISENSE pin (2) Adaptive maximum duty cycle clamp reached during load/line transients (3) Maximum duty cycle reset of the PWM latch During any of the following conditions — low VIN, low SD_VSEC or over-current detection at the OC pin — a soft-start event is latched and both SOUT and OUT turn off immediately (Figure 1). Leading Edge Blanking To prevent MOSFET switching noise causing premature turn off of SOUT or OUT, programmable leading edge blanking exists. This means both the current sense comparator and over-current comparator outputs are ignored during MOSFET turn on and for an extended period after the OUT leading edge (Figure 6). The extended blanking period is programmable by adjusting a resistor from the BLANK pin to ground. Adaptive Maximum Duty Cycle Clamp (Volt-Second Clamp) For forward converter applications using the simplest topology of a single MOSFET on the primary, a maximum switch duty cycle clamp which adapts to transformer input voltage is necessary for reliable control of the MOSFET. This volt-second clamp provides a safeguard for transformer reset that prevents transformer saturation. Instantaneous load changes can cause the converter loop to demand maximum duty cycle. If the maximum duty cycle of the switch is too great, the transformer reset voltage can exceed the voltage rating of the primary-side MOSFET with catastrophic damage. Many converters solve this problem 1952f 10 LT1952 U OPERATIO by limiting the operational duty cycle of the MOSFET to 50% or less — or by using a fixed (non-adaptive) maximum duty cycle clamp with very large voltage rated MOSFETs. The LT1952 provides a volt-second clamp to allow MOSFET duty cycles well above 50%. This gives greater power utilization for the MOSFET, rectifiers and transformer resulting in less space for a given power output. In addition, the volt-second clamp allows a reduced voltage rating on the MOSFET resulting in lower RDSON for greater efficiency. The volt-second clamp defines a maximum duty cycle ‘guard rail’ which falls when system input voltage increases. The LT1952 SD_VSEC and SS_MAXDC pins provide a capacitorless, programmable volt-second clamp solution. Some controllers with volt-second clamps control switch maximum duty cycle by using an external capacitor to program maximum switch ON time. Such techniques have a volt-second clamp inaccuracy directly related to the error of the external capacitor/pin capacitance and the error/drift of the internal oscillator. The LT1952 uses simple resistor ratios to implement a volt-second clamp without the need for an accurate external capacitor and with an order of magnitude less dependency on oscillator error. An increase of voltage at the SD_VSEC pin causes the maximum duty cycle clamp to decrease. If SD_VSEC is resistively divided down from transformer input voltage, a volt-second clamp is realised. To adjust the initial maximum duty cycle clamp, the SS_MAXDC pin voltage is programmed by a resistor divider from the 2.5V VREF pin to ground. An increase of programmed voltage on SS_MAXDC pin provides an increase of switch maximum duty cycle clamp. Soft-Start The LT1952 provides true PWM soft-start by using the SS_MAXDC pin to control soft-start timing. The proportional relationship between SS_MAXDC voltage and switch maximum duty cycle clamp allows the SS_MAXDC pin to slowly ramp output voltage by ramping the maximum switch duty cycle clamp — until switch duty cycle clamp seamlessly meets the natural duty cycle of the converter. A soft-start event is triggered whenever VIN is too low, SD_VSEC is too low (UVLO), or a 100mV over-current threshold at OC pin is exceeded. Whenever a soft-start event is triggered, switching at SOUT and OUT is stopped immediately. The SS_MAXDC pin is discharged and only released for charging when it has fallen below it’s reset threshold of 0.45V and all faults have been removed. Increasing voltage on the SS_MAXDC pin above 0.8V will increase switch maximum duty cycle. A capacitor to ground on the SS_MAXDC pin in combination with a resistor divider from VREF, defines the soft-start timing. Current Mode Topology (ISENSE Pin) The LT1952 current mode topology eases frequency compensation requirements because the output inductor does not contribute to phase delay in the regulator loop. This current mode technique means that the error amplifier (nonisolated applications) or the optocoupler (isolated applications) commands current (rather than voltage) to be delivered to the output. This makes frequency compensation easier and provides faster loop response to output load transients. A resistor divider from the application’s output voltage generates a voltage at the inverting FB input of the LT1952 error amplifier (or to the input of an external optocoupler) and is compared to an accurate reference (1.23V for LT1952). The error amplifier output (COMP) defines the input threshold (ISENSE) of the current sense comparator. COMP voltages between 0.8V (active threshold) and 2.5V define a maximum ISENSE threshold from 0mV to 220mV. By connecting ISENSE to a sense resistor in series with the source of an external power MOSFET, the MOSFET peak current trip point (turn off) can be controlled by COMP level and hence by the output voltage. An increase in output load current causing the output voltage to fall, will cause COMP to rise, increasing ISENSE threshold, increasing the current delivered to the output. For isolated applications, the error amplifier COMP output can be disabled to allow the optocoupler to take control. Setting FB = VREF disables the error amplifier COMP output, reducing pin current to (COMP – 0.7)/40k. 1952f 11 LT1952 U OPERATIO Slope Compensation The current mode architecture requires slope compensation to be added to the current sensing loop to prevent subharmonic oscillations which can occur for duty cycles above 50%. Unlike most current mode converters which have a slope compensation ramp that is fixed internally, placing a constraint on inductor value and operating frequency, the LT1952 has externally adjustable slope compensation. Slope compensation can be programmed by inserting an external resistor (RSLOPE) in series with the ISENSE pin. The LT1952 has a linear slope compensation ramp which sources current out of the ISENSE pin of approximately 8µA at 0% duty cycle to 35µA at 80% duty cycle. Over-Current Detection and Soft-Start (OC Pin) An added feature to the LT1952 is a precise 100mV sense threshold at the OC pin used to detect over-current conditions in the converter and set a soft-start latch. The OC pin is connected directly to the source of the primary side MOSFET to monitor peak current in the MOSFET (Figure 7). The 100mV threshold is constant over the entire duty cycle range of the converter because it is unaffected by the slope compensation added to the ISENSE pin. Synchronizing A SYNC pin allows the LT1952 oscillator to be synchronized to an external clock. The SYNC pin can be driven from a logic level output, requiring less than 0.8V for a logic level low and greater than 2.2V for a logic level high. Duty cycle should run between 10% and 90%. To avoid loss of slope compensation during synchronization, the free running oscillator frequency (fOSC) should be programmed to 80% of the external clock frequency (fSYNC). The RSLOPE resistor chosen for non-synchronized operation should be increased by 1.25x (= fSYNC/fOSC). U W U U APPLICATIO S I FOR ATIO Shutdown and Programming Undervoltage Lockout The LT1952 has an accurate 1.32V shutdown threshold at the SD_VSEC pin. This threshold can be used in conjunction with a resistor divider to define the undervoltage lockout threshold (UVLO) of the system input voltage (VS) to the power converter (Figure 3). A pin current hysteresis (11µA before part turn on, 0µA after part turn on) allows UVLO hysteresis to be programmed. Calculation of the ON/OFF thresholds for the supply (SVIN) to the power converter can be made as follows: VS OFF Threshold = 1.32[1 + (R1/R2)] VS ON Threshold = SVIN OFF + (11µA • R1) A simple open drain transistor can be added to the resistor divider network at the SD_VSEC pin to control the turn off of the LT1952 (Figure 3). The SD_VSEC pin must not be left open since there must be an external source current >11µA to lift the pin past its 1.32V threshold for part turn on. SYSTEM INPUT (VS) R1 SD_VSEC OPTIONAL SHUTDOWN TRANSISTOR – 11µA R2 1.32V + ON OFF LT1952 1952 F03 Figure 3. Programming Undervoltage Lockout (UVLO) Micropower Start-Up: Selection of Start-Up Resistor and Capacitor for VIN The LT1952 uses turn-on voltage hysteresis at the VIN pin and low start-up current to allow micro-power start-up (Figure 4). The LT1952 monitors VIN pin voltage to allow part turn on at 14.25V and part turn off at 8.75V. Low startup current (460µA) allows a large resistor to be connected 1952f 12 LT1952 U W U U APPLICATIO S I FOR ATIO between system input supply and VIN. Once the part is turned on, input current increases to drive the IC (4.5mA) and the output drivers (IDRIVE). A large enough capacitor is chosen at the VIN pin to prevent VIN falling below 8.5V before an auxiliary winding in the converter takes over supply to VIN. This technique allows a simple resistor/ capacitor for start-up which draws low power from the system supply to the converter. The values for RSTART and CSTART are given by: RSTART(MAX) = (VS(MIN) – VIN ON(max))/ISTART(MAX) CSTART(MIN) = (IQ(MAX) + IDRIVE(MAX)) • tSTART/ VIN HYST(MIN) Example: For VS(MIN) = 36V, VIN ON(MAX) = 15.75V, ISTART(MAX) = 700µA, IQ(MAX) = 5.5mA, IDRIVE(MAX) = 5mA, VIN HYST(MIN) = 3.75V and tSTART = 100µs, VIN, possibly exceeding the rating for the VIN pin. The zener voltage should obey VIN ON(MAX) < VZ < 25V. Programming Oscillator Frequency The oscillator frequency (fOSC) of the LT1952 is programmed using an external resistor (ROSC) connected between the ROSC pin and ground. Figure 5 shows typical fOSC vs. ROSC resistor values. The LT1952 free-running oscillator frequency is programmable in the range of 100kHz to 500kHz. Stray capacitance and potential noise pickup on the ROSC pin should be minimized by placing the ROSC resistor as close as possible to the ROSC pin and keeping the area of the ROSC node as small as possible. The ground side of the ROSC resistor should be returned directly to the (analog ground) GND pin. ROSC can be calculated by, ROSC = 9.125k [(4100k/fOSC) – 1] RSTART = (36 – 15.75)/700µA = 28.9k (choose 28.7k) 500 CSTART = (5.5mA + 5mA) • 100µs/3.75V = 0.28µF (typically choose ≥ 1µF) 450 SYSTEM INPUT (VS) 350 300 250 200 150 100 50 100 150 200 250 ROSC (kΩ) 300 350 400 1952 F05 FROM AUXILIARY WINDING RSTART FREQUENCY (kHz) For system input voltages exceeding the absolute maximum rating of the LT1952 VIN pin, an external zener should be connected from the VIN pin to ground. This covers the condition where VIN charges past VIN ON (typically 14.25V) but the part does not turn on because SD_VSEC < 1.32V. In this condition VIN will continue to charge towards system 400 VIN Figure 5. Oscillator Frequency (fOSC) vs ROSC (14.25V ON, 8.75V OFF) Programming Leading Edge Blank Time D1* – 1.32V + CSTART LT1952 *FOR VS > 25V, ZENER D1 RECOMMENDED (VIN ON(MAX) < VZ < 25V) 1952 F04 For PWM controllers driving external MOSFETs, noise can be generated at the source of the MOSFET during gate rise time and some time thereafter. This noise can potentially exceed the OC and ISENSE pin thresholds of the LT1952 to cause premature turn off of SOUT and OUT in addition to false trigger of soft-start. The LT1952 provides programmable leading edge blanking of the OC and ISENSE comparator outputs to avoid false current sensing during MOSFET switching. Figure 4. Low Power Start-Up 1952f 13 LT1952 U W U U APPLICATIO S I FOR ATIO Blanking is provided in 2 phases (Figure 6): The first phase automatically blanks during gate rise time. Gate rise times can vary depending on MOSFET type. For this reason the LT1952 performs true ‘leading edge blanking’ by automatically blanking OC and ISENSE comparator outputs until OUT rises to within 0.5V of VIN or reaches its clamp level of 13V. The second phase of blanking starts after the leading edge of OUT has been completed. This phase is programmable by the user with a resistor connected from the BLANK pin to ground. Typical durations for this portion of the blanking period are from 45ns at RBLANK = 10k to 540ns at RBLANK = 120k. Blanking duration can be approximated as: Blanking (extended) = [45(RBLANK/10k)]ns (see graph in Typical Performance Characteristics) (AUTOMATIC) LEADING EDGE BLANKING (PROGRAMMABLE) EXTENDED BLANKING CURRENT SENSE DELAY 10k < RBLANK ≤ 240k 100ns OUT RBLANK (MIN) = 10k BLANKING 0 Xns X + 45ns [X + 45(RBLANK/10k)]ns 1952 F06 Figure 6. Leading Edge Blank Timing Programming Current Limit (OC Pin) The LT1952 uses a precise 100mV sense threshold at the OC pin to detect over-current conditions in the converter and set a soft-start latch. It is independent of duty cycle because it is not affected by slope compensation programmed at the ISENSE pin. The OC pin monitors the peak current in the primary MOSFET by sensing the voltage across a sense resistor (RS) in the source of the MOSFET. The current limit for the converter can be programmed by, Current limit = (100mV/RS)(NP/NS) – (1/2)(IRIPPLE) where, RS = sense resistor in source of primary MOSFET IRIPPLE = p-p ripple current in the output inductor L1 NS = number of transformer secondary turns NP = number of transformer primary turns Programming Slope Compensation The LT1952 uses a current mode architecture to provide fast response to load transients and to ease frequency compensation requirements. Current mode switching regulators which operate with duty cycles above 50% and have continuous inductor current must add slope compensation to their current sensing loop to prevent subharmonic oscillations. (For more information on slope compensation, see Application Note 19.) The LT1952 has programmable slope compensation to allow a wide range of inductor values, to reduce susceptibility to PCB generated noise and to optimize loop bandwidth. The LT1952 programs slope compensation by inserting a resistor RSLOPE in series with the ISENSE pin (Figure 7). The LT1952 generates a current at the ISENSE pin which is linear from 0% duty cycle to the maximum duty cycle of the OUT pin. A simple calculation of I(ISENSE) • RSLOPE gives an added ramp to the voltage at the ISENSE pin for programmable slope compensation. (See both graphs ‘ISENSE Pin Current vs. Duty Cycle’ and ‘ISENSE Maximum Threshold vs Duty Cycle’ in the Typical Performance Characteristics section.) CURRENT SLOPE = 35µA • DC LT1952 OUT VS OC ISENSE 1952 F07 RSLOPE RS V(ISENSE) = VS + (ISENSE • RSLOPE) ISENSE = 8µA + 35DC µA DC = DUTY CYCLE FOR SYNC OPERATION ISENSE(SYNC) = 8µA + (k • 35DC)µA k = fOSC/fSYNC Figure 7. Programming Slope Compensation 1952f 14 LT1952 U W U U APPLICATIO S I FOR ATIO Programming Synchronous Rectifier Timing: SOUT to OUT delay (‘tDELAY’) The LT1952 has an additional output SOUT which provides a ±50mA peak drive clamped to 12V. In applications requiring synchronous rectification for high efficiency, the LT1952 SOUT provides a sync signal for secondary side control of the synchronous rectifier MOSFETs (Figure11). Timing delays through the converter can cause nonoptimum control timing for the synchronous rectifier MOSFETs. The LT1952 provides a programmable delay (tDELAY, Figure 8) between SOUT rising edge and OUT rising edge to optimize timing control for the synchronous rectifier MOSFETs to achieve maximum efficiency gains. A resistor RDELAY connected from the DELAY pin to ground sets the value of tDELAY. Typical values for tDELAY range from 10ns with RDELAY = 10k to 160ns with RDELAY = 160k. (see graph in Typical Performance Characteristics) OUT To program the volt-second clamp, the following steps should be taken: (1) The maximum operational duty cycle of the converter should be calculated for the given application. (2) An initial value for the maximum duty cycle clamp should be calculated using the equation below with a first pass guess for SS_MAXDC. Note: Since maximum operational duty cycle occurs at minimum system input voltage (UVLO), the voltage at the SD_VSEC pin = 1.32V. Max Duty Cycle Clamp (OUT pin) = k • 0.522(SS_MAXDC(DC)/SD_VSEC) – (tDELAY • fOSC) where, tDELAY SOUT SS_MAXDC pin using a resistor divider from VREF. An increase of voltage at the SS_MAXDC pin causes the maximum duty cycle clamp to increase. SS_MAXDC(DC) = VREF(RB/(RT + RB) LT1952 SD_VSEC = 1.32V at minimum system input voltage DELAY 1952 F08 RDELAY tDELAY = programmed delay between SOUT and OUT k = 1.11 – 5.5e–7 • (fOSC) Figure 8. Programming SOUT to OUT Delay: tDELAY Programming Maximum Duty Cycle Clamp For forward converter applications using the simplest topology of a single MOSFET on the primary, a maximum switch duty cycle clamp which adapts to transformer input voltage is necessary for reliable control of the MOSFET. This volt-second clamp provides a safeguard for transformer reset that prevents transformer saturation. The LT1952 SD_VSEC and SS_MAXDC pins provide a capacitor-less, programmable volt-second clamp solution using simple resistor ratios (Figure 9). An increase of voltage at the SD_VSEC pin causes the maximum duty cycle clamp to decrease. Deriving SD_VSEC from a resistor divider connected to system input voltage creates the volt-second clamp. The maximum duty cycle clamp can be adjusted by programming voltage on the (3) The maximum duty cycle clamp calculated in (2) should be programmed to be 10% greater than the maximum operational duty cycle calculated in (1). Simple adjustment of maximum duty cycle can be achieved by adjusting SS_MAXDC. SYSTEM INPUT VOLTAGE R1 LT1952 ADAPTIVE DUTY CYCLE CLAMP INPUT SD_VSEC R2 SS_MAXDC RT * VREF RB 1952 F09 MAX DUTY CYCLE CLAMP ADJUST INPUT *MINIMUM ALLOWABLE RT IS 10k TO GUARANTEE SOFT-START PULL-OFF Figure 9. Programming Maximum Duty Cycle Clamp 1952f 15 LT1952 U W U U APPLICATIO S I FOR ATIO Example calculation for (2) For RT = 35.7k, RB = 100k, VREF = 2.5V, RDELAY = 40k, fOSC = 200kHz and SD_VSEC = 1.32V, this gives SS_MAXDC(DC) = 1.84V, tDELAY = 40ns and k = 1 Maximum Duty Cycle Clamp = 1 • 0.522(1.84/1.32) – (40ns • 200kHz) = 0.728 – 0.008 = 0.72 (Duty Cycle Clamp = 72%) Note 1: To achieve the same maximum duty cycle clamp at 100kHz as calculated for 200kHz, the SS_MAXDC voltage should be reprogrammed by, SS_MAXDC(DC) (100kHz) = SS_MAXDC(DC) (200kHz) • k (200kHz)/k (100kHz) = 1.84 • 1.0/1.055 = 1.74V (k = 1.055 for 100kHz) The second order effect of tDELAY should also be considered for final adjustment of SS_MAXDC(DC). Note 2 : To achieve the same maximum duty cycle clamp while synchronizing to an external clock at the SYNC pin, the SS_MAXDC voltage should be re-programmed as, SS_MAXDC (DC) (fsync) = SS_MAXDC (DC) (200kHz) • [(fosc/fsync) + 0.09(fosc/200kHz)0.6] A capacitor CSS on the SS_MAXDC pin and the resistor divider from VREF used to program maximum switch duty cycle clamp, determine soft-start timing (Figure 11). A soft-start event is triggered for the following faults: (1) VIN < 8.75V, or (2) SD_VSEC < 1.32V (UVLO), or (3) OC > 100mV (over-current condition) When a soft-start event is triggered, switching at SOUT and OUT is stopped immediately. A soft-start latch is set and SS_MAXDC pin is discharged. The SS_MAXDC pin can only recharge when the soft-start latch has been reset. Note: A soft-start event caused by (1) or (2) above, also causes VREF to be disabled and to fall to ground. SS_MAXDC SOFT-START EVENT TRIGGERED 0.8V (ACTIVE THRESHOLD) 0.45V (RESET THRESHOLD) TIMING (A): SOFT START FAULT REMOVED BEFORE SS_MAXDC FALLS TO 0.45V SS_MAXDC For SS_MAXDC (DC) (200kHz) = 1.84V for 72% duty cycle 0.8V (ACTIVE THRESHOLD) 0.45V (RESET THRESHOLD) 0.2V SS_MAXDC (DC) (fsync = 250kHz) for 72% duty cycle = 1.84 • [(200kHz/250kHz) + 0.09(1)0.6] = 1.638V TIMING (B): SOFT-START FAULT REMOVED AFTER SS_MAXDC FALLS PAST 0.45V 1952 F10 Figure 10. Soft-Start Timing SS_MAXDC(DC) Programming Soft-Start Timing The LT1952 has built-in soft-start capability to provide low stress controlled startup from a list of fault conditions that can occur in the application (see Figure 1 and Figure 10). The LT1952 provides true PWM soft-start by using the SS_MAXDC pin to control soft-start timing. The proportional relationship between SS_MAXDC voltage and switch maximum duty cycle clamp allows the SS_MAXDC pin to slowly ramp output voltage by ramping the maximum switch duty cycle clamp — until switch duty cycle clamp seamlessly meets the natural duty cycle of the converter. LT1952 LT1952 RCHARGE SS_MAXDC SS_MAXDC RT VREF CSS CSS RB 1952 F11 SS_MAXDC CHARGING MODEL SS_MAXDC(DC) = VREF [RB/(RT + RB)] RCHARGE = [RT • RB/(RT + RB)] Figure 11. Programming Soft-Start Timing 1952f 16 LT1952 U W U U APPLICATIO S I FOR ATIO Soft-start latch reset requires all of the following: (A) VIN > 14.25*, and (B) SD_VSEC > 1.32V, and (C) OC < 100mV, and (D) SS_MAXDC < 0.45V (SS_MAXDC reset threshold) *VIN > 8.75V is ok for latch reset if the latch was only set by over-current condition in (3) above SS_MAXDC Discharge Timing It can be seen in Figure 10 that two types of discharge can occur for the SS_MAXDC pin. In timing (A) the fault that caused the soft-start event has been removed before SS_MAXDC falls to 0.45V. This means the soft-start latch will be reset when SS_MAXDC falls to 0.45V and SS_MAXDC will begin charging. In timing (B), the fault that caused the soft-start event is not removed until some time after SS_MAXDC has fallen past 0.45V. The SS_MAXDC pin continues to discharge to 0.2V and remains low until all faults are removed. The time for SS_MAXDC to fall to a given voltage can be approximated as, SS_MAXDC (tFALL) = (CSS/IDIS) • [SS_MAXDC(DC) – VSS(MIN)] where, IDIS = net discharge current on CSS CSS = capacitor value at SS_MAXDC pin SS_MAXDC(DC) = programmed DC voltage VSS(MIN) = minimum SS_MAXDC voltage before recharge IDIS ~ 8e–4 + (VREF – VSS(MIN))[(1/2RB) – (1/RT)] For faults arising from (1) and (2), VREF = 100mV. For a fault arising from (3), VREF = 2.5V. SS_MAXDC(DC) = VREF[RB/(RT + RB)] VSS(MIN) = SS_MAXDC reset threshold = 0.45V (if fault removed before tFALL) Example For an over-current fault (OC > 100mV), VREF = 2.5V, RT = 35.7k, RB = 100k, CSS = 0.1µF and assume VSS(MIN) = 0.45V, IDIS ~ 8e–4 + (2.5 – 0.45)[(1/2 • 100k) – (1/35.7k)] = 8e–4 + (2.05)(–0.23e–4) = 7.5e–4 SS_MAXDC(DC) = 1.84V SS_MAXDC (tFALL) = (1e – 7/7.5e–4) • (1.84 – 0.45) = 1.85e–4 s If the OC fault is not removed before 185µs then SS_MAXDC will continue to fall past 0.45V towards a new VSS(MIN). The typical VOL for SS_MAXDC at 150µA is 0.2V. SS_MAXDC Charge Timing When all faults are removed and the SS_MAXDC pin has fallen to its reset threshold of 0.45V or lower, the SS_MAXDC pin will be released and allowed to charge. SS_MAXDC will rise until it settles at its programmed DC voltage — setting the maximum switch duty cycle clamp. The calculation of charging time for the SS_MAXDC pin between any two voltage levels can be approximated as an RC charging waveform using the model shown in Figure 11. The ability to predict SS_MAXDC rise time between any two voltages allows prediction of several key timing periods: (1) No Switching Period (time from SS_MAXDC(DC) to VSS(MIN) + time from VSS(MIN) to VSS(ACTIVE)) (2) Converter Output Rise Time (time from VSS(ACTIVE) to VSS(REG); VSS(REG) is the level of SS_MAXDC where maximum duty cycle clamp equals the natural duty cycle of the switch) (3) Time For Maximum Duty Cycle Clamp within X% of Target Value The time for SS_MAXDC to charge to a given voltage VSS is found by re-arranging, VSS(t) = SS_MAXDC(DC) (1 – e(–t/RC)) 1952f 17 LT1952 U W U U APPLICATIO S I FOR ATIO to give, t = RC • (–1) • ln(1 – VSS/SS_MAXDC(DC)) where, VSS = SS_MAXDC voltage at time t SS_MAXDC(DC) = programmed DC voltage setting maximum duty cycle clamp = VREF(RB/(RT + RB) R = RCHARGE (Figure 11) = RT • RB/(RT + RB) C = CSS (Figure 11) Example (1) No Switching Period The period of no switching for the converter, when a soft-start event has occurred, depends on how far SS_MAXDC can fall before recharging occurs and how long a fault exists. It will be assumed that a fault triggering soft-start is removed before SS_MAXDC can reach its reset threshold (0.45V). No Switching Period = tDISCHARGE + tCHARGE tDISCHARGE = discharge time from SS_MAXDC(DC) to 0.45V tCHARGE = charge time from 0.45V to VSS(ACTIVE) tDISCHARGE was already calculated earlier as 185µs. tCHARGE is calculated by assuming the following: VREF = 2.5V, RT = 35.7k, RB = 100k, CSS = 0.1µF and VSS(MIN) = 0.45V. tCHARGE = t(VSS = 0.8V) – t(VSS = 0.45V) Step 1: Step 3: t(VSS = 0.8V) is calculated from, t = RCHARGE • CSS • (–1) • ln(1 – VSS/SS_MAXDC(DC)) = 2.63e4 • 1e–7 • (–1) • ln(1 – 0.8/1.84) = 2.63e–3 • (–1) • ln(0.565) = 1.5e–3 s From Step 1 and Step 2 tCHARGE = (1.5 – 0.73)e–3 s = 7.7e–4 s The total time of no switching for the converter due to a soft-start event = tDISCHARGE + tCHARGE = 1.85e–4 + 7.7e–4 = 9.55e–4 s Example (2) Converter Output Rise Time The rise time for the converter output to reach regulation can be closely approximated as the time between the start of switching (SS_MAXDC = VSS(ACTIVE)) and the time where converter duty cycle is in regulation (DC(REG)) and no longer controlled by SS_MAXDC (SS_MAXDC = VSS(REG)). Converter output rise time can be expressed as, Output Rise Time = t(VSS(REG)) – t(VSS(ACTIVE)) Step 1: Determine converter duty cycle DC(REG) for output in regulation The natural duty cycle DC(REG) of the converter depends on several factors. For this example it is assumed that DC(REG) = 60% for system input voltage near the undervoltage lockout threshold (UVLO). This gives SD_VSEC = 1.32V. Also assume that the maximum duty cycle clamp programmed for this condition is 72% for SS_MAXDC(DC) = 1.84V, fOSC = 200kHz and RDELAY = 40k. SS_MAXDC(DC) = 2.5[100k/(35.7k + 100k)] = 1.84V Step 2: Calculate VSS(REG) RCHARGE = (35.7k • 100k/135.7k) = 26.3k To calculate the level of SS_MAXDC (VSS(REG)) that no longer clamps the natural duty cycle of the converter, the equation for maximum duty cycle clamp must be used (see previous section ‘Programming Maximum Duty Cycle Clamp’). Step 2: t(VSS = 0.45V) is calculated from, t = RCHARGE • CSS • (–1) • ln(1 – VSS/SS_MAXDC(DC)) = 2.63e4 • 1e–7 • (–1) • ln(1 – 0.45/1.84) = 2.63e–3 • (–1) • ln(0.755) = 7.3e–4 s The point where the maximum duty cycle clamp meets DC(REG) during soft-start is given by, DC(REG) = Max Duty Cycle clamp 1952f 18 LT1952 U W U U APPLICATIO S I FOR ATIO 0.6 = k • 0.522(SS_MAXDC(DC)/SD_VSEC) – (tDELAY • fOSC) For SD_VSEC = 1.32V, fOSC = 200kHz and RDELAY = 40k This gives k = 1 and tDELAY = 40ns. Re-arranging the above equation to solve for SS_MAXDC = VSS(REG) = [0.6 + (tDELAY • fOSC)(SD_VSEC)]/(k • 0.522) = [0.6 + (40ns • 200kHz)(1.32V)]/(1 • 0.522) = (0.608)(1.32)/0.522 = 1.537V From previous calculations, t(0.45) = 7.3e – 4 s. Using previous values for RT, RB, and CSS, t(1.803) = 2.63e–4 • 1e–7 • (–1) • ln(1 – 1.803/1.84) = 2.63e–3 • (–1) • ln(0.02) = 1.03e–2 s Hence the time for SS_MAXDC to charge from its minimum reset threshold of 0.45V to within 2% of its target value is given by, t(1.803) – t(0.45) = 1.03e–2 – 7.3e–4 = 9.57e–3 Step 3: Calculate t(VSS(REG)) – t(VSS(ACTIVE)) Forward Converter Applications Recall the time for SS_MAXDC to charge to a given voltage VSS is given by, The following section covers applications where the LT1952 is used in conjunction with other LTC parts to provide highly efficient power converters using the single switch forward converter topology. t = RCHARGE • CSS • (–1) • ln(1 – VSS/SS_MAXDC(DC)) (Figure 11 gives the model for SS_MAXDC charging) For RT = 35.7k, RB = 100k, RCHARGE = 26.3k 95% Efficient, 5V, Synchronous Forward Converter For CSS = 0.1µF, this gives t(VSS(ACTIVE)) = t(VSS(0.8V)) = 2.63e4 • 1e–7 • (–1) • ln(1 – 0.8/1.84) = 2.63e–3 • (–1) • ln(0.565) = 1.5e–3 s The circuit in Figure 14 is based on the LT1952 to provide the simplest forward power converter circuit — using only one primary MOSFET. The SOUT pin of the LT1952 provides a synchronous control signal for the LTC1698 located on the secondary. The LTC1698 drives secondary side synchronous rectifier MOSFETs to achieve high efficiency. The LTC1698 also serves as an error amplifier and optocoupler driver. t(VSS(REG)) = t(VSS(1.537V)) = 26.3k • 0.1µF • –1 • ln(1 – 1.66/1.84) = 2.63e–3 • (–1) • ln(0.146) = 5e–3 s The rise time for the converter output = t(VSS(REG)) – t(VSS(ACTIVE)) = (5 – 1.5)e–3 s = 3.5e–3 s Example (3) Time For Maximum Duty Cycle Clamp to Reach Within X% of Target Value A maximum duty cycle clamp of 72% was calculated previously in the section ‘Programming Maximum Duty Cycle Clamp’. The programmed value used for SS_MAXDC(DC) was 1.84V. The time for SS_MAXDC to charge from its minimum value VSS(MIN) to within X% of SS_MAXDC(DC) is given by, t(SS_MAXDC charge time within X% of target) = t[(1 – (X/100) • SS_MAXDC(DC)] – t(VSS(MIN)) For X = 2 and VSS(MIN) = 0.45V, t(0.98 • 1.84) – t(0.45) = t(1.803) – t(0.45) Efficiency and transient response are shown in Figures 12 and 13. Peak efficiencies of 95% and ultra-fast transient response are superior to presently available power modules. Integrated soft-start, over-current detection and short circuit hiccup mode provide low stress, reliable protection. In addition, the circuit in Figure 14 is an allceramic capacitor solution providing low output ripple voltage and improved reliability. The LT1952-based converter can be used to replace power module converters at a much lower cost. The LT1952 solution benefits from thermal conduction of the system board resulting in higher efficiencies and lower rise in component temperatures. The 7mm height allows dense packaging and the circuit can easily be adjusted to provide an output voltage from 1.23V to 26V. Higher currents are achievable by simple scaling of power components. The LT1952-based solution in Figure 14 is a powerful topology for replacement of a wide range of power modules. 1952f 19 LT1952 U U W U APPLICATIO S I FOR ATIO 98 EFFICIENCY (%) 96 94 IOUT (5A/DIV) 92 0A 90 VOUT (200mV/DIV) 88 VIN = 48V VOUT = 5V fOSC = 300kHz 86 5 0 15 10 LOAD CURRENT (A) 20 25 1952 F13 20µs/DIV 1952 F12 Figure 12. LT1952-Based Synchronous Forward Converter Efficiency vs Load Current (For Circuit in Figure 14) Figure 13. Output Voltage Transient Response (6A to 12A Load Step at 6A/µs) +VIN 36V TO 72V CIN 2.2µF 100V X5R 40k SOUT 16 5 100k 2 FB LT1952 1k 0.015Ω 8 GND 15 3 115k Q1 13 PGND ROSC 7VBIAS BAS516 10VBIAS VIN 4 1 18.2k BLANK DELAY 1 COMP 9 12 40k 33k T2 4.75k 0.1µF 560Ω C9, 6.8nF R14 1.2k HCPL-M453 10VBIAS Q1: PHM15NQ20 PHILIPS 220pF 3 R13 270Ω SYNC SOUT 1µF 2 1µF X5R 9.53k SYNC C01 100µF X5R 2× Q3 PH3830 10 ISENSE 0.1µF Q2 PH3830 11 OC VREF 475k 14 OUT 22k 6 0.1µF SS_MAXDC +V0UT 5V 20A 7 SD_VSEC SOUT L1 PA1393.152 T1 PA0491 6 1 5 2 4 3 4 5 6 8 LTC1698 VDD CG FG SYNC PGND VAUX GND ICOMP OPTO +ISNS VCOMP –ISNS VFB OVP 16 15 SYNC 14 0.1µF 13 12 11 9 +V0UT R15 38.3k R16 12.4k 1952 F14 Figure 14. 36V to 72V Input to 5V at 20A Synchronous Forward Converter 1952f 20 LT1952 U U W U APPLICATIO S I FOR ATIO 48V to Isolated 12V, 20A (No Opto-Coupler) ‘Bus Converter’ The solution is only slightly larger than 1/4 “brick” size and uses only ceramic capacitors for high reliability. The wide programmable range and accuracy of the LT1952 Volt-Second clamp makes the LT1952 an ideal choice for ‘Bus Converter’ applications where the Volt-Second clamp provides line regulation for the converter output. The 48V to 12V 20A ‘Bus Converter’ application in Figure16 shows a semi-regulated isolated output without the need for an optocoupler, optocoupler driver, reference or feedback network. Some ‘Bus Converter’ solutions run with a fixed 50% duty cycle resulting in an output variation of 2-to-1 for applications with a 72V to 36V input range. The LT1952 uses an accurate wide programmable range Volt-Second clamp to initially program and then control power supply output voltage to typically ±10% for the same 36V to 72V input range. Efficiency for the LT1952-based bus converter in Figure 16 achieves a high 94% at 20A (Figure 15). EFFICIENCY (%) 95.5 95.0 94.5 94.0 93.5 VIN = 48V VOUT = 12V 93.0 4 6 8 10 12 14 16 LOAD CURRENT (A) 20 1952 F15 Figure 15. LT1952-Based Synchronous ‘Bus Converter’ Efficiency vs Load Current (For Circuit in Figure 16) T1 PA0815.002 VU1 2.4µH • • 82k 18 • VIN 36V TO 72V 47k 12V Bus Converter Efficiency 96.0 VOUT 12V, 20A BAS516 BCX55 0.1µF 18V 2.2µF, 100V 2x 115k 3 27k 0.47µF 9 5 59k 10k SD_VSEC OUT ROSC VIN BLANK GND SS_MAXDC LT1952 0.1µF 6 1 2 5 VREF COMP FB PGND DELAY OC ISENSE SOUT 14 VU1 6 1µF 4 15 8 8V BIAS 1µF 13 12 8 BAT760 FG 16 3 CS+ 1 10k GND CS– 2 10k VCC SYNC TIMER 39k 9mΩ 1nF 7 470Ω 560Ω 220pF T2 Q4470-B CT 1nF 8V BIAS 11 10 CG RT 15k • • 7 10k COUT 33µF, 16V X5R, TDK 3x LTC3900 • PH21NQ15 2x 370k 13.2k PH4840 2x Si7370 2x 12V L1: PA1494.242 PULSE ENGINEERING T1: PULSE ENGINEERING T2: COILCRAFT 1952 F16 Figure 16. 36V to 72V Input to 12V at 20A No ‘Optocoupler’ Synchronous ‘Bus Converter’ 1952f 21 LT1952 U U W U APPLICATIO S I FOR ATIO 36V to 72V Input, 3.3V 40A Converter controlled hiccup mode. This allows a significant reduction in power component sizing using the LT1952-based converter. An LT1952-based synchronous forward converter provides the ideal solution for power supplies requiring high efficiency at low output voltages and high load currents. The 3.3V 40A solution in Figure 18 achieves peak efficiencies of 92.5% (Figure 17) by minimizing power loss due to rectification at the output. Synchronous rectifier control output SOUT, with programmable delay, optimizes timing control for a secondary side synchronous MOSFET controller (LTC3900) which results in high efficiency synchronous rectification. The LT1952 uses a precision current limit threshold at the OC pin combined with a soft-start hiccup mode to provide low stress output short circuit protection. The maximum output current will vary only 10% over the full VIN range. During short circuit the average power dissipation of the circuit will be lower than 15% of maximum rated power thanks to a soft-start 93 EFFICIENCY (%) 92 91 90 89 88 VIN = 48V VOUT = 3.3V fOSC = 300kHz 87 86 0 20 40 30 OUTPUT CURRENT (A) 10 1952 F17 Figure 17. LT1952-Based Synchronous Forward Converter Efficiency vs Load Current (For Circuit in Figure 18) VU1 L1 PA0912.002 • • 82k BCX55 50 • +VIN 36V TO 72V 47k 94 VOUT 3.3V, 40A BAS516 0.1µF 18V Q2 PH3230 2x 12V Q3 PH3230 2x COUT 100µF 3x 10k 2.2µF LTC3900 • 5 370k 7 115k 3 27k 0.22µF 9 5 59k 10k SD_VSEC OUT ROSC VIN BLANK GND SS_MAXDC PGND LT1952 6 0.1µF 33k 1 2 2.2k VR = 2.5V COMP FB = 1.23V DELAY OC ISENSE SOUT 14 VU1 1µF Si7846 4 15 8 8V BIAS 1µF 13 12 8 BAT760 FG CG 10k 2 10k GND CS VCC CS– SYNC TIMER 1nF 15k 10mΩ 1nF 8V BIAS 470Ω 560Ω 220pF 249k 16 T2 Q4470-B 22k 7 39k 11 10 3 + 1 80.6k • • 13.2k 6 2.2nF 8V BIAS 18k VU1 PS8101 270Ω 2 – LT1797 5 + 1 L1: PA0713, PULSE ENGINEERING ALL CAPACITORS X7R, CERAMIC, TDK T2: COILCRAFT 4 3 10k 10k 1µF 8 0.1µF 4 LT1009 1952 F18 Figure 18. 36V to 72V, 3.3V at 40A Synchronous Forward Converter 1952f 22 LT1952 U U W U APPLICATIO S I FOR ATIO Bus Converter: Optimum Output Voltage Tolerance The Bus Converter applications shown on page 1 and in Figure 16, provide semi-regulated isolated outputs without the need for an optocoupler, optocoupler driver, reference or feedback network. The LT1952 Volt-Second clamp adjusts switch duty cycle inversely proportional to input voltage to provide an output voltage that is regulated against input line variations. Some bus converters use a switch duty cycle limit which causes output voltage variation of typically ±33% over a 2:1 input voltage range. The LT1952 typically provides a ±10% output variation for the same input variation. Typical output tolerance is further improved for the LT1952 by inserting a resistor from the system input voltage to the SS_MAXDC pin (Rx in Figure 19). The LT1952 electrical specifications for the OUT Max Duty Cycle Clamp show typical switch duty cycle to move from 72% to 33% for a 2x change of input voltage (SS_MAXDC pin = 1.84V). Since output voltage regulation follows VIN • Duty Cycle, a switch duty cycle change of 72% to 36% (for a 2x input voltage change) provides minimal output voltage variation for the LT1952 bus converter. To achieve this, an SS_MAXDC pin voltage increase of 1.09x (36/33) would be required at high input line. A resistor Rx inserted between the SS_MAXDC pin and system input voltage (Figure 19) increases SS_MAXDC voltage as input voltage increases, minimizing output voltage variation over a 2:1 input voltage change. The following steps determine values for Rx, RT and RB (1) Program switch duty cycle at minimum system input voltage (VS(MIN)) (a) RT(1) = 10k (minimum allowed to still guarantee softstart pull-down) VOLT-SECOND CLAMP ADJUST INPUT (2) Calculate Rx Rx = ([VS(MAX) – VS(MIN)]/[SS1 • (X – 1)]) • RTHEV(1) RTHEV(1) = RB(1) • RT(1)/(RB(1) + RT(1)), X = ideal duty cycle (VS(MAX))/actual duty cycle (VS(MAX)) (3) The addition of Rx causes an increase in the original programmed SS_MAXDC voltage SS1. A new value for RB(1) should be calculated to provide a lower SS_MAXDC voltage (SS2) to correct for this offset. (a) SS2 = SS1 – [(VS(MIN) – SS1) • RTHEV(1)/Rx] (b) RB(2) = [SS2/(2.5 – SS2)] • RT(1) (4) The thevinin resistance RTHEV(1) used to calculate Rx should be re-established for RT and RB. (a) RB (final value) = RB(2) • (RTHEV(1)/RTHEV(2)) (b) RT (final value) = RT(1) • (RTHEV(1)/RTHEV(2)) where RTHEV(2) = RB(2) • RT(1)/(RB(2) + RT(1)) Example: For a Bus Converter running from 36V to 72V input, VS(MIN) = 36V, VS(MAX) = 72V. choose RT(1) = 10k, SS_MAXDC = SS1 = 1.84V (for 72% duty cycle at VS(MIN) = 36V) RB(1) = [1.84V/(2.5V – 1.84V)] • 10k = 28k RTHEV(1) = [28k • 10k/(28k + 10k)] = 7.4k Rx = [(72V – 36V)/(1.84 • 0.09)] • 7.4k = 1.6M Rx VOLT-SECOND CLAMP INPUT SS2 = 1.84 – [(36V – 1.84) • 7.4k/1.6M] = 1.682V LT1952 SD_VSEC R2 (c) Calculate RB(1) = [SS1/(2.5 – SS1)] • RT(1) SS_MAXDC correction = 36%/33% = 1.09 SYSTEM INPUT VOLTAGE R1 (b) Select switch duty cycle for the Bus Converter for a given output voltage at V S(MIN) and calculate SS_MAXDC voltage (SS1) (See Applications Information “Programming Maximum Duty Cycle Clamp”) RB(2) = [1.682/(2.5 – 1.682)] • 10k = 20.6k SS_MAXDC RT RTHEV(2) = [20.6k • 10k/(20.6k + 10k)] = 6.7k VREF RB 1952 F19 RTHEV(1)/RTHEV(2) = 7.4k/6.7k = 1.104 RB (final value) = 20.6k • 1.104 = 22.7k (choose 22.6k) Figure 19. Optimal Programming of Maximum Duty Cycle Clamp for Bus Converter Applications (Adding Rx) RT (final value) = 10k • 1.104 = 11k 1952f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LT1952 U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) 2 3 4 5 6 7 .0532 – .0688 (1.35 – 1.75) 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) .008 – .012 (0.203 – 0.305) TYP NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .0250 (0.635) BSC GN16 (SSOP) 0204 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1681/LT3781 Synchronous Forward Controllers High Efficiency 2-Switch Forward Control LT1698 Secondary Synchronous Rectifier Controller Use for Isolated Power Supplies, Contains Voltage Margining, Optocoupler Driver, Synchronization Circuit with the Primary Side, Error Amplifier LT1725 General Purpose Isolated Flyback Controller Drives External Power MOSFET, Senses Output Voltage Directly from Primary Side Switching — No Optoisolator Required, 16-pin SSOP LT1950 Single Switch Forward Controller 3V ≤ VIN ≤ 25V, 25W to 500W, Adaptive Max Duty Cycle Clamp, Programmable Slope Compensation, Low 100mV Sense Threshold, 16-Pin SSOP LTC3722-1/LTC3722-2 Dual Mode Phase Modulated Full-Bridge Controllers ZVS Full-Bridge Controllers LTC3723-1/LTC3723-2 Synchronous Push-Pull PWM Controllers High Efficiency Push-Pull PWM LTC3803 SOT-23 Flyback Controller Adjustable Slope Compensation, Internal Soft-Start, 200kHz LTC3806 Synchronous Flyback Controller Excellent Cross Regulation, High Efficiency, Multiple Outputs LTC3900 Synchronous Rectifier Driver for Forward Converters Use for Isolated Power Supplies, 4.5V ≤ VIN ≤ 11V, N-channel Synchronous MOSFET Driver, Programmable Timeout, Reverse Inductor Current Sense, 16-pin SSOP 1952f 24 Linear Technology Corporation LT/TP 0804 1K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004