NX5P1100
Logic controlled high-side power switch
Rev. 1 — 21 March 2014
Product data sheet
1. General description
The NX5P1100 is an advanced power switch and ESD-protection device for USB OTG
applications. It includes under voltage and over voltage lockout, over-current,
over-temperature, reverse bias and in-rush current protection circuits. These circuits are
designed to isolate a VBUS OTG voltage source from a VBUS interface pin automatically
when a fault condition occurs. The device features two power switch terminals, one input
(VINT) and one output (VBUS). It has a current limit input (ILIM) for defining the
over-current and in-rush current limit. A voltage detect output (VDET) is used to determine
when VINT is in the correct voltage range. An open-drain fault output (FAULT) indicates
when a fault condition has occurred, and an enable input (EN) controls the state of the
switch. When EN is set LOW the device enters a low-power mode, disabling all protection
circuits except the undervoltage lockout. The low-power mode can be entered at anytime
unless the over temperature protection circuit has been triggered.
Designed for operation from 3 V to 5.5 V, it is used in power domain isolation applications
to protect from out of range operation. The enable input includes integrated logic level
translation making the device compatible with lower voltage processors and controllers.
2. Features and benefits
Wide supply voltage range from 3 V to 5.5 V
30 V tolerant on VBUS
ISW maximum 1 A continuous current
Very low ON resistance: 100 m (maximum) at a supply voltage of 4.0 V
Low-power mode (ground current 20 A typical)
1.8 V control logic
Soft start turn-on slew rate
Protection circuitry
Over-temperature protection
Over-current protection with low current output mode
Reverse bias current/Back drive protection
Overvoltage lockout
Undervoltage lockout
Analog voltage limited VBUS monitor path
ESD protection:
HBM ANSI/ESDA/JEDEC JDS-001 Class 2 exceeds 2 kV
CDM AEC standard Q100-011 category C6 exceeds 1 kV
IEC61000-4-2 contact discharge exceeds 8 kV for pins VBUS, D, D+ and ID
Specified from 40 C to +85 C
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
3. Applications
USB OTG applications
4. Ordering information
Table 1.
Ordering information
Type number Package
Temperature range Name
NX5P1100UK 40 C to +85 C
Description
Version
WLCSP12 wafer level chip-scale package; 12 bumps;
1.36 x 1.66 x 0.51 mm, 0.4 mm pitch (Backside coating
included)
NX5P1100
5. Marking
Table 2.
Marking codes
Type number
Marking code
NX5P1100UK
NX5PB
6. Functional diagram
(1
9%86
9,17
'
9'(7
'
,/,0
,'
)$8/7
DDD
Fig 1.
Logic symbol
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
P$
&855(176285&(
5(9(56(&855(17
3527(&7,21
,/,0
29(5&855(17
3527(&7,21
9,17
9%86
89/229/2
3527
9'(7
&21752/
'
'
,'
(1
)$8/7
&
3527
DDD
Fig 2.
Logic diagram (simplified schematic)
7. Pinning information
7.1 Pinning
1;3
EDOO$
LQGH[DUHD
1;3
$
$
9,17
9'(7
9%86
%
%
9,17
)$8/7
9%86
&
&
(1
*1'
,'
'
'
,/,0
'
'
DDD
DDD
7UDQVSDUHQWWRSYLHZ
Fig 3.
Pin configuration WLCSP12 package
7UDQVSDUHQWWRSYLHZ
Fig 4.
Ball mapping for WLCSP12
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
VINT
A1, B1
internal circuitry voltage I
VBUS
A3, B3
external connector voltage O
EN
C1
enable input (active HIGH) I
ILIM
D1
current limiter I/O
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
Table 3.
Pin description …continued
Symbol
Pin
Description
VDET
A2
VBUS voltage level indicator O
FAULT
B2
fault condition indicator (open-drain; active LOW)
GND
C2
ground (0 V)
D-
D2
ESD-protection I/O
D+
D3
ESD-protection I/O
ID
C3
ESD-protection I/O
8. Functional description
Table 4.
Function table[1]
EN
VINT
VBUS
FAULT Operation mode
X
0V
Z
L
no supply
X
0V
< 30 V
Z
disabled; switch open
X
< 3.2 V
Z
L
undervoltage lockout; switch open
H
> 5.5 V
Z
L
overvoltage lockout; switch open
H
3.2 V to 5.5 V
Z
L
over-temperature; switch open
L
3.2 V to 5.5 V
Z
Z
disabled; switch open
H
3.2 V to 5.5 V
VBUS = VINT
Z
enabled; switch closed; active
H
3.2 V to 5.5 V
0 V to VINT
L
over-current; switch open; constant current on VBUS
H
3.2 V to 5.5 V
0 V to VINT
L
when ILIM is connected to GND, VBUS is supplied with
10 mA current source
H
3.2 V to 5.5 V
VINT + 30 mV < VBUS < VINT +
0.45 V (> 4 ms)
L
reverse bias current/back drive; switch open
H
3.2 V to 5.5 V
VBUS > VINT + 0.45 V
L
reverse bias current/back drive; switch open
[1]
H = HIGH voltage level; L = LOW voltage level, Z = high-impedance OFF-state, X = Don’t care.
Table 5.
Function table VDET versus VBUS
VBUS
VDET
3 V < VBUS < 30 V
1.5 < VDET < 5.5 V VDET detects VBUS voltage; See Figure 22.
Operation mode
8.1 EN input
A LOW on EN disables the N-channel MOSFET and the device enters low-power mode.
In low-power mode, all protection circuits are disabled except for the undervoltage lockout
circuit. A HIGH on EN, enables the protection circuits and then enables the N-channel
MOSFET.
8.2 FAULT output
The FAULT output is an open-drain output that requires an external pull-up resistor. If any
of the UVLO, OVLO, RCP, OCP or OTP circuits are activated the FAULT output is set
LOW. A LOW indicates that a fault has occurred. The FAULT output returns to the high
impedance state automatically once the fault condition is removed.
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
8.3 VDET output
VDET is an analog output that allows a controller to monitor the voltage level on VBUS.
8.4 Undervoltage lockout (UVLO)
When VINT < 3.2 V, the UVLO circuit is triggered. It disables the N-channel MOSFET sets
the FAULT output LOW and the device enters low-power mode. Once VINT > 3.2 V, the
EN pin controls the state of the N-channel MOSFET. The UVLO circuit remains active in
low-power mode.
8.5 Overvoltage lockout (OVLO)
When EN is HIGH and VINT > 5.75 V, the OVLO circuit is triggered. It disables the
N-channel MOSFET and sets the FAULT output LOW. The OVLO circuit is disabled in
low-power mode and does not influence the FAULT output state. If the OVLO circuit is
triggered, setting the EN pin LOW returns the device to low-power mode.
8.6 Over-current protection (OCP)
If either of these two conditions occur for longer than 8 ms, the OCP circuit is triggered.
1. Current through the N-channel MOSFET exceeds Itrig.
2. VBUS < VINT 200 mV.
During the 8 ms trigger delay, the maximum current is clamped at Iocp. The OCP disables
the N-channel MOSFET; supplies VBUS from the 10 mA current source (IO), and sets
FAULT LOW. When VINT > VBUS > VINT - 200 mV for 20 s, the OCP circuit is disabled.
EN controls the state of the N-channel MOSFET, the 10 mA current source is
disconnected and FAULT is set high impedance. If the OCP circuit is active, setting the
EN pin LOW returns the device to low-power mode. (see Figure 23, Figure 24, Figure 25,
Figure 26)
8.7 ILIM
The OCP trigger value Itrig, is set using an external resistor RILIM connected to the ILIM pin
(see Figure 6). When EN is HIGH and ILIM is grounded, VBUS is supplied by the 10 mA
current source and FAULT is set LOW.
8.8 Over-temperature protection (OTP)
When EN is HIGH, if the device temperature exceeds 125 C, the OTP circuit is triggered.
It disables the N-channel MOSFET and sets FAULT LOW. Any transition on EN has no
effect. Once the device temperature decreases to below 115 C the device returns to the
defined state. The OTP circuit is disabled in low-power mode. If the OTP circuit is active,
setting the EN pin LOW does not return the device to low-power mode.
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
8.9 Reverse bias current/back drive protection
If either of these two conditions occur, the RCP circuit is triggered.
1. (VINT + 30 mV) < VBUS < (VINT + 0.45 V) for longer than 4 ms.
2. VBUS > (VINT + 0.45 V)
It disables the N-channel MOSFET and sets FAULT LOW. Once VBUS < VINT for longer
than 4 ms the device returns to the defined state. If the RCP circuit is active, setting the
EN pin LOW returns the device to low-power mode.
8.10 In-rush current protection
The N-channel MOSFET can be enabled via the EN pin or via a recovering fault condition.
When enabled, the in-rush current protection circuit limits the current while VBUS
increases to VINT 200 mV. The resistor connected to ILIM determines the current limit.
The in-rush current protection circuit is disabled in low-power mode.
9. Application diagram
The NX5P1100 typically connects a voltage source on VINT to the VBUS of a USB
connector supporting USB3 OTG in a portable, battery operated device. The external
resistor RILIM sets the maximum current limit threshold. The FAULT signal requires an
external pull-up resistor.
P$
&855(176285&(
5(9(56(&855(17
3527(&7,21
29(5&855(17
3527(&7,21
,/,0
9,17
9%86
89/229/2
3527
&
Q)
5SX
9'(7
'
'
,'
&21752/
(1
&
)
86%27*9%86
92/7$*(
6285&(
$1'
&21752/
)$8/7
&
3527
5,/,0
*1'
DDD
Fig 5.
NX5P1100 application diagram
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
6 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
10. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
input voltage
VI
Conditions
Min
Max
Unit
VBUS
[1]
0.5
+32
V
VINT
[1]
0.5
+6.0
V
EN, ILIM
[2]
0.5
VINT + 0.5
V
D-, D+, ID
[1]
0.5
+6.0
V
VO
output voltage
FAULT
0.5
+6.0
V
IIK
input clamping current
EN: VI < 0.5 V
50
-
mA
ISK
switch clamping current
VBUS; VINT; VI < 0.5 V
50
-
mA
ISW
switch current
-
1000
mA
Tj(max)
maximum junction
temperature
40
+125
C
Tstg
storage temperature
65
+150
C
-
100
mW
Tamb = 85 °C
[3]
total power dissipation
Ptot
[1]
The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[2]
The minimum input voltage rating may be exceeded if the input current rating is observed.
[3]
The (absolute) maximum power dissipation depends on the junction temperature Tj. Higher power dissipation is allowed at lower
ambient temperatures. The conditions to determine the specified values are Tamb = 85 C and the use of a two layer PCB.
11. Recommended operating conditions
Table 7.
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VI
input voltage
VINT
3.0
5.5
V
EN, ILIM
0
VINT
V
30
V
VO
output voltage
VBUS; EN = LOW
0
VI/O
input/output voltage
D-, D+, ID
0
5.5
V
Tamb
ambient temperature
40
+85
C
12. Thermal characteristics
Table 8.
Symbol
Rth(j-a)
[1]
Thermal characteristics
Parameter
Conditions
thermal resistance from junction to ambient
[1]
Typ
Unit
73
K/W
Rth(j-a) is dependent upon board layout. To minimize Rth(j-a), ensure that all pins have a solid connection to larger copper layer areas. In
multi-layer PCBs, the second layer should be used to create a large heat spreader area below the device. Avoid using solder-stop
varnish under the device.
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
7 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
13. Static characteristics
Table 9.
Static characteristics
VI(VINT) = 4.0 V to 5.5 V; unless otherwise specified; Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Tamb = 25 C
Conditions
Tamb = 40 C to +85 C Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level input
voltage
EN input
1.2
-
-
1.2
-
V
VIL
LOW-level input
voltage
EN input
-
-
0.4
-
0.4
V
VO
output voltage
VDET; IVDET = 2 mA;
3V < VBUS < 30 V
1.5
-
5.5
5.5
V
VOL
LOW-level output
voltage
FAULT, IO = 8 mA
-
-
0.5
-
0.5
V
IO
output current
Current source; EN = HIGH
-
10
-
8
15
mA
Itrig
trigger current
OCP trigger; EN = HIGH;
see Figure 6
-
-
-
-
-
mA
Iocp
overcurrent
protection current
EN = HIGH; see Figure 6
-
Itrig+250
-
Itrig+150
Itrig+350
mA
Rpu
pull-up resistance
FAULT
20
-
200
-
-
k
Vpu
pull-up voltage
FAULT
-
-
VINT
-
VINT
V
RILIM
current limit
resistance
ILIM
IGND
ground current
VBUS open; EN = LOW;
see Figure 7 and Figure 8
-
20
-
-
40
A
VBUS open; EN = HIGH;
see Figure 7 and Figure 8
-
220
-
-
360
A
40
-
300
1.5
40
300
k
IOFF
power-off leakage
current
VBUS = 0 V to 30 V;
VINT = 0 V; see Figure 9
[2]
-
2
-
-
22
A
IS(OFF)
OFF-state leakage
current
VBUS = 0 V to 30 V;
see Figure 10 and Figure 11
[2]
-
2
-
-
22
A
VUVLO
undervoltage lockout
voltage
3.0
3.2
3.4
3.0
3.4
V
VOVLO
overvoltage lockout
voltage
5.5
5.75
6.0
5.5
6.0
V
-
150
-
-
-
mV
Vhys(OVLO) overvoltage lockout
hysteresis voltage
CI/O
input/output
capacitance
D-, D+, ID
-
3
-
-
-
pF
CI
input capacitance
EN
-
2
-
-
-
pF
CS(ON)
ON-state
capacitance
-
0.2
-
-
1
nF
[1]
Typical values are measured at Tamb = 25 C and VI(VINT) = 5.0 V unless otherwise specified.
[2]
Typical value is measured at Tamb = 25 C and VI(VBUS) = 5.0 V.
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
8 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
13.1 Graphs
DDD
,WULJ
$
,RFS
$
DDD
,*1'
$
5,/,0Nȍ
VI(VINT) = 5 V; Tamb = 25 C.
7DPE&
(1) Enabled
(1) Iocp
(2) Disabled
(2) Itrig
Fig 6.
Typical OCP trigger current and overcurrent
protection current versus the external resistor
value.
Fig 7.
DDD
,*1'
$
Typical ground current versus temperature
DDD
,2))
$
9,(19
9,9%869
(1) Tamb = 85 C
(2) Tamb = 25 C
(3) Tamb = 40 C
Fig 8.
Typical ground current versus input voltage
NX5P1100
Product data sheet
Fig 9.
Typical power-off leakage current versus input
voltage on pin VBUS
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
DDD
,62))
$
DDD
,62))
$
9,9%869
(1) Tamb = 85 C
(1) VI(VBUS) = 15.0 V
(2) Tamb = 25 C
(2) VI(VBUS) = 10.0 V
(3) Tamb = 40 C
(3) VI(VBUS) = 5.0 V
Fig 10. Typical OFF-state leakage current versus input
voltage on pin VBUS
7DPE&
Fig 11. Typical OFF-state leakage current versus
temperature
13.2 ON resistance
Table 10. ON resistance
At recommended operating conditions; voltages are referenced to GND (ground = 0 V)
Symbol Parameter
RON
Tamb = 25 C
Conditions
Tamb = 40 C to +85 C Unit
Min
Typ
Max
Min
Max
-
60
-
-
100
ON resistance switch enabled; ILOAD = 200 mA;
see Figure 12, Figure 13 and Figure 14
VI(VINT) = 4.0 V to 5.5 V
m
13.3 ON resistance test circuit and waveforms
96:
(1
9
9%86
9,17
*1'
,/2$'
9,
DDD
RON = VSW / ILOAD.
Fig 12. Test circuit for measuring ON resistance
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
10 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
DDD
521
Pȍ
521
Pȍ
DDD
7DPE&
(1) VI(VINT) = 5.5 V
(1) Tamb = 85 C
(2) VI(VINT) = 4.0 V
(2) Tamb = 25 C
9,179
(3) Tamb = 40 C
Fig 13. Typical ON resistance versus temperature
Fig 14. Typical ON resistance versus input voltage
14. Dynamic characteristics
Table 11. Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 16.
VI(VINT) = 4.0 V to 5.5 V.
Symbol Parameter
Tamb = 25 C
Conditions
Tamb = 40 C to +85 C
Min
Typ
Max
Min
Max
Unit
ten
enable time
EN to VBUS; see Figure 15
-
0.18
-
0.14
-
ms
tdis
disable time
EN to VBUS; see Figure 15
-
1.5
-
-
-
ms
ton
turn-on time
EN to VBUS; see Figure 15
-
0.63
-
0.52
-
ms
toff
turn-off time
EN to VBUS; see Figure 15
-
34.5
-
-
-
ms
tTLH
LOW to HIGH
output transition
time
VBUS; see Figure 15
-
0.39
-
0.16
-
ms
tTHL
HIGH to LOW
output transition
time
VBUS; see Figure 15
-
33
-
-
-
ms
tdegl
deglitch time
VINT; while enabled;
see Figure 23
-
8
-
-
-
ms
[1]
[1]
Guarantee by design.
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
14.1 Waveforms, graphs and test circuit
9,
(1LQSXW
90
*1'
92+
WRQ
WRII
WGLV
WHQ
9;
9%86RXWSXW
9<
*1'
W7/+
W7+/
DDD
Measurement points are given in Table 12.
Logic level: VOH is the typical output voltage that occurs with the output load.
Fig 15. Switching times
Table 12.
Measurement points
Supply voltage
EN Input
Output
VI(VINT)
VM
VX
VY
4.0 V to 5.5 V
0.5 VI
0.9 VOH
0.1 VOH
(1
9%86
*
9,
5/
9,17
9(;7
&/
DDD
Test data is given in Table 13.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
VEXT = External voltage for measuring switching times.
Fig 16. Test circuit for measuring switching times
Table 13.
Test data
Supply voltage
Input
Load
VEXT
VI
CL
RL
4.0 V to 5.5 V
1.5 V
100 F
150
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
12 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
DDD
DDD
(1
9%86
9
,9,17
$
,9,17
$
(1
9%86
9
WPV
WPV
EN = 1.5 V; VINT = 4 V; RL = 150 ; CL = 220 F;
RILIM = 50 k; Tamb = 25 C.
EN = 1.5 V; VINT = 5.5 V; RL = 150 ; CL =220 F;
RILIM = 50 k; Tamb = 25 C.
(1) EN
(1) EN
(2) VBUS
(2) VBUS
(3) II(VINT)
(3) II(VINT)
Fig 17. Typical enable time and in-rush current
DDD
Fig 18. Typical enable time and in-rush current
DDD
9%86
9
WHQ
V
5,/,0Nȍ
EN = 1.5 V; VINT = 4 V; RL = 150 ; CL = 100 F;
Tamb = 25 C.
Fig 19. Typical enable time versus current limit
resistance (RILIM)
NX5P1100
Product data sheet
WPV
EN = 1.5 V; VINT = 4 V; RL = 150 ; CL = 100 F;
RILIM = 50 k; Tamb = 25 C.
Fig 20. Typical disable time
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
13 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
DDD
DDD
9'(7
9
9%86
9
WPV
9%869
EN = 1.5 V; VINT = 5.5 V; RL = 150 ; CL = 100 F;
RILIM = 50 k; Tamb = 25 C.
Fig 21. Typical disable time
VINT = 5.5 V; Tamb = 25 C.
Fig 22. Typical VDET versus VBUS
DDD
,9%86
$
9,179%86
9
,RFS
,9,17
$
,WULJ
WGHJO
PV
,2
WV
DDD
WV
(1) VINT
(2) VBUS
(3) II(VINT)
Fig 23. OCP level definitions
NX5P1100
Product data sheet
Fig 24. OCP load curve
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
14 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
DDD
9,179%86
9
,9,17
$
DDD
9,179%86
9
,9,17
$
WV
(1) VINT
(1) VINT
(2) VBUS
(2) VBUS
(3) II(VINT)
(3) II(VINT)
Fig 25. OCP load curve
WPV
Fig 26. OCP load curve
1;3
$
9%86
(1
9,17
,/,0
ȍ
ȍ
*1'
)
Nȍ
)
9
DDD
Fig 27. Test circuit for measuring OCP load curves
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
15 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
15. Package outline
:/&63ZDIHUOHYHOFKLSVFDOHSDFNDJH
EXPSV[[PPPPSLWFK%DFNVLGHFRDWLQJLQFOXGHG
$
(
1;3
%
$
EDOO$
LQGH[DUHD
$
'
$
GHWDLO;
H
H
&
Y
Z
E
& $ %
&
\
'
H
&
H
H
%
$
EDOO$
LQGH[DUHD
;
PP
VFDOH
'LPHQVLRQVPPDUHWKHRULJLQDOGLPHQVLRQV
8QLW
PP
$
PD[ QRP PLQ $
$
E
'
(
H
H
H
Y
Z
\
ZOFVSBQ[SBSR
2XWOLQH
YHUVLRQ
5HIHUHQFHV
,(&
-('(&
-(,7$
(XURSHDQ
SURMHFWLRQ
,VVXHGDWH
1;3
Fig 28. Package outline NX5P1100 (WLCSP12)
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
16 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
16. Abbreviations
Table 14.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MOSFET
Metal-Oxide Semiconductor Field Effect Transistor
OCP
OverCurrent Protection
OTP
OverTemperature Protection
RCP
Reverse Current Protection
USB OTG
Universal Serial Bus On-The-Go
UVLO
Undervoltage lockout
VBUS
USB Power Supply
OVLO
Overvoltage lockout
17. Revision history
Table 15.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
NX5P1100 v.1
20140321
Product data sheet
-
-
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
17 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
NX5P1100
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
18 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
19 of 20
NX5P1100
NXP Semiconductors
Logic controlled high-side power switch
20. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
9
10
11
12
13
13.1
13.2
13.3
14
14.1
15
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
EN input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
FAULT output . . . . . . . . . . . . . . . . . . . . . . . . . . 4
VDET output . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Undervoltage lockout (UVLO). . . . . . . . . . . . . . 5
Overvoltage lockout (OVLO). . . . . . . . . . . . . . . 5
Over-current protection (OCP) . . . . . . . . . . . . . 5
ILIM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Over-temperature protection (OTP) . . . . . . . . . 5
Reverse bias current/back drive protection . . . 6
In-rush current protection . . . . . . . . . . . . . . . . . 6
Application diagram . . . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
Thermal characteristics . . . . . . . . . . . . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . 10
ON resistance test circuit and waveforms . . . 10
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms, graphs and test circuit . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 21 March 2014
Document identifier: NX5P1100