Si5010 OC-12/3, STM-4/1 SONET/SDH CLock and Data Recovery IC

Si5010
OC-12/3, STM-4/1 SONET/SDH C LOCK AND D ATA R ECOVERY IC
Features
Complete CDR solution includes the following:
Supports OC-12/3, STM-4/1
Exceeds
Low
power, 293 mW (TYP OC12)
Small footprint: 4x4 mm
DSPLL™ eliminates external
loop filter components
3.3 V tolerant control inputs
All SONET/SDH
jitter specifications
Jitter generation
1.6 mUIrms (typ)
Device
powerdown
indicator
Single 2.5 V supply
Ordering Information:
Loss-of-lock
See page 16.
Applications
Pin Assignments
SONET/SDH
test equipment
Optical transceiver modules
SONET/SDH regenerators
Description
CLKOUT–
CLKOUT+
GND
Si5010
NC
routers
Add/drop multiplexers
Digital cross connects
Board level serial links
RATESEL
SONET/SDH/ATM
20 19 18 17 16
1
15
PWRDN/CAL
VDD
2
14
VDD
GND
3
13
DOUT+
REFCLK+
4
12
DOUT–
REFCLK–
5
11
VDD
6
7
8
9
10
LOL
GND
DIN+
DIN–
The Si5010 represents an industry-leading combination of low-jitter, lowpower, and small size for high-speed CDRs. It operates from a single 2.5 V
supply over the industrial temperature range (–40 to 85 °C).
GND
Pad
Connection
VDD
The Si5010 is a fully-integrated low-power clock and data recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-12/3 or STM-4/1 data
rates. DSPLL® technology eliminates sensitive noise entry points thus
making the PLL less susceptible to board-level interaction and helping to
ensure optimal jitter performance in the application.
REXT
Top View
Functional Block Diagram
LOL
DIN+
DIN–
2
BUF
DSPLL TM
Phase-Locked
Loop
Retim er
BUF
2
DOUT+
DOUT–
PW RDN/CAL
Bias
REXT
Rev. 1.5 2/15
2
RATESEL
BUF
2
CLKOUT+
CLKOUT–
REFCLK+
REFCLK–
Copyright © 2015 by Silicon Laboratories
Si5010
Si5010
2
Rev. 1.5
Si5010
TABLE O F C ONTENTS
Section
Page
1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1. DSPLL® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3. Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.4. Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5. Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.6. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.7. Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.8. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. Pin Descriptions: Si5010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9. 4x4 mm 20L QFN Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Rev. 1.5
3
Si5010
1. Detailed Block Diagram
DOUT+
Retim e
DOUT–
c
DIN+
DIN–
Phase
Detector
A/D
VCO
DSP
CLK
Divider
CLKOUT+
c
CLKOUT–
n
REFCLK+
Lock
Detector
REFCLK–
LOL
RATESEL
REXT
Calibration
Bias
G eneration
4
PWRDN/CAL
Rev. 1.5
Si5010
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Ambient Temperature
Si5010 Supply Voltage2
Test Condition
Min1
Typ
Max1
Unit
TA
–40
25
85
°C
VDD
2.375
2.5
2.625
V
Notes:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2. The Si5010 specifications are guaranteed when using the recommended application circuit (including component
tolerance) shown in "3. Typical Application Schematic" on page 9.
V
SIGNAL +
Differential
VICM, VOCM
SIGNAL –
I/Os
VIS
Single Ended Voltage
(SIGNAL+) – (SIGNAL–)
Differential Peak-to-Peak Voltage
VID,VOD
Differential
Voltage Swing
t
Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
t C-D
DOUT
CLKOUT
Figure 2. Differential Clock to Data Timing
80%
DOUT,
CLKOUT
20%
tF
tR
Figure 3. Differential DOUT and CLKOUT Rise/Fall Times
Rev. 1.5
5
Si5010
Table 2. DC Characteristics
(VDD = 2.5 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Supply Current
OC-12
OC-3
IDD
Power Dissipation
OC-12
OC-3
PD
Test Condition
Min
Typ
Max
Unit
—
—
117
124
131
138
mA
—
—
293
310
344
362
mW
VICM
varies with VDD
—
.80 x VDD
—
V
Single Ended Input Voltage (DIN, REFCLK)
VIS
See Figure 1
200
—
750
mVPP
Differential Input Voltage Swing*
(DIN, REFCLK)
VID
See Figure 1
200
—
1500
mVPP
Input Impedance (DIN, REFCLK)
RIN
Line-to-Line
84
100
116

Differential Output Voltage Swing
(DOUT)
VOD
100  Load
Line-to-Line
780
970
1260
mVPP
Differential Output Voltage Swing
(CLKOUT)
VOD
100  Load
Line-to-Line
780
970
1260
mVPP
Output Common Mode Voltage
(DOUT,CLKOUT)
VOCM
100  Load
Line-to-Line
—
VDD –
0.23
—
V
Output Impedance (DOUT,CLKOUT)
ROUT
Single-ended
84
100
116

Output Short to GND (DOUT,CLKOUT)
ISC(–)
—
25
31
mA
Output Short to VDD (DOUT,CLKOUT)
ISC(+)
–17.5
–14.5
—
mA
Input Voltage Low (LVTTL Inputs)
VIL
—
—
.8
V
Input Voltage High (LVTTL Inputs)
VIH
2.0
—
—
V
Input Low Current (LVTTL Inputs)
IIL
—
—
10
A
Input High Current (LVTTL Inputs)
IIH
—
—
10
A
Common Mode Input Voltage (DIN, REFCLK)
Output Voltage Low (LVTTL Outputs)
VOL
IO = 2 mA
—
—
0.4
V
Output Voltage High (LVTTL Outputs)
VOH
IO = 2 mA
2.0
—
—
V
Input Impedance (LVTTL Inputs)
RIN
10
—
—
k
PWRDN/CAL Leakage Current
IPWRDN
15
25
35
A
VPWRDN  0.8 V
*Note: The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage
swing of the signal applied to the active input must exceed the specified minimum differential input voltage swing (V ID
min) and the unused input must be ac-coupled to ground. When driving differentially, the difference between the positive
and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this range.) In
either case, the voltage applied to any individual pin (DIN+, DIN–, REFCLK+, or REFCLK–) must not exceed the
specified maximum Input Voltage Range (VIS max).
6
Rev. 1.5
Si5010
Table 3. AC Characteristics (Clock & Data)
(VA 2.5 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Output Clock Rate
fCLK
Output Rise/Fall Time (differential)
tR,tF
Figure 3
Clock to Data Delay
OC-12
OC-3
t(c-d)
Figure 2
Input Return Loss
100 kHz–1 GHz
Min
Typ
Max
Unit
150
—
666
MHz
—
80
110
ps
835
4040
880
4090
930
4140
ps
ps
—
20
—
dB
Table 4. AC Characteristics (PLL Characteristics)
(VDD = 2.5 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Tolerance (OC-12 Mode)*
JTOL(PP)
f = 30 Hz
40
—
—
UIPP
f = 300 Hz
4
—
—
UIPP
f = 25 kHz
4
—
—
UIPP
f = 250 kHz
0.4
—
—
UIPP
f = 30 Hz
40
—
—
UIPP
f = 300 Hz
4
—
—
UIPP
f = 6.5 kHz
4
—
—
UIPP
Jitter Tolerance (OC-3 Mode)*
RMS Jitter Generation*
Peak-to-Peak Jitter Generation
Jitter Transfer Bandwidth
*
Jitter Transfer Peaking*
Acquisition Time
Input Reference Clock Duty Cycle
JTOL(PP)
f = 65 kHz
0.4
—
—
UIPP
JGEN(rms)
with no jitter on serial data
—
1.6
3.0
mUI
JGEN(PP)
with no jitter on serial data
—
25
55
mUI
JBW
OC-12 Mode
—
—
500
kHz
OC-3 Mode
—
—
130
kHz
JP
f < 2 MHz
—
.03
0.1
dB
TAQ
After falling edge of
PWRDN/CAL
1.45
1.5
1.7
ms
From the return of valid
data
40
60
150
s
40
50
CDUTY
Reference Clock Range
19.44
60
%
155.52
MHz
Input Reference Clock Frequency
Tolerance
CTOL
–100
—
100
ppm
Frequency Difference at which
Receive PLL goes out of Lock
(REFCLK compared to the divided
down VCO clock)
LOL
450
600
750
ppm
Frequency Difference at which
Receive PLL goes into Lock
(REFCLK compared to the divided
down VCO clock)
LOCK
150
300
450
ppm
*Note: Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 223 –1 data pattern.
Rev. 1.5
7
Si5010
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
DC Supply Voltage
VDD
–0.5 to 2.8
V
LVTTL Input Voltage
VDIG
–0.3 to 3.6
V
Differential Input Voltages
VDIF
–0.3 to (VDD+ 0.3)
V
±50
mA
Maximum Current any output PIN
Operating Junction Temperature
TJCT
–55 to 150
°C
Storage Temperature Range
TSTG
–55 to 150
°C
1
kV
ESD HBM Tolerance (100 pf, 1.5 k)
Note: Permanent device damage may occur if the above absolute maximum ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
8
Symbol
Test Condition
Value
Unit
JA
Still Air
38
°C/W
Rev. 1.5
Si5010
3. Typical Application Schematic
LVTTL
Control Inputs
Loss-of-Lock
Indicator
LOL
PWRDN/CAL
DOUT+
DIN–
DOUT–
Si5010
REFCLK+
CLKOUT+
CLKOUT–
Recovered
Data
Recovered
Clock
GND
REFCLK–
VDD
System
Reference
Clock
DIN+
REXT
High-Speed
Serial Input
RATESEL1-0
2
0.1 F
10 k
(1%)
VDD
2200 pF
20 pF
Rev. 1.5
9
Si5010
4. Functional Description
4.3. Multi-Rate Operation
The Si5010 utilizes a phase-locked loop (PLL) to
recover a clock synchronous to the input data stream.
This clock is used to retime the data, and both the
recovered clock and data are output synchronously via
current mode logic (CML) drivers. Optimal jitter
performance is obtained by using Silicon Laboratories'
DSPLL® technology to eliminate the noise entry points
caused by external PLL filter components.
The Si5010 supports clock and data recovery for OC12/3 and STM-4/1 data streams.
Multi-rate operation is achieved by configuring the
device to divide down the output of the VCO to the
desired data rate. The RATESEL configuration and
associated data rates are given in Table 7.
Table 7. Data-Rate Configuration
4.1. DSPLL®
The PLL structure (shown in "3. Typical Application
Schematic" on page 9) utilizes Silicon Laboratories'
DSPLL technology to eliminate the need for external
loop filter components found in traditional PLL
implementations. This is achieved by using a digital
signal processing (DSP) algorithm to replace the loop
filter commonly found in analog PLL designs. This
algorithm processes the phase detector error term and
generates a digital control value to adjust the frequency
of the voltage-controlled oscillator (VCO). Because
external loop filter components are not required,
sensitive noise entry points are eliminated, thus making
the DSPLL less susceptible to board-level noise
sources that make SONET/SDH jitter compliance
difficult to attain.
4.2. PLL Self-Calibration
The Si5020 achieves optimal jitter performance by
using self-calibration circuitry to set the loop gain
parameters within the DSPLL. For the self-calibration
circuitry to operate correctly, the power supply voltage
must exceed 2.25 V when calibration occurs. For best
performance, the user should force a self-calibration
once the supply has stabilized on power-up.
A self-calibration can be initiated by forcing a high-tolow transition on the power-down control input,
PWRDN/CAL, while a valid reference clock is supplied
to the REFCLK input. The PWRDN/CAL input should be
held high at least 1 s before transitioning low to
guarantee a self-calibration. Several application circuits
that could be used to initiate a power-on self-calibration
are provided in Silicon Laboratories application note
“AN42: Controlling DSPLL Self-Calibration for the
Si5020/5018/5010 CDR Devices and Si531x Clock
Multiplier/Regenerator Devices”.
10
RATESEL
SONET/SDH
0
622.08 Mbps
1
155.52 Mbps
4.4. Reference Clock Detect
The Si5010 CDR requires an external reference clock
applied to the REFCLK input for normal device
operation. When REFCLK is absent, the LOL alarm will
always be asserted when it has been determined that
no activity exists on REFCLK, indicating the lock status
of the PLL is unknown. Additionally, the Si5010 uses the
reference clock to center the VCO operating frequency
so that clock and data can be recovered from the input
data stream. The VCO operates at an integer multiple of
the REFCLK frequency. (See “Lock Detect” section.)
The device will self configure for operation with one of
three reference clock frequencies. This eliminates the
need to externally configure the device to operate with a
particular reference clock. The REFCLK frequency
should be 19.44 MHz, 77.76 MHz, or 155.52 MHz with a
frequency accuracy of ±100 ppm.
4.5. Lock Detect
The Si5010 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. The circuit compares the frequency of a
divided-down version of the recovered clock with the
frequency of the applied reference clock (REFCLK). If
the recovered clock frequency deviates from that of the
reference clock by the amount specified in Table 4 on
page 7, the PLL is declared out-of-lock, and the loss-oflock (LOL) pin is asserted high. In this state, the PLL will
periodically try to reacquire lock with the incoming data
stream. During reacquisition, the recovered clock may
drift over a ±600 ppm range relative to the applied
reference clock, and the LOL output alarm may toggle
until the PLL has reacquired frequency lock. Due to the
low noise and stability of the DSPLL, under the
condition where data is removed from the inputs, there
is the possibility that the PLL will not drift enough to
render an out-of-lock condition.
Rev. 1.5
Si5010
If REFCLK is removed, the LOL output alarm will always
be asserted when it has been determined that no
activity exists on REFCLK, indicating the frequency lock
status of the PLL is unknown.
Note: LOL is not asserted during PWRDN/CAL.
4.6. PLL Performance
The PLL implementation used in the Si5010 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 3, September 2000 and ITU-T G.958.
4.6.3. Jitter Generation
The Si5010 meets all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
Si5010 typically generates less than 1.6 mUIrms of jitter
when presented with jitter-free input data.
Jitter
Transfer
4.6.1. Jitter Tolerance
20 dB/Decade
Slope
0.1 dB
The Si5010’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 4. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
Acceptable
Range
Fc
Frequency
Sinusoidal
Input
Jitter (UI p-p)
Slope = 20 dB/Decade
15
SONET
Data Rate
Fc
(kHz)
1.5
OC-12
500
OC-3
130
0.15
Figure 5. Jitter Transfer Specification
f0
f1
f2
f3
ft
4.7. Powerdown
Frequency
F0
(Hz)
F1
(Hz)
OC-12
10
30
300
25
250
OC-3
10
30
300
6.5
65
SONET
Data Rate
F2
(Hz)
F3
(kHz)
The Si5010 provides a powerdown pin, PWRDN/CAL,
that disables the device. When the PWRDN/CAL pin is
driven high, the positive and negative terminals of
CLKOUT and DOUT are each tied to VDD through
100  on-chip resistors. This feature is useful in
reducing power consumption in applications that
employ redundant serial channels. When PWRDN/CAL
is released (set to low) the digital logic resets to a
known initial condition, recalibrates the DSPLL®, and
will begin to lock to the data stream.
Ft
(kHz)
Figure 4. Jitter Tolerance Specification
4.6.2. Jitter Transfer
The Si5010 is fully compliant with the relevant Bellcore/
ITU specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency (see
Figure 5). These measurements are made with an input
test signal that is degraded with sinusoidal jitter whose
magnitude is defined by the mask in Figure 4.
Note: LOL is not asserted when the device is in the powerdown state.
4.8. Device Grounding
The Si5010 uses the GND pad on the bottom of the 20pin QFN package for device ground. This pad should be
connected directly to the analog supply ground. See
Figures 10 and 12 for the ground (GND) pad location.
Rev. 1.5
11
Si5010
4.9. Bias Generation Circuitry
4.10. Differential Input Circuitry
The Si5010 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption versus traditional
implementations that use an internal resistor. The bias
generation circuitry requires a 10 k (1%) resistor
connected between REXT and GND.
The Si5010 provides differential inputs for both the highspeed data (DIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is
shown in Figure 6. In applications where direct dc
coupling is possible, the 0.1 µF capacitors may be
omitted. The DIN and REFCLK input amplifiers require
an input signal with a minimum differential peak-to-peak
voltage listed in Table 2 on page 6.
Si5010
Differential
Driver
VDD
2.5 k
0.1 µF
Zo = 50 
DIN+,
REFCLK+
Zo = 50 
DIN–,
REFCLK–
10 k
0.1 µF
2.5 k
102 
10 k
GND
Figure 6. Input Termination for DIN and REFCLK (AC-coupled)
Si5010
Clock
source
VDD
2.5 k
0.1 F
Zo = 50 
REFCLK +
10 k
2.5 k
100 
102 
REFCLK –
10 k
0.1 F
GND
Figure 7. Single-Ended Input Termination for REFCLK (AC-coupled)
12
Rev. 1.5
Si5010
Si5010
Clock
source
VDD
2.5 k
0.1 F
Zo = 50 
DIN +
10 k
2.5 k
100 
102 
DIN –
10 k
0.1 F
GND
Figure 8. Single-Ended Input Termination for DIN (AC-coupled)
4.11. Differential Output Circuitry
The Si5010 utilizes a current mode logic (CML)
architecture to output both the recovered clock
(CLKOUT) and data (DOUT). An example of output
termination with ac coupling is shown in Figure 9. In
applications in which direct dc coupling is possible, the
0.1 µF capacitors may be omitted. The differential peakto-peak voltage swing of the CML architecture is listed
in Table 2 on page 6.
Si5010
VDD
50 
VDD
100 
DOUT+,
CLKOUT+
0.1F
Zo = 50 
DOUT–,
CLKOUT–
0.1F
Zo = 50 
100 
VDD
50 
VDD
Figure 9. Output Termination for DOUT and CLKOUT (AC-coupled)
Rev. 1.5
13
Si5010
CLKOUT–
CLKOUT+
GND
RATESEL
NC
5. Pin Descriptions: Si5010
20 19 18 17 16
REFCLK+
4
REFCLK–
5
6
7
8
9
10
DIN–
3
DIN+
GND
GND
Pad
Connection
GND
2
LOL
1
VDD
VDD
REXT
15
PWRDN/CAL
14
VDD
13
DOUT+
12
DOUT–
11
VDD
Top View
Figure 10. Si5010 Pin Configuration
Table 8. Si5010 Pin Descriptions
Pin #
Pin Name
1
REXT
2, 7, 11, 14
VDD
2.5 V
Supply Voltage.
Nominally 2.5 V.
3, 8, 18, and
GND Pad
GND
GND
Supply Ground.
Nominally 0.0 V. The GND pad found on the bottom
of the 20-pin micro leaded package (see Figure 12)
must be connected directly to supply ground.
4
5
REFCLK+
REFCLK–
I
See Table 2
Differential Reference Clock.
The reference clock sets the initial operating frequency used by the onboard PLL for clock and data
recovery. Additionally, the reference clock is used to
derive the clock output when no data is present.
6
LOL
O
LVTTL
Loss-of-Lock.
This output is driven high when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 7.
9
10
DIN+
DIN–
I
See Table 2
14
I/O
Signal Level
Description
External Bias Resistor.
This resistor is used by onboard circuitry to establish bias currents within the device. This pin must
be connected to GND through a 10 k1resistor.
Rev. 1.5
Differential Data Input.
Clock and data are recovered from the differential
signal present on these pins.
Si5010
Table 8. Si5010 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
12
13
DOUT–
DOUT+
O
CML
Differential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN. It is
phase aligned with CLKOUT and is updated on the
rising edge of CLKOUT.
15
PWRDN/CAL
I
LVTTL
Powerdown.
To shut down the high-speed outputs and reduce
power consumption, hold this pin high. For normal
operation, hold this pin low.
Calibration.
To initiate an internal self-calibration, force a highto-low transition on this pin. (See "4.2. PLL SelfCalibration" on page 10.)
Note: This input has a weak internal pulldown.
16
17
CLKOUT–
CLKOUT+
O
CML
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN. In the absence of data, the output
clock is derived from REFCLK.
19
RATESEL
I
LVTTL
Data Rate Select.
This pin configures the onboard PLL for clock and
data recovery at one of two user selectable data
rates. See Table 7 for configuration settings.
Note: This input has a weak internal pulldown.
20
No Connect.
This pin should be tied to ground.
NC
Rev. 1.5
15
Si5010
6. Ordering Guide
Part Number
Package
Voltage
Pb-Free
Temperature
Si5010-X-GM
20-lead QFN
2.5
Yes
–40 to 85 °C
Notes:
1. “X” denotes product revision.
2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel.
3. These devices use a NiPdAu pre-plated finish on the leads that is fully RoHS6 compliant while being
fully compatible with both leaded and lead-free card assembly processes.
16
Rev. 1.5
Si5010
7. Top Marking
Figure 11. Si5010 Top Marking
Table 9. Top Marking Explanation
Part Number
Die Revision (R)
Assembly Date (YWW)
Si5010-B-GM
B
Y = Last digit of current year
WW = Work week
Rev. 1.5
17
Si5010
8. Package Outline
Figure 12 illustrates the package details for the Si5010. Table 10 lists the values for the dimensions shown in the
illustration.
Figure 12. 20-pin Quad Flat No-Lead (QFN)
Table 10. Package Dimensions
Dimension
Min
Nom
Max
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
E2
2.0
2.10
2.20
A1
0.00
0.02
0.05
L
0.50
0.60
0.70
b
0.18
0.25
0.30
aaa
0.15
bbb
0.10
ccc
0.08
D
D2
4.00 BSC
2.0
2.10
2.20
e
0.50 BSC
ddd
0.05
E
4.00 BSC
eee
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VGGD-1.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
18
Rev. 1.5
9. 4x4 mm 20L QFN Recommended PCB Layout
See Note 8
Gnd Pin
See Note 9
Gnd Pin
Gnd Pin
Figure 13. 4x4 mm 20L QFN PCB Layout
Table 11. PCB Land Pattern Dimensions
Symbol
Parameter
Dimensions
Min
Nom
Max
A
Pad Row/Column Width/Length
2.23
2.25
2.28
D
Thermal Pad Width/Height
2.03
2.08
2.13
e
Pad Pitch
—
0.50 BSC
—
G
Pad Row/Column Separation
2.43
2.46
2.48
R
Pad Radius
—
0.12 REF
—
Notes:
1. All dimensions listed are in millimeters (mm).
2. The perimeter pads are to be Non-Solder Mask Defined (NSMD). Solder mask openings should be designed to leave 60-75 mm
separation between solder mask and pad metal, all the way around the pad.
3. The center thermal pad is to be Solder Mask Defined (SMD).
4. Thermal/Ground vias placed in the center pad should be no less than 0.2 mm (8 mil) diameter and tented from the top to prevent
solder from flowing into the via hole.
5. The stencil aperture should match the pad size (1:1 ratio) for the perimeter pads. A 3x3 array of 0.5 mm square stencil openings, on a
0.65 mm pitch, should be used for the center thermal pad.
6. A stencil thickness of 5 mil is recommended. The stencil should be laser cut and electropolished, with trapezoidal walls to facilitate
paste release.
7. A “No-Clean”, Type 3 solder paste should be used for assembly. Nitrogen purge during reflow is recommended.
8. Do not place any signal or power plane vias in these “keep out” regions.
9. Suggest four 0.38 mm (15 mil) vias to the ground plane.
Si5010
Table 11. PCB Land Pattern Dimensions (Continued)
X
Pad Width
Y
Pad Length
Z
Pad Row/Column Extents
0.23
0.25
0.28
—
0.94 REF
—
4.26
4.28
4.31
Notes:
1. All dimensions listed are in millimeters (mm).
2. The perimeter pads are to be Non-Solder Mask Defined (NSMD). Solder mask openings should be designed to leave 60-75 mm
separation between solder mask and pad metal, all the way around the pad.
3. The center thermal pad is to be Solder Mask Defined (SMD).
4. Thermal/Ground vias placed in the center pad should be no less than 0.2 mm (8 mil) diameter and tented from the top to prevent
solder from flowing into the via hole.
5. The stencil aperture should match the pad size (1:1 ratio) for the perimeter pads. A 3x3 array of 0.5 mm square stencil openings, on a
0.65 mm pitch, should be used for the center thermal pad.
6. A stencil thickness of 5 mil is recommended. The stencil should be laser cut and electropolished, with trapezoidal walls to facilitate
paste release.
7. A “No-Clean”, Type 3 solder paste should be used for assembly. Nitrogen purge during reflow is recommended.
8. Do not place any signal or power plane vias in these “keep out” regions.
9. Suggest four 0.38 mm (15 mil) vias to the ground plane.
20
Rev. 1.5
Si5010
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
Added
"7. Top Marking" on page 17.
“8. Package Outline: Si5010-BM” on
page 17.
Added "9. 4x4 mm 20L QFN Recommended
PCB Layout" on page 19.
Updated
Revision 1.1 to Revision 1.2
Made
minor note corrections to "9. 4x4 mm 20L
QFN Recommended PCB Layout" on page 19.
Revision 1.2 to Revision 1.3
Global
change: MLP to QFN.
"6. Ordering Guide" on page 16.
Updated "7. Top Marking" on page 17.
Updated "8. Package Outline" on page 18.
Updated "9. 4x4 mm 20L QFN Recommended
PCB Layout" on page 19.
Updated
Revision 1.3 to Revision 1.4
Changed
Minimum Output Clock Rate to
150 MHz in Table 3 on page 7.
Added "7. Top Marking" on page 17.
Updated "6. Ordering Guide" on page 16.
Updated "8. Package Outline" on page 18.
Revision 1.4 to Revision 1.5
Updated
“8. Package Outline”
Rev. 1.5
21
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