Si5010 OC-12/3, STM-4/1 SONET/SDH C LOCK AND D ATA R ECOVERY IC Features ! ! ! ! Supports OC-12/3, STM-4/1 Low Power, 293 mW (TYP OC-12) Small Footprint: 4 mm x 4 mm DSPLL™ Eliminates External Loop Filter Components 3.3 V Tolerant Control Inputs ! ! ! ! ! Exceeds All SONET/SDH Jitter Specifications Jitter Generation 1.6 mUIRMS (TYP) S ! i5 01 0 Complete CDR solution includes the following: Device Power Down Loss-of-Lock Indicator Single 2.5 V Supply Ordering Information: See page 14. Applications CLKOUT– 20 19 18 17 16 RE XT 1 15 PW R DN/CA L VD D 2 14 VD D GND 3 13 DO UT+ RE FCLK+ 4 12 DO UT– RE FCLK– 5 11 VD D 6 7 8 9 10 DIN– The Si5010 represents an industry-leading combination of low jitter, low power, and small size for high speed CDRs. It operates from a single 2.5 V supply over the industrial temperature range (–40°C to 85°C). G ND Pad DIN+ The Si5010 is a fully integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-12/3 or STM-4/1 data rates. DSPLL™ technology eliminates sensitive noise entry points thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance in the application. CLKOUT+ Description GND Si5010 RATESEL ! GND ! ! Pin Assignments SONET/SDH Test Equipment Optical Transceiver Modules SONET/SDH Regenerators NC ! ! LO L ! SONET/SDH/ATM Routers Add/Drop Multiplexers Digital Cross Connects Board Level Serial Links VDD ! Top View Functional Block Diagram LO L D IN + D IN – 2 BUF DSPLL TM Phase-Locked Loop Retim er BUF 2 D O U T+ D O U T– P W R D N /C A L Bias REXT BUF 2 RATESEL Preliminary Rev. 0.31 4/01 2 C LK O U T+ C LK O U T– REFC LK+ REFC LK– Copyright © 2001 by Silicon Laboratories Si5010-DS031 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i5 01 0 2 Preliminary Rev. 0.31 Si5010 TA B L E O F C O N T E N T S Section Page Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si5010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preliminary Rev. 0.31 4 5 9 9 9 9 9 9 10 10 10 11 11 12 14 15 16 3 S i5 01 0 Detailed Block Diagram DOUT+ R e tim e DOUT– c D IN + D IN – Phase D e te c to r A /D VCO DSP CLK D ivid e r CLKOUT+ c CLKOUT– n REFCLK+ Lock D e te c to r REFCLK– LOL RATES EL REXT C a lib ratio n B ias G en e ra tio n P W R D N /C A L Figure 1. Detailed Block Diagram 4 Preliminary Rev. 0.31 Si5010 Electrical Specifications Table 1. Recommended Operating Conditions Symbol Parameter Ambient Temperature Si5010 Supply Voltage2 Test Condition Min1 Typ Max1 Unit TA –40 25 85 °C VDD 2.375 2.5 2.625 V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. 2. The Si5010 specifications are guaranteed when using the recommended application circuit (including component tolerance) of Figure 5 on page 8. V SIGNAL + Differential V ICM , V O CM SIGNAL – I/Os V IS (SIGNAL +) – (SIGNAL –) V ID ,V O D Differential Voltage Swing Differential Peak-to-Peak Voltage t Figure 2. Differential Voltage Measurement tC-D DOUT CLKOUT Figure 3. Clock to Data Timing 80% DOUT, CLKOUT 20% tF tR Figure 4. DOUT and CLKOUT Rise/Fall Times Preliminary Rev. 0.31 5 S i5 01 0 Table 2. DC Characteristics (VDD = 2.5 V ± 5%, TA = –40°C to 85°C) Parameter Symbol Supply Current OC-12 OC-3 IDD Power Dissipation OC-12 OC-3 PD Test Condition Min Typ Max Unit — — 117 124 127 134 mA — — 293 310 333 352 mW Common Mode Input Voltage (DIN, REFCLK) VICM varies with VDD — .80 VDD — V Input Voltage Range* (DIN+, DIN–, REFCLK+, REFCLK–) VIS See Figure 2 — — 750 mV Differential Input Voltage Swing* (DIN, REFCLK) VID See Figure 2 200 — 1500 mV (pk-pk) Input Impedance (DIN, REFCLK) RIN Line-to-Line 84 100 116 Ω Differential Output Voltage Swing (DOUT) VOD 100 Ω Load Line-to-Line TBD 940 TBD mV (pk-pk) Differential Output Voltage Swing (CLKOUT) VOD 100 Ω Load Line-to-Line TBD 900 TBD mV (pk-pk) Output Common Mode Voltage (DOUT,CLKOUT) VOCM 100 Ω Load Line-to-Line — VDD – 0.7 — V Output Impedance (DOUT,CLKOUT) ROUT Single-ended 84 100 116 Ω Output Short to GND (DOUT,CLKOUT) ISC(–) — 25 TBD mA Output Short to VDD (DOUT,CLKOUT) ISC(+) TBD –15 — mA Input Voltage Low (LVTTL Inputs) VIL — — .8 V Input Voltage High (LVTTL Inputs) VIH 2.0 — — V Input Low Current (LVTTL Inputs) IIL — — 10 µA Input High Current (LVTTL Inputs) IIH — — 10 µA " Output Voltage Low (LVTTL Outputs) VOL IO = 2 mA — — 0.4 V Output Voltage High (LVTTL Outputs) VOH IO = 2 mA 2.0 — — V Input Impedance (LVTTL Inputs) RIN 10 — — kΩ TBD 25 TBD µA PWRDN/CAL Leakage Current IPWRDN VPWRDN ≥ 0.8 V *Note: The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage swing of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (VID min) and the unused input must be tied to ground. When driving differentially, the difference between the positive and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this range.) In either case, the voltage applied to any individual pin (DIN+, DIN–, REFCLK+, or REFCLK–) must not exceed the specified maximum Input Voltage Range (VIS max). 6 Preliminary Rev. 0.31 Si5010 Table 3. AC Characteristics (Clock & Data) (VA 2.5 V ± 5%, TA = –40°C to 85°C) Parameter Symbol Test Condition Min Typ Max Unit .15 — 666 MHz Output Clock Rate fCLK Output Rise Time tR Figure 4 — 100 TBD ps tF Figure 4 — 100 TBD ps t(c-d) Figure 3 — — 890 4100 TBD TBD ps ps 18.7 — — dB Output Fall Time Clock to Data Delay OC-12 OC-3 Input Return Loss 100 kHz–622 MHz Table 4. AC Characteristics (PLL Characteristics) (VDD = 2.5 V ± 5%, TA = –40°C to 85°C) Parameter Jitter Tolerance (OC-12 Mode) Jitter Tolerance (OC-3 Mode) * * RMS Jitter Generation* Test Condition Min Typ Max Unit JTOL(PP) f = 30 Hz 40 TBD — UIPP f = 300 Hz 4 TBD — UIPP JTOL(PP) f = 25 kHz 4 TBD — UIPP f = 250 kHz 0.4 TBD — UIPP f = 30 Hz 40 TBD — UIPP f = 300 Hz 4 TBD — UIPP f = 6.5 kHz 4 TBD — UIPP f = 65 kHz 0.4 TBD — UIPP — 1.6 3.0 mUI — 25 55 mUI JGEN(RMS) with no jitter on serial data Peak-to-Peak Jitter Generation Jitter Transfer Bandwidth Symbol * * Jitter Transfer Peaking Acquisition Time Input Reference Clock Duty Cycle JGEN(PP) with no jitter on serial data JBW OC-12 Mode — — 500 kHz OC-3 Mode — — 130 kHz JP f < 2 MHz — .03 0.1 dB TAQ After falling edge of PWRDN/CAL 1.45 1.5 1.7 ms From the return of valid data 40 60 150 µs 40 50 60 % 155.52 MHz CDUTY Reference Clock Range 19.44 Input Reference Clock Frequency Tolerance CTOL –100 — 100 ppm Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) LOL TBD 600 TBD ppm Frequency Difference at which Receive PLL goes into Lock (REFCLK compared to the divided down VCO clock) LOCK TBD 300 TBD ppm *Note: Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 223 –1 data pattern. Preliminary Rev. 0.31 7 S i5 01 0 Table 5. Absolute Maximum Ratings Parameter Symbol Value Unit DC Supply Voltage VDD –0.5 to 2.8 V LVTTL Input Voltage VDIG –0.3 to 3.6 V Differential Input Voltages VDIF –0.3 to (VDD+ 0.3) V ±50 mA °C Maximum Current any output PIN Operating Junction Temperature TJCT –55 to 150 Storage Temperature Range TSTG –55 to 150 °C 300 °C 1 kV Lead Temperature (soldering 10 seconds) ESD HBM Tolerance (100 pf, 1.5 kΩ) Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Thermal Characteristics Parameter Symbol Test Condition Value Unit ϕJA Still Air 38 °C/W Thermal Resistance Junction to Ambient LOL RATESEL High Speed Serial Input Loss-of-Lock Indicator PWRDN/CAL LVTTL Control Inputs DIN+ DOUT+ DIN– DOUT– Recovered Data Si5010 CLKOUT+ REFCLK– CLKOUT– Ω 10 kΩ (1%) VDD GND REFCLK+ REXT System Reference Clock VDD 0.1 µF 2200pF 20pF Figure 5. Si5010 Typical Application Circuit 8 Preliminary Rev. 0.31 Recovered Clock Si5010 Functional Description The Si5010 utilizes a phase-locked loop (PLL) to recover a clock synchronous to the input data stream. This clock is used to retime the data, and both the recovered clock and data are output synchronously via current mode logic (CML) drivers. Optimal jitter performance is obtained by using Silicon Laboratories' DSPLL™ technology to eliminate the noise entry points caused by external PLL loop filter components. DSPLL™ The phase-locked loop structure (shown in Figure 1 on page 4) utilizes Silicon Laboratories' DSPLL technology to eliminate the need for external loop filter components found in traditional PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage controlled oscillator (VCO). Because external loop filter components are not required, sensitive noise entry points are eliminated thus making the DSPLL less susceptible to board-level noise sources that make SONET/SDH jitter compliance difficult to attain. PLL Self-Calibration The Si5020 achieves optimal jitter performance by using self-calibration circuitry to set the loop gain parameters within the DSPLL. For the self-calibration circuitry to operate correctly, the power supply voltage must exceed 2.25 V when calibration occurs. For best performance, the user should force a self-calibration once the supply has stabilized on power-up. A self-calibration can be initiated by forcing a high-to-low transition on the power-down control input, PWRDN/CAL, while a valid reference clock is supplied to the REFCLK input. The PWRDN/CAL input should be held high at least 1 µS before transitioning low to guarantee a self-calibration. Several application circuits that could be used to initiate a power-on self-calibration are provided in Silicon Laboratories application note AN42. Multi-Rate Operation The Si5010 supports clock and data recovery for OC-12/3 and STM-4/1 data streams. Multi-rate operation is achieved by configuring the device to divide down the output of the VCO to the desired data rate. The RATESEL configuration and associated data rates are given in Table 7. Table 7. Data-Rate Configuration RATESEL SONET/SDH 0 622.08 Mbps 1 155.52 Mbps Reference Clock Detect The Si5020 uses the reference clock to center the VCO operating frequency so that clock and data can be recovered from the input data stream. The VCO operates at an integer multiple of the REFCLK frequency. (See “Lock Detect” section.) The device will self configure for operation with one of three reference clock frequencies. This eliminates the need to externally configure the device to operate with a particular reference clock. The REFCLK frequency should be 19.44 MHz, 77.76 MHz, or 155.52 MHz with a frequency accuracy of ±100 ppm. Lock Detect The Si5010 provides lock-detect circuitry that indicates whether the DSPLL has frequency locked with the incoming data signal (DIN). The circuit compares the frequency of a divided down version of the CLKOUT output with the frequency of the supplied reference clock. If the divided CLKOUT frequency deviates from that of the reference clock by the amount specified in Table 4 on page 7, the PLL is declared out of lock, and the loss-of-lock (LOL) pin is asserted. While out of lock, the DSPLL will try to reacquire lock with the input data. During reacquisition, the clock output (CLKOUT) will drift over a range of approximately 1% relative to the supplied reference clock. The LOL output will remain asserted until the divided clock output frequency differs from the REFCLK frequency by less than the amount specified in Table 4. Note: LOL is not asserted during PWRDN/CAL. PLL Performance The PLL implementation used in the Si5010 is fully compliant with the jitter specifications proposed for SONET/SDH equipment by Bellcore GR-253-CORE, Issue 2, December 1995 and ITU-T G.958. Jitter Tolerance The Si5010’s tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 6. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device. Preliminary Rev. 0.31 9 S i5 01 0 Jitter Transfer Sinusoidal Input Jitter (UI p-p) S lo p e = 2 0 d B /D e c a d e 15 20 dB/Decade Slope 0.1 dB 1.5 Acceptable Range 0.15 f0 f1 f2 f3 ft Frequency F0 (Hz) F1 (Hz) OC-12 10 30 300 25 250 OC-3 10 30 300 6.5 65 SONET Data Rate F2 (Hz) Fc Frequency F3 (kHz) Ft (kHz) Figure 6. Jitter Tolerance Specification SONET D ata R ate Fc (kH z) OC-12 500 OC-3 130 Figure 7. Jitter Transfer Specification Jitter Transfer Power Down The Si5010 is fully compliant with the relevant Bellcore/ ITU specifications related to SONET/SDH jitter transfer. Jitter transfer is defined as the ratio of output signal jitter to input signal jitter as a function of jitter frequency (see Figure 7). These measurements are made with an input test signal that is degraded with sinusoidal jitter whose magnitude is defined by the mask in Figure 6. The Si5010 provides a power down pin, PWRDN/CAL, that disables the device. When the PWRDN/CAL pin is driven “high”, the positive and negative terminals of CLKOUT and DOUT are each tied to VDD through 100 Ω on-chip resistors. This feature is useful in reducing power consumption in applications that employ redundant serial channels. When PWRDN/CAL is released (set to “low”) the digital logic resets to a known initial condition, recalibrates the DSPLL, and will begin to lock to the data stream. Jitter Generation The Si5010 meets all relevant specifications for jitter generation proposed for SONET/SDH equipment. The jitter generation specification defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. The Si5010 typically generates less than 1.6 mUIRMS of jitter when presented with jitter-free input data. Note: LOL is not asserted when the device is in the power down state. Device Grounding The Si5010 uses the GND pad on the bottom of the 20-pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figures 10 and 11 for the ground (GND) pad location. Bias Generation Circuitry The Si5010 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 kΩ (1%) resistor connected between REXT and GND. 10 Preliminary Rev. 0.31 Si5010 Differential Input Circuitry Differential Output Circuitry The Si5010 provides differential inputs for both the high speed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 8. In applications where direct DC coupling is possible, the 0.1 µF capacitors may be omitted. The DIN and REFCLK input amplifiers require an input signal with a minimum differential peak-to-peak voltage listed in Table 2 on page 6. The Si5010 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with AC coupling is shown in Figure 9. In applications in which direct DC coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 6. Differential Driver Si5010 VDD 2.5 k Ω 0.1 µ F Zo = 50 Ω D IN +, REFC LK+ Zo = 50 Ω D IN –, REFC LK– 10 k Ω 0.1 µ F 2.5 k Ω 102 Ω 10 k Ω GND Figure 8. Input Termination for DIN and REFCLK (AC Coupled) Si5010 VDD VDD 50 Ω 100 Ω DOUT+, CLKOUT+ 0.1 µ F Zo = 50 Ω DOUT–, CLKOUT– 0.1 µ F Zo = 50 Ω 100 Ω VDD 50 Ω VDD Figure 9. Output Termination for DOUT and CLKOUT (AC Coupled) Preliminary Rev. 0.31 11 S i5 01 0 NC RATESEL G ND CLKO UT+ CLKO UT– Pin Descriptions: Si5010 20 19 18 17 16 REXT 1 15 PW RDN/CAL VDD 2 14 VDD G ND 3 13 DO UT+ REFCLK+ 4 12 DO UT– REFCLK– 5 11 VDD 7 8 9 10 G ND DIN+ DIN– LO L 6 VDD GND Pad Top View Figure 10. Si5010 Pin Configuration Table 8. Si5010 Pin Descriptions Pin # Pin Name 1 REXT I/O Signal Level Description External Bias Resistor. This resistor is used by onboard circuitry to establish bias currents within the device. This pin must be connected to GND through a 10 kΩ (1%) resistor. 2, 7, 11, 14 VDD 2.5 V Supply Voltage. Nominally 2.5 V. 3, 8, 18, and GND Pad GND 4, 5 REFCLK+, REFCLK– I LOL O 6 GND Supply Ground. Nominally 0.0 V. The GND pad found on the bottom of the 20-pin micro leaded package (see Figure 11) must be connected directly to supply ground. See Table 2 Differential Reference Clock. The reference clock sets the initial operating frequency used by the onboard PLL for clock and data recovery. Additionally, the reference clock is used to derive the clock output when no data is present. LVTTL Loss of Lock. This output is driven high when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 7. 9, 10 DIN+, DIN– I See Table 2 Differential Data Input. Clock and data are recovered from the differential signal present on these pins. 12 Preliminary Rev. 0.31 Si5010 Table 8. Si5010 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 12, 13 DOUT–, DOUT+ O CML PWRDN/CAL I 15 Description Differential Data Output. The data output signal is a retimed version of the data recovered from the signal present on DIN. It is phase aligned with CLKOUT and is updated on the rising edge of CLKOUT. LVTTL Power Down. To shut down the high-speed outputs and reduce power consumption, hold this pin high. For normal operation, hold this pin low. Calibration. To initiate an internal self-calibration, force a high-to-low transition on this pin. (See "PLL Self-Calibration" on page 9.) Note: This input has a weak internal pulldown. 16, 17 19 CLKOUT–, CLKOUT+ O RATESEL I CML Differential Clock Output. The output clock is recovered from the data signal present on DIN. In the absence of data, the output clock is derived from REFCLK. LVTTL Data Rate Select. This pin configures the onboard PLL for clock and data recovery at one of two user selectable data rates. See Table 7 for configuration settings. Note: This input has a weak internal pulldown. 20 NC No Connect. This pin should be tied to ground. Preliminary Rev. 0.31 13 S i5 01 0 Ordering Guide Table 9. Ordering Guide 14 Part Number Package Temperature Si5010-BM 20-pin MLP –40°C to 85°C Preliminary Rev. 0.31 Si5010 Package Outline Figure 11 illustrates the package details for the Si5010. Table 10 lists the values for the dimensions shown in the illustration. 2X TO P VIEW 0 .2 5 C BO TTO M VIEW A D A 10 D /2 0 .0 5 D1 C 4 4X P b A 0 .1 0 D 2 /2 A3 0 .2 5 C C A B D2 A2 2X N M R A1 D 1 /2 8. N B 4X P 5 6 E 1 /2 1 0 .5 0 D IA . 1 E /2 2 2 E1 3 4X Q E (N e-1 )X e 3 E2 REF. E 2 /2 L 0 .2 0 C B 2X 0 B 0 .2 0 C e C A S E A T IN G PLANE 2X A1 b REF. 11 NO TES: 4 C CL 1. C 2. CL SEC TIO N "C -C " SCALE: NONE e (N d -1 )X e e DIE THICKNESS ALLO W ABLE IS 0.305mm MA XIMUM(.012 INCHES MAXIMUM ) DIMENSIO NING & TO LERANCES CO NFO RM T O ASME Y14.5M. - 1994. 3. N IS THE NUMB ER O F TERMINALS. Nd IS THE NUM BER O F TERMINALS IN X-DIR ECTIO N & Ne IS THE NUM BER O F TERMINALS IN Y-DIR ECTIO N. 4. DIMENSIO N b A PPLIES TO PLATED TERMINA L AND IS MEASURED BETW EEN 0.20 AND 0.25mm FRO M TERMINA L TIP. T E R M IN A L T IP FO R O D D TER M IN AL/SID E 5. THE PIN #1 IDE NTIFIER MUST BE EXISTED O N THE TO P SURFACE O F THE PACKAG E BY U SING INDENTATIO N MARK O R O THER FEATURE O F PACKA G E BO DY. FO R EVEN TER M IN AL/SID E 6. EXACT SHAPE AND SIZE O F THIS FEATURE IS O PTIO NAL. 7. ALL DIMENSIO N S ARE IN MILLIMETERS. 8. THE SHAPE SH O W N O N FO UR CO RNERS AR E NO T ACTUAL I/O . 9. PACKAG E W AR PAG E MAX 0.05mm. 10. APPLIED FO R E XPO SED PAD AND TERMINAL S. EXCLUDE EMB EDDING PART O F EXPO SED PAD FRO M MEA SURING . 11. APPLIED O NLY FO R TERMINALS. Figure 11. 20-pin Micro Leaded Package (MLP) Table 10. Package Diagram Dimensions Symbol A A1 A2 A3 b D D1 D2 e E Millimeters Min — 0.00 — 0.23 1.95 Nom 0.85 0.01 0.65 0.20 REF 0.28 4.00 BSC 3.75 BSC 2.10 0.50 BSC 4.00 BSC Symbol Max 1.00 0.05 0.80 0.35 2.25 Millimeters Min E1 E2 N Nd Ne L P Q R θ Preliminary Rev. 0.31 1.95 0.50 0.24 0.30 0.13 — Nom 3.75 BSC 2.10 20 5 5 0.60 0.42 0.40 0.17 — Max 2.25 0.75 0.60 0.65 0.23 12° 15 S i5 01 0 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. 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