Ordering number : ENA1659 LC88F52H0A CMOS IC FROM 512K byte, RAM 24K byte on-chip http://onsemi.com 16-bit 1-chip Microcontroller Overview The LC88F52H0A is a 16-bit microcomputer that, centered around an Xstromy16 CPU, integrates on a single chip a number of hardware features such as 512K-byte flash ROM (onboard programmable), 24K-byte RAM, eight 16-bit timers, a base timer serving as a time-of-day clock,, a real time clock, two synchronous SIO interfaces with automatic transmission capability, two single master I2C/synchronous SIO interface, a slave I2C/synchronous SIO interface, four asynchronous SIO (UART) interfaces, a 16-channel 12-bit resolution AD converter, 8bit resolution DA converter, four multifrequency 12-bit PWM modules, a watchdog timer, a system clock frequency divider, a 59-source (32 modules) 14-vector interrupt feature, and on-chip debugger feature. Features Xstromy16 CPU • 4G-byte address space • General-purpose registers: 16 bits × 16registers Flash ROM • Capable of onboard programming with a wide range of voltage levels (3.0 to 5.5V). • Block-erasable in 512 or 1K byte units. • Data written in 2-byte units. • 524288 × 8 bits RAM • 24576 × 8 bits * This product is licensed from Silicon Storage Technology, Inc. (USA). Semiconductor Components Industries, LLC, 2013 May, 2013 Ver.1.03 33110HKIM 20100312-S00006 No.A1659-1/38 LC88F52H0A Minimum instruction cycle time (tCYC) • 83.3 ns (12MHz) VDD = 4.5 to 5.5V • 107 ns (9.3MHz) VDD = 3.0 to 5.5V • 500 ns (2MHz) VDD = 2.5 to 5.5V Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units : 86 (P0n P1n, P2n, P3n, P4n, P5n, P6n, P7n, PAn PB0 to PB6, PC2, PD0 to PD5) • Oscillation/normal withstand voltage I/O ports : 4 (PC0, PC1, PC3, PC4) • Reset pins : 1 (RESB) • TEST pins : 1 (TEST) • Power pins : 8 (VSS1 to 4, VDD1 to 4) Timers • Timer 0: 16-bit timer that supports PWM/toggle outputs 1) 5-bit prescaler 2) 8-bit PWM × 2, 8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 1: 16-bit timer with capture registers 1) 5-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 2: 16-bit timer with capture registers 1) 4-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, OSC0, OSC1, and external events • Timer 3: 16-bit timer that supports PWM/toggle outputs 1) 8-bit prescaler 2) 8-bit timer × 2ch or 8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and external events • Timer 4: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0 • Timer 5: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0 • Timer 6: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 1 • Timer 7: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 1 * Prescaler 0 and 1 are consisted of 4 bits and can choose their clock source from OSC0 or OSC1. • Base timer 1) Clock may be selected from OSC0 (32.768kHz crystal oscillator) and frequency-divided output of system clock. 2) Interrupts can be generated in 7 timing schemes. Real time clock 1) Calender with Jan. 1, 2000 to Dec.31, 2799 including automatic leap year calculation function. 2) Consisted of Independent second- minute-hour-day-month-year-century counters. 3) Programmable count-clock calibration function. No.A1659-2/38 LC88F52H0A Serial interfaces • SIO0: 8-bit synchronous SIO 1) LSB first/MSB first mode selectable 2) Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) 3) Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks) 4) Continuous/automatic data transmission (9- to 32768-bit units specifiable) 5) Interval function (intervals specifiable in 0 to 64 tSCK units) 6) Wakeup function • SIO1: 8-bit synchronous SIO 1) LSB first/MSB first mode selectable 2) Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) 3) Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks) 4) Continuous/automatic data transmission (9- to 32768-bit units specifiable) 5) Interval function (intervals specifiable in 0 to 64 tSCK units) 6) Wakeup function • SMIIC0: Single master I2C/8-bit synchronous SIO Mode 0: Single-master mode communication Mode 1: Synchronous 8-bit serial I/O (MSB first) • SMIIC1: Single master I2C/8-bit synchronous SIO Mode 0: Single-master mode communication Mode 1: Synchronous 8-bit serial I/O (MSB first) • SLIIC0: Slave I2C/8-bit synchronous SIO Mode 0: I2C slave mode communication Mode 1: Synchronous 8-bit serial I/O (MSB first) Note: usable only with the external clock source • UART0 1) Data length : 8 bits (LSB first) 2) Start bits : 1 bit 3) Stop bits : 1 bit 4) Parity bits : None/even parity/odd parity 5) Transfer rate : 4/8 cycle 6) Baudrate source clock : P07 input signal used as a 1 cycle signal (T0PWMH can be used as a clock source) or Timer 4 cycle. 7) Full duplex communication Note: The “cycle” refers to one period of the baudrate clock source. • UART2 1) Data length : 8 bits (LSB first) 2) Start bits : 1 bit 3) Stop bits : 1/2 bit 4) Parity bits : None/even parity/odd parity 5) Transfer rate : 8 to 4096 cycle 6) Baudrate source clock : System clock/OSC0/OSC1/P26 input signal 7) Wakeup function 8) Full duplex communication Note: The “cycle” refers to one period of the baudrate clock source. • UART3 1) Data length : 8 bits (LSB first) 2) Start bits : 1 bit 3) Stop bits : 1/2 bit 4) Parity bits : None/even parity/odd parity 5) Transfer rate : 8 to 4096 cycle 6) Baudrate source clock: System clock/OSC0/OSC1/P36 input signal 7) Wakeup function 8) Full duplex communication Note: The “cycle” refers to one period of the baudrate clock source. No.A1659-3/38 LC88F52H0A • UART4 1) Data length : 8 bits (LSB first) 2) Start bits : 1 bit 3) Stop bits : 1/2 bit 4) Parity bits : None/even parity/odd parity 5) Transfer rate : 8 to 4096 cycle 6) Baudrate source clock: System clock/OSC0/OSC1/P37 input signal 7) Wakeup function 8) Full duplex communication Note: The “cycle” refers to one period of the baudrate clock source. AD converter 1) 12/8 bits resolution selectable 2) Analog input: 16 channels 3) Comparator mode 4) Automatic reference voltage generation DA converter 1) 8 bits resolution 2) 2 converters built-in 3) Able to choose output pins PWM • PWM0: Multifrequency 12-bit PWM × 2 channels (PWM00 and PWM01) 1) 2-channel pairs controlled independently of one another 2) Clock source selectable from system clock or OSC1 3) 8-bit prescaler: TPWMR0=(prescaler value + 1) × clock period 4) 8-bit fundamental wave PWM generator circuit + 4-bit additional pulse generator circuit 5) Fundamental wave PWM mode Fundamental wave period: 16 TPWMR0 to 256 TPWMR0 High pulse width : 0 to (Fundamental wave period - TPWMR0) 6) Fundamental wave + additional pulse mode Fundamental wave period: 16 TPWMR0 to 256 TPWMR0 Overall period : Fundamental wave period × 16 High pulse width : 0 to (Fundamental wave period - TPWMR0) • PWM1: Multifrequency 12-bit PWM × 2 channels (PWM10 and PWM11) 1) 2-channel pairs controlled independently of one another 2) Clock source selectable from system clock or OSC1 3) 8-bit prescaler: TPWMR1=(prescaler value + 1) × clock period 4) 8-bit fundamental wave PWM generator circuit + 4-bit additional pulse generator circuit 5) Fundamental wave PWM mode Fundamental wave period: 16 TPWMR1 to 256 TPWMR1 High pulse width : 0 to (Fundamental wave period - TPWMR1) 6) Fundamental wave + additional pulse mode Fundamental wave period: 16 TPWMR1 to 256 TPWMR1 Overall period : Fundamental wave period × 16 High pulse width : 0 to(Fundamental wave period - TPWMR1) Watchdog timer 1) Driven by the base timer + internal watchdog timer dedicated counter 2) Interrupt or reset mode selectable No.A1659-4/38 LC88F52H0A Interrupts (peripheral function) • 59 sources (32 modules), 14 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Interrupt Source 1 08000H Watchdog timer (1) 2 08004H Base timer (2) 3 08008H Timer 0 (2) 4 0800CH INT0 (1) 5 08014H INT1 (1) 6 08018H INT2 (1)/timer 1 (2)/UART2 (4) 7 0801CH INT3 (1)/timer 2 (4)/SMIIC0 (1)/SLIIC1 (1) 8 08020H INT4 (1)/timer 3 (2) 9 08024H INT5 (1)/timer 4 (1)/SIO1 (2) 10 0802CH PWM0 (1)/SMIIC1(1) 11 08030H ADC (1)/timer 5 (1) 12 08034H INT6 (1)/timer 6 (1)/UART 3 (4) 13 08038H INT7 (1)/SIO0 (2)/SIO0(2)/USRT4 (4) 14 0803CH Port 0 (3)/Port 5 (8)/RTC (1) • 3 priority levels selectable. • Of interrupts of the same level, the one with the smallest vector address takes precedence. • A number enclosed in parentheses denotes the number of sources. Subroutine Stack: 24K-byte RAM area • Subroutine calls that automatically save PSW, interrupt vector calls: 6 bytes • Subroutine calls that do not automatically save PSW: 4 bytes Multiplication/division instructions • 16 bits × 16 bits (18 tCYC execution time) • 16 bits ÷ 16 bits (18 to 19 tCYC execution time) • 32 bits ÷ 16 bits (18 to 19 tCYC execution time) Oscillator circuits • RC oscillator circuit (internal): For system clock • CF oscillator circuit (built-in Rf circuit): For system clock (OSC1) • VCO oscillator circuit: For system clock (OSC1) • Crystal oscillator circuit (built-in Rf circuit): For low-speed system clock (OSC0) • SLRC oscillator circuit (internal): For system clock (In the case of exception processing) System clock divider function • Can run on low current. • 1/1 to 1/128 of the system clock frequency can be set. No.A1659-5/38 LC88F52H0A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Released by a system reset or occurrence of an interrupt. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) OSC1, RC and OSC0 oscillators automatically stop. 2) There are the six ways of releasing the HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established at port 5 (5) Having an interrupt established at SIO0 or SIO1 (6) Having an interrupt established at UART2, UART3 or UART4 • HOLDX mode: Suspends instruction execution and the operation of the peripheral circuits except those which run on OSC0. 1) OSC1 and RC oscillations automatically stop. 2) OSC0 maintains the state that is established when the HOLDX mode is entered. 3) There are seven ways of releasing the HOLDX mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established at port 5 (5) Having an interrupt source established at the base timer circuit (6) Having an interrupt established at SIO0 or SIO1 (7) Having an interrupt established at UART2, UART3 or UATR4 . On-chip debugger function • Supports software debugging with the IC mounted on the target board. • Supports source line debugging and tracing functions, and breakpoint setting and real time display. • Single-wire communication Package Form • TQFP100(14×14): Lead-free and halogen-free type Development Tools • On-chip debugger: EOCUIF1 + LC88F52H0A Programming board Package Programming Board TQFP100 (14 × 14) W88F52TQ Flash Programming Manufacturer Model Name Supported Version Device Flash Support Group (single) AF9708/09/09B/09C Revision: After Rev.03.32D 88F512SN AF9723/23B Flash Support Group (Gang) AF9833 Our company SKK/SKK Type-B Application Version After 1.06 Chip Data Version After 2.22 LC88F52H0A No.A1659-6/38 LC88F52H0A Package Dimensions unit : mm (typ) 3274 75 0.5 16.0 14.0 51 50 100 26 14.0 16.0 76 1 0.5 0.2 25 0.125 1.2max 0.1 (1.0) (1.0) SANYO : TQFP100(14X14) No.A1659-7/38 LC88F52H0A PB5/SM1DA PB4/SM1CK PB3/U4TX PB2/U4RX PB1/PWM11 PB0/PWM10 P37/T7O P36/T6O P35/U3TX P34/U3RX P33/INT3 P32/INT2 P31/INT1 P30/INT0 P07/T0PWMH/U0BRG P06/T0PWML P05/P05INT P04/P04INT P03/P0INT P02/P0INT P01/P0INT P00/P0INT VSS3 VDD3 P40/INT6 Pin Assignment 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 LC88F52H0A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P41/INT7 P42 P43/SO1 P44/SI1/SB1 P45/SCK1 P46/PWM00 P47/PWM01 P27 P26/T5O P25/T4O P24/SM0DO P23/SM0DA P22/SM0CK VDD2 VSS2 P21/INT5 P20/INT4 PD5/DA22 PD4/DA21 PD3/DA20 PD2/DA02 PD1/DA01 PD0/DA00 P17/U2TX P16/U2RX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/U0TX P14/T3OL/U0RX P15/T3OH 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P55/P5INT5 P56/P5INT6 P57/P5INT7 TEST RESB PC0/XT1 PC1/XT2 VSS1 PC3/CF1 PC4/VCOT/CF2 VDD1 PB6/SM1DO P70/AN8 P71/AN9 P72/AN10 P73/AN11 P74/AN12 P75/AN13 P76/AN14 P77/AN15 VSS4 VDD4 PA0 PA1 PA2 PA3 PA4/SL0CK PA5/SL0DA PA6/SL0DO PA7 PC2/FILT P50/P5INT0 P51/P5INT1 P52/P5INT2 P53/P5INT3 P54/P5INT4 Top view TQFP100 (14×14) (Lead-free and halogen-free type) No.A1659-8/38 LC88F52H0A System Block Diagram Base timer Watchdog timer FLASH ROM Xstromy16 CPU Timer 0 RAM Timer 1 On-chip debugger Timer 2 Port 0 PLL Timer 3 Port 1 Port 2 Timer 5 CF RC Port 3 X’tal Timer 6 Port 4 Low speed RC Clock generator VCO Timer 4 Timer 7 Port 5 SIO0 Port 6 SIO1 Port 7 SMIIC0 Port A SMIIC1 Port B SLIIC0 Port C UART0 Port D UART2 INT0 to INT7 UART3 AD UART4 DA PWM0 RTC PWM1 No.A1659-9/38 LC88F52H0A Pin Description Pin Name I/O Description VSS1, VSS2, VSS3, VSS4 - - Power sources VDD1, VDD2, VDD3, VDD4 - + Power sources Port 0 I/O • 8-bit I/O port • I/O specifiable in 1-bit units P00 to P07 • Pull-up resistors can be turned on and off in 1 bit units • HOLD release input (P00 to P03, P04, P05) • Port 0 interrupt input (P00 to P03, P04, P05) • Pin functions P06: Timer 0L output P07: Timer 0L output/UART0 clock input Port 1 I/O • 8-bit I/O port • I/O specifiable in 1-bit units P10 to P17 • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P10: SIO0 data output P11: SIO0 data input/pulse input/output P12: SIO0 clock input/output P13: UART0 transmit P14: Timer 3L output/UART0 receive P15: Timer 3H output P16: UART2 receive P17: UART2 transmit Port 2 I/O • 8-bit I/O port • I/O specifiable in 1-bit units P20 to P27 • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P20: INT4 input/HOLD release input/timer 3 event input/timer 2L capture input/timer 2H capture input P21: INT5 input/HOLD release input/timer 3 event input/timer 2L capture input/timer 2H capture input P22: SMIIC0 clock input/output P23: SMIIC0 bus input/output/data input P24: SMIIC0 data output (used in 3-wire SIO mode) P25: Timer 4 output P26: Timer 5 output Interrupt acknowledge type INT4, INT5: H level, L level, H edge, L edge, both edges Port 3 P30 to P37 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P30: INT0 input/HOLD release/timer 2L capture input P31: INT1 input/HOLD release/timer 2H capture input P32: INT2 input/HOLD release/timer 2 event input/timer 2L capture input P33: INT3 input/HOLD release/timer 2 event input/timer 2H capture input P34: UART3 receive P35: UART3 transmit P36: Timer 6 output P37: Timer 7 output Interrupt acknowledge type INT0 to INT3: H level, L level, H edge, L edge, both edges Continued on next page. No.A1659-10/38 LC88F52H0A Continued from preceding page. Pin Name Port 4 I/O I/O Description • 8-bit I/O port • I/O specifiable in 1-bit units P40 to P47 • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P40: INT6 input/HOLD release input P41: INT7 input/HOLD release input P43: SIO1 data output P44: SIO1 data input/bus input/output P45: SIO1 clock input/output P46: PWM00 output P47: PWM01 output Interrupt acknowledge type INT6, INT7: H level, L level, H edge, L edge, both edges Port 6 I/O • 8-bit I/O port • I/O specifiable in 1-bit units P60 to P67 • Pull-up resistors can be turned on and off in 1 bit units • Pin functions AN0 (P60) to AN7 (P67): AD converter input port Port 7 I/O • 8-bit I/O port • I/O specifiable in 1-bit units P70 to P77 • Pull-up resistors can be turned on and off in 1 bit units • Pin functions AN8 (P70) to AN15 (P77): AD converter input port Port A I/O • 8-bit I/O port • I/O specifiable in 1-bit units PA0 to PA7 • Pull-up resistors can be turned on and off in 1 bit units • Multiplexed pin functions PA4: SLIIC0 clock input PA5: SLIIC0 bus input/output/data input PA6: SLIIC0 data output (used in 3-wire SIO mode) Port B I/O • 7-bit I/O port • I/O specifiable in 1-bit units PB0 to PB6 • Pull-up resistors can be turned on and off in 1 bit units • Multiplexed pin functions PB0: PWM10 output PB1: PWM11 output PB2: UART4 receive PB3: UART4 transmit PB4: SMIIC1 clock input/output PB5: SMIIC1 bus input/output/data input PB6: SMIIC1 data output (used in 3-wire SIO mode) Port C I/O • 5-bit I/O port • I/O specifiable in 1-bit units PC0 to PC4 • Pull-up resistors can be turned on and off in 1 bit units (PC2) • Pin functions PC0: 32.768 kHz crystal oscillator input PC1: 32.768 kHz crystal oscillator output PC2: FILT PC3: Ceramic oscillator input PC4: Ceramic oscillator output/VCO output Port D I/O • 6-bit I/O port • I/O specifiable in 1-bit units PD0 to PD5 • Pull-up resistors can be turned on and off in 1 bit units • Multiplexed pin functions PD0: DA00 output PD1: DA01 output PD2: DA02 output PD3: DA10 output PD4: DA11 output PD5: DA12 output TEST I/O • TEST pin • Used to communicate with on-chip debugger. • Connects an external 100kΩ pull-down resistor. RESB I Reset pin No.A1659-11/38 LC88F52H0A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 Option Selected in Output Type Units of 1 bit Pull-up Resistor CMOS Programmable P10 to P17 Able to program special functions’ output type from CMOS P20 to P27 output or N-channel open drain P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 PA0 to PA7 PB0 to PB6 P60 to P67 CMOS P70 to p77 PD0 to PD5 PC2 PC0 - N-channel open drain (32.768kHz crystal oscillator input) None PC1 - N-channel open drain (32.768kHz crystal oscillator output) None PC3 - CMOS (ceramic oscillator input) None PC4 - CMOS (ceramic oscillator output) None * Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time. Be sure to electrically short the VSS1, VSS2, VSS3 and VSS4 pins. Example 1: When data is being backed up in the HOLD mode, the H level signals to the output ports are fed by the backup capacitors. LSI VDD1 Power supply For buckup VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 Example 2: When data is being backed up in the HOLD mode, the H level output at any ports is not sustained and is unpredictable. LSI VDD1 Power supply For buckup VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 No.A1659-12/38 LC88F52H0A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Maximum supply Symbol Applicable Pin /Remarks VDD max VDD1, VDD2, VDD3, Input voltage VI(1) VDD4 RESB Input/output VIO(1) Ports 0, 1, 2 voltage voltage Specification Conditions VDD[V] VDD1=VDD2=VDD3= VDD4 Ports 3, 4, 5 min typ -0.3 +6.5 -0.3 VDD +0.3 unit V VDD +0.3 -0.3 Ports 6, 7 max Ports A, B, C, D Peak output IOPH(1) current Ports 0, 1, 2, 3 CMOS output selected P40 to P45 Per applicable pin Ports 7, A, D -10 PB2 to PB6 IOPH(2) P46, P47 Per applicable pin PB0, PB1 IOPH(3) Port 5, 6 Per applicable pin PC0 to PC4 Ports 0, 1, 2, 3 CMOS output selected output P40 to P45 Per applicable pin current Ports 5, 6, 7, A (Note 1-1) PB2 to PB6 Average IOMH(1) -20 -5 -7.5 Ports D IOMH(2) P46, P47 Per applicable pin PB0, PB1 IOMH(3) Port 5, 6 Per applicable pin High level output current PC0 to PC4 Total output ΣIOAH(1) current ΣIOAH(2) Pprts 5 Total of currents at PC0 to PC4 applicable pins Port 6 Total of currents at applicable pins ΣIOAH(3) ΣIOAH(4) ΣIOAH(5) Port 5, 6 Total of currents at PC0 to PC4 applicable pins Ports 1,D1 Total of currents at P20 to P21 applicable pins P22 to P27 Total of currents at applicable pins ΣIOAH(6) Ports 1, 2, D Total of currents at applicable pins ΣIOAH(7) Ports 4 Total of currents at applicable pins ΣIOAH(8) Ports 0, 3 Total of currents at applicable pins ΣIOAH(9) Ports 0, 3, 4 Total of currents at applicable pins ΣIOAH(10) Ports B, 7 Total of currents at applicable pins ΣIOAH(11) Ports A Total of currents at applicable pins ΣIOAH(12) Ports 7, A, B Total of currents at applicable pins -10 -3 -15 -15 mA -20 -25 -25 -45 -25 -25 -45 -25 -25 -45 Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms. Continued on next page. . No.A1659-13/38 LC88F52H0A Continued from preceding page. Parameter Peak output Symbol IOPL(1) current Applicable Pin /Remarks Ports 0, 1, 3, 4 Specification Conditions VDD[V] min typ max unit Per applicable pin Ports 7, A, B P20, P21, P24 to P27 20 PA0 to PA4, PA6, PA7 PB0 to PB4, PB6, PB7 IOPL(2) P22, P23 Per applicable pin PA4, PA5 25 PB4, PB5 IOPL(3) Ports 5, 6 Per applicable pin 10 PC0 to PC4 Average IOML(1) Ports 0, 1, 3, 4 output current Ports 7, A, B (Note 1-1) P20, P21, P24 to P27 Per applicable pin 15 PA0 to PA4, PA6, PA7 PB0 to PB4, PB6, PB7 IOML(2) P22, P23 Per applicable pin PA4, PA5 20 Low level output current PB4, PB5 IOML(3) Ports 5, 6 Per applicable pin 7.5 PC0 to PC4 Total output ΣIOAL(1) Ports 5 Total of currents at PC0 to PC2 applicable pins ΣIOAL(2) Port 6 Total of currents at PC3 to PC4 applicable pins ΣIOAL(3) Port 5, 6 Total of currents at PC0 to PC4 applicable pins Ports 1, D Total of currents at P20, P21 applicable pins current ΣIOAL(4) ΣIOAL(5) P22 to P27 15 mA 15 20 45 Total of currents at 45 applicable pins ΣIOAL(6) Ports 1, 2, D Total of currents at 80 applicable pins ΣIOAL(7) Port 4 Total of currents at 45 applicable pins ΣIOAL(8) Port 0, 3 Total of currents at 45 applicable pins ΣIOAL(9) Port 0, 3, 4 Total of currents at 80 applicable pins ΣIOAL(10) Port 7, B Total of currents at 45 applicable pins ΣIOAL(11) Port A Total of currents at 45 applicable pins ΣIOAL(12) Port 7, A, B Total of currents at 80 applicable pins Allowable power Pd max TQFP100(14×14) Ta=-40 to +85°C 250 dissipation Operating ambient Topr temperature Storage ambient temperature Tstg -40 +85 -55 +125 mW °C Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. No.A1659-14/38 LC88F52H0A Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Operating Applicable Symbol VDD(1) Pin/Remarks VDD1=VDD2=VDD3 supply voltage (Note 2-1) Memory VHD VDD1=VDD2=VDD3 sustaining Specification Conditions VDD[V] min typ max unit 0.081μs≤tCYC≤66μs 4.0 5.5 0.103μs≤tCYC≤66μs 3.0 5.5 0.490μs≤tCYC≤66μs 2.5 5.5 2.0 5.5 RAM and register contents sustained in HOLD mode supply voltage High level input VIH(1) voltage Ports 0, 1, 2, 3, 4 2.5 to 5.5 Port 5, A, B VIH(2) Ports 6, 7, PC2 VIH(3) RESB PC0, PC1, PC3, PC4 VIH(4) VIL(1) voltage When ports 1, 2, 3, 4, 5, A and port B, VIL(2) PnFSAn=0 Ports 0, 6, 7, PC2 VIL(3) When ports 1, 2, 3, 4, 5, A and port B, VIL(4) PnFSAn=1 VIL(5) CF1, RESB PC0, PC1, PC3, PC4 VIL(6) P22, P23, PA4, PA5, PB4, PB5 I2C side Instruction tCYC frequency FEXCF(1) CF1 2.5 to 5.5 0.3VDD +0.7 VDD 2.5 to 5.5 0.75VDD VDD 2.5 to 5.5 0.7VDD VDD 4.0 to 5.5 VSS 2.5 to 4.0 VSS 4.0 to 5.5 VSS 2.5 to 4.0 VSS 0.2VDD 2.5 to 5.5 VSS 0.25VDD 2.5 to 5.5 VSS 0.3VDD 0.1VDD +0.4 0.2VDD 0.15VDD +0.4 4.5 to 5.5 0.081 66 0.122 66 2.5 to 5.5 0.490 66 • CF2 pin open 4.5 to 5.5 0.1 12 • System clock frequency 3.0 to 5.5 0.1 8.3 2.5 to 5.5 0.1 2 • CF2 pin open 4.5 to 5.5 0.2 24 • System clock frequency 3.0 to 5.5 0.2 18.6 2.5 to 5.5 0.2 4 (Note 2-2) system clock VDD 2.8 to 5.5 cycle time External +0.7 V P22, P23, PA4, PA5, PB4, PB5 I2C side Low level input 0.3VDD μs division ratio=1/1 • External system clock MHz DUTY50±5% division ratio=1/2 Note 2-1: VDD≥3.0V must be maintained when making onboard programming into flash ROM. Note 2-2: Relationship between tCYC and oscillation frequency is 1/FmCF when frequency division ratio is 1/1 and 2/FmCF when the ratio is 1/2. Continued on next page. No.A1659-15/38 LC88F52H0A Continued from preceding page Parameter Oscillation Symbol FmCF(1) frequency Conditions VDD[V] PC3 (CF1), 12MHz ceramic oscillator PC4 (CF2) mode range (Note 2-3) Specification Applicable Pin /Remarks min typ max 4.5 to 5.5 12 3.0 to 5.5 8 unit See Fig. 1. FmCF(2) PC3(CF1), 8MHz ceramic oscillator PC4(CF2) mode See Fig. 1. FmCF(3) PC3(CF1), 4MHz ceramic oscillator PC4(CF2) mode MHz 2.5 to 5.5 4 See Fig. 1. FmRC Internal RC oscillation FmSLRC Internal low-speed RC oscillation FsX'tal XT1, XT2 2.5 to 5.5 0.5 1.0 2.0 2.5 to 5.5 18 30 45 kHz 32.768kHz crystal oscillator mode 2.5 to 5.5 32.768 See Fig. 2. FmVCO(1) VCO oscillator When setting VC3=1 When SELDIV=0 or 1 2.5 to 3.8 5.0 9.0 2.5 to 3.8 5.0 12 3.6 to 5.5 5.0 9.0 3.6 to 5.5 9.0 12 See Fig. 9. FmVCO(2) VCO oscillator When setting VC3=0 When SELDIV=2 or 3 See Fig. 9. FmVCO(3) VCO oscillator When setting VC3=1 When SELDIV=0 or 1 MHz See Fig. 9. FmVCO(4) VCO oscillator When setting VC3=0 When SELDIV=2 or 3 See Fig. 9. FmVCO(5) VCO oscillator When OSC0=32.768KHz SELDIV setting range=0 to 3 2.5 to 5.5 Note 2-4 SELDLY setting range=0 to 3 Note 2-3: See Tables 1 and 2 for oscillator constant values. Note 2-4: VCO oscillation frequency = 0.032768×(56×(SELDIV+3)+SELDLY) No.A1659-16/38 LC88F52H0A Electrical Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter High level input IIH(1) current IIL(1) current voltage VOH(1) VOH(2) Output disabled Ports 3, 4, 5 Pull-up resistor off Ports 6, 7 VIN=VDD (Including output Tr. off leakage RESB current) Ports 0, 1, 2 Output disabled Ports 3, 4, 5 Pull-up resistor off Ports 6, 7 VIN=VSS (Including output Tr. off leakage min typ 2.5 to 5.5 2.5 to 5.5 -1 current) IOH=-1.0mA 4.5 to 5.5 VDD-1 IOH=-0.4mA 3.0 to 5.5 VDD-0.4 P40 to P45 VOH(3) PB2 to PB6 IOH=-0.2mA 2.5 to 5.5 VDD-0.4 VOH(4) Port 5, 6 IOH=-0.4mA 3.0 to 5.5 VDD-0.4 VOH(5) PC2 IOH=-0.2mA 2.5 to 5.5 VDD-0.4 VOH(6) P46, P47 IOH=-10mA 4.5 to 5.5 VDD-1.5 VOH(7) PB0, PB1 IOH=-1.6mA 3.0 to 5.5 VDD-0.4 IOH=-1.0mA 2.5 to 5.5 VDD-0.4 VOH(9) PC0, PC1, IOH=-1.0mA 3.0 to 5.5 VDD-0.4 VOH(10) PC3, PC4, IOH=-0.4mA 2.5 to 5.5 VDD-0.4 VOL(1) Ports 0, 1, 3, 4 IOL=10mA voltage Ports 7, D VOL(2) P20 to P21, P24 to P27 IOL=1.6mA unit μA RESB Ports 4, A, D max 1 Ports 0, 1, 2, 3 VOH(8) Low level output VDD[V] Ports 0, 1, 2 Ports A, B, C, D High level output Conditions Remarks Ports A, B, C, D Low level input Specification Applicable/ Symbol 4.5 to 5.5 1.5 3.0 to 5.5 0.4 2.5 to 5.5 0.4 V PA0 to PA3 VOL(3) PA6 to PA7 IOL=1.0mA PB0 to PB3, PB6 VOL(4) P22, P23, IOL=11mA 4.5 to 5.5 1.5 VOL(5) PA4, PA5, IOL=3.0mA 3.0 to 5.5 0.4 IOL=1.3mA 2.5 to 5.5 0.4 0.4 VOL(6) Pull-up resistor PB4, PB5 VOL(7) Ports 5, 6 IOL=1.6mA 3.0 to 5.5 VOL(8) PC2 IOL=1.0mA 2.5 to 5.5 0.4 VOL(9) PC0, PC1, IOL=1.0mA 3.0 to 5.5 0.4 VOL(10) PC3, PC4 IOL=0.4mA 2.5 to 5.5 Rpu(1) Ports 0, 1, 2, 3 VOH=0.9VDD 4.5 to 5.5 15 35 80 2.5 to 4.5 18 55 150 0.4 kΩ Ports 4, 5, 6, 7 Rpu(2) Hysteresis VHYS voltage Ports A, B, D, PC2 RESB When ports 1, 2, 3, 4, A 2.5 to 5.5 0.1VDD V 2.5 to 5.5 10 pF PnFSAn=1 Pin capacitance CP All pins Pins other than that under test VIN=VSS f=1MHz Ta=25°C No.A1659-17/38 LC88F52H0A Serial I/O Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Serial I/O Characteristics (Wakeup Function Disabled) (Note 4-1-1) Parameter Symbol Period tSCK(1) Low level tSCKL(1) Specification Applicable Conditions Pin/Remarks SCK0(P12) VDD[V] • See Fig. 6. tSCKHA(1) Input clock tSCKH(1) pulse width typ max unit 4 2 pulse width High level min 2 • Automatic communication mode • See Fig. 6. 6 2.5 to 5.5 tCYC • Automatic communication tSCKHBSY(1a) mode 23 • See Fig. 6. • Mode other than automatic tSCKHBSY(1b) communication mode 4 Serial clock • See Fig. 6. Period tSCK(2) SCK0(P12) • CMOS output selected 4 • See Fig. 6. Low level tSCKL(2) 1/2 pulse width High level tSCK tSCKH(2) 1/2 pulse width • Automatic communication Output clock tSCKHA(2) mode • CMOS output selected 2.5 to 5.5 6 • See Fig. 6. • Automatic communication tSCKHBSY(2a) mode 4 • CMOS output selected 23 tCYC • See Fig. 6. • Mode other than automatic tSCKHBSY(2b) communication mode 4 Serial input • See Fig. 6. Data setup time SI0(P11), SB0(P11) Data hold time • Specified with respect to rising • See Fig. 6. thDI(1) 0.03 edge of SIOCLK 2.5 to 5.5 0.03 Output clock Input clock Output Serial output tsDI(1) tdD0(1) delay time SO0(P10), • (Note 4-1-2) SB0(P11) 1tCYC +0.05 tdDO(2) • (Note 4-1-2) μs 2.5 to 5.5 1tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. No.A1659-18/38 LC88F52H0A SIO0 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-2-1) Input clock Serial clock Parameter Period tSCK(3) Low level tSCKL(3) SCK0 (P12) Specification Conditions VDD[V] • See Fig. 6. High level tSCKH(3) pulse width tSCKHBSY(3) Data hold time min typ max tsDI(2) unit 2 1 2.5 to 5.5 tCYC 1 2 SI0 (P11), SB0 (P11) • Specified with respect to thDI(2) 0.03 rising edge of SIOCLK • See Fig. 6. 2.5 to 5.5 0.03 Output Input clock Serial input Applicable Pin/Remarks pulse width Data setup time Serial output Symbol delay time tdD0(3) SO0 (P10), μs • (Note 4-2-2) SB0 (P11) 2.5 to 5.5 1tCYC +0.05 Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Note 4-2-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig.6. No.A1659-19/38 LC88F52H0A SIO1 Serial Input/Output Characteristics (Wakeup Function Disabled) (Note 4-3-1) Parameter Symbol Period tSCK(4) Low level tSCKL(4) Specification Applicable Conditions Pin/Remarks SCK1(P45) VDD[V] • See Fig. 6. tSCKHA(4) Input clock tSCKH(4) pulse width typ max unit 4 2 pulse width High level min 2 • Automatic communication mode • See Fig. 6. 6 2.5 to 5.5 tCYC • Automatic communication tSCKHBSY(4a) mode 23 • See Fig. 6. • Mode other than automatic tSCKHBSY(4b) communication mode 4 Serial clock • See Fig. 6. Period tSCK(5) SCK1(P45) • CMOS output selected 4 • See Fig. 6. Low level tSCKL(5) 1/2 pulse width High level tSCK tSCKH(5) 1/2 pulse width • Automatic communication Output clock tSCKHA(5) mode • CMOS output selected 2.5 to 5.5 6 • See Fig. 6. • Automatic communication tSCKHBSY(5a) mode 4 • CMOS output selected 23 tCYC • See Fig. 6. • Mode other than automatic tSCKHBSY(5b) communication mode 4 Serial input • See Fig. 6. Data setup time SI1(P44), SB1(P44) Data hold time • Specified with respect to rising • See Fig. 6. thDI(3) 0.03 edge of SIOCLK μs 2.5 to 5.5 0.03 Input clock Output tdD0(4) delay time SO1(P43), • (Note 4-3-2) SB1(P44) 1tCYC +0.05 tdDO(5) Output clock Serial output tsDI(3) • (Note 4-3-2) μs 2.5 to 5.5 1tCYC +0.05 Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. No.A1659-20/38 LC88F52H0A SIO1 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-4-1) Input clock Serial clock Parameter Period tSCK(6) Low level tSCKL(6) Specification Applicable Conditions Pin/Remarks SCK1(P45) VDD[V] min • See Fig. 6. typ 1 High level tSCKH(6) 1 pulse width tSCKHBSY(6) 2 tsDI(4) SI1(P44), SB1(P44) unit tCYC • Specified with respect to rising edge of SIOCLK • See Fig. 6. Data hold time max 2 2.5 to 5.5 pulse width Data setup time Serial input Symbol thDI(4) 0.03 2.5 to 5.5 0.03 Input clock Serial output μs Output tdD0(6) delay time SO1(P43), • (Note 4-4-2) SB1(P44) 1tCYC 2.5 to 5.5 +0.05 Note 4-4-1: These specifications are theoretical values. Add margin depending on its use. Note 4-4-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. SMIIC0 Simple SIO Mode Input/Output Characteristics Input clock Symbol Period tSCK(7) Low level tSCKL(7) Specification Applicable Conditions Pin/Remarks SM0CK(P22) VDD[V] See Fig. 6. 2.5 to 5.5 pulse width High level Period SM0CK(P22) • CMOS output selected tSCKL(8) 4 1/2 tSCK tSCKH(8) 1/2 pulse width Serial input Data setup time SM0DA(P23) • Specified with respect to rising edge of SIOCLK • See Fig. 6. Data hold time thDI(5) 0.03 2.5 to 5.5 0.03 Output delay Serial output tsDI(5) unit 2 2.5 to 5.5 pulse width High level max 2 • See Fig. 6. Low level typ tCYC tSCKH(7) tSCK(8) min 4 pulse width Output clock Serial clock Parameter time tdD0(7) SM0DO(P24), SM0DA(P23) μs • Specified with respect to falling edge of SIOCLK • Specified as interval up to time when output state starts 2.5 to 5.5 1tCYC +0.05 changing. • See Fig. 6. Note 4-5-1: These specifications are theoretical values. Add margin depending on its use. No.A1659-21/38 LC88F52H0A SMIIC0 I2C Mode Input/Output Characteristics Clock Input clock Parameter Symbol Period tSCL Low level tSCLL Specification Applicable Conditions Pin/Remarks SM0CK(P22) VDD[V] • See Fig. 8. High level Output clock SM0CK(P22) • Specified as interval up to time tSCLLx 2.5 to 5.5 pulse width High level 2.5 10 when output state starts changing. Low level 1/2 tSCL tSCLHx 1/2 pulse width SM0CK and SM0DA tsp pins input spike unit 2 pulse width tSCLx max Tfilt tSCLH Period typ 5 2.5 to 5.5 pulse width min SM0CK(P22) • See Fig. 8. SM0DA(P23) 2.5 to 5.5 1 Tfilt suppression time time between start and stop tBUF SM0CK(P22) • See Fig. 8. SM0DA(P23) Input Bus release 2.5 SM0CK(P22) • Standard clock mode SM0DA(P23) • Specified as interval up to time Output tBUFx Tfilt 2.5 to 5.5 5.5 when output state starts changing. μs • High-speed clock mode • Specified as interval up to time 1.6 when output state starts changing. Start/restart tHD;STA condition hold SM0DA(P23) • When SMIIC register control bit, I2CSHDS=0 2.0 • See Fig. 8. Input time SM0CK(P22) Tfilt • When SMIIC register control bit, 2 I CSHDS=1 • See Fig. 8. SM0CK(P22) • Standard clock mode SM0DA(P23) • Specified as interval up to time Output tHD;STAx 2.5 2.5 to 5.5 4.1 when output state starts changing. μs • High-speed clock mode • Specified as interval up to time 1.0 when output state starts changing. time tSU;STA SM0CK(P22) • See Fig. 8. SM0DA(P23) 1.0 tSU;STAx Output condition setup Input Restart SM0CK(P22) • Standard clock mode SM0DA(P23) • Specified as interval up to time 2.5 to 5.5 5.5 when output state starts changing. μs • High-speed clock mode • Specified as interval up to time Tfilt 1.6 when output state starts changing. Continued on next page. No.A1659-22/38 LC88F52H0A Continued from preceding page Parameter Symbol setup time tSU;STO Input Stop condition Specification Applicable Conditions Pin/Remarks SM0CK(P22) VDD[V] SM0DA(P23) typ max 1.0 SM0CK(P22) • Standard clock mode SM0DA(P23) • Specified as interval up to time Output tSU;STOx min unit • See Fig. 8. 2.5 to 5.5 Tfilt 4.9 when output state starts changing. μs • High-speed clock mode • Specified as interval up to time 1.1 when output state starts changing. tHD;DAT Input Data hold time Output Input Output SM0CK(P22) SM0DA(P23) • Specified as interval up to time 2.5 to 5.5 when output state starts changing. Tfilt 1 1.5 • See Fig. 8. 1 • Specified as interval up to time 2.5 to 5.5 when output state starts changing. Tfilt 1tSCL -1.5Tfilt tF Input time SM0CK(P22) 0 SM0DA(P23) tSU;DATx SM0DA pins fall SM0CK(P22) SM0DA(P23) tSU;DAT SM0CK and • See Fig. 8. SM0DA(P23) tHD;DATx Data setup time SM0CK(P22) SM0CK(P22) • See Fig. 8. SM0DA(P23) tF SM0CK (P22) SM0DA (P23) 2.5 to 5.5 • When SMIIC register control bits, 5 PSLW=1, P5V=1 Output • When SMIIC register control bits, 3 PSLW=1, P5V=0 300 20 +0.1Cb 20 +0.1Cb 250 ns 250 • SM0CK, SM0DA port output FAST mode 3 to 5.5 100 • Cb≤400pF Note 4-6-1: These specifications are theoretical values. Add margin depending on its use. Note 4-6-2: The value of Tfilt is determined by the values of the register SMIC0BRG, bits 7 and 6 (BRP1, BRP0) and the system clock frequency. BRP1 BRP0 Tfilt 0 0 tCYC×1 0 1 tCYC×2 1 0 tCYC×3 1 1 tCYC×4 Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range: 250ns ≥ Tfilt >140ns Note 4-6-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 400pF Note 4-6-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows: 250ns ≥ Tfilt >140ns BRDQ (bit5) = 1 SCL frequency setting ≤ 100kHz The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows: 250ns ≥ Tfilt >140ns BRDQ (bit5) = 0 SCL frequency setting ≤ 400kHz No.A1659-23/38 LC88F52H0A SMIIC1 Simple SIO Mode Input/Output Characteristics Input clock Symbol Period tSCK(7) Low level tSCKL(7) Specification Applicable Conditions Pin/Remarks SM1CK(PB4) VDD[V] See Fig. 6. 2.5 to 5.5 pulse width High level Period SM1CK(PB4) • CMOS output selected tSCKL(8) 4 1/2 tSCK tSCKH(8) 1/2 pulse width Serial input Data setup time tsDI(5) SM1DA(PB5) • Specified with respect to rising edge of SIOCLK • See Fig. 6. Data hold time unit 2 2.5 to 5.5 pulse width High level max 2 • See Fig. 6. Low level typ tCYC tSCKH(7) tSCK(8) min 4 pulse width Output clock Serial clock Parameter thDI(5) 0.03 2.5 to 5.5 0.03 Serial output μs Output delay time tdD0(7) SM1DO(PB6), SM1DA(PB5) • Specified with respect to falling edge of SIOCLK • Specified as interval up to time when 2.5 to 5.5 output state starts changing. 1tCYC +0.05 • See Fig. 6. Note 4-7-1: These specifications are theoretical values. Add margin depending on its use. No.A1659-24/38 LC88F52H0A SMIIC1 I2C Mode Input/Output Characteristics Clock Input clock Parameter Symbol Period tSCL Low level tSCLL Specification Applicable Conditions Pin/Remarks SM1CK(PB4) VDD[V] • See Fig. 8. High level Output clock SM1CK(PB4) • Specified as interval up to time tSCLLx 2.5 to 5.5 pulse width High level 2.5 10 when output state starts changing. Low level 1/2 tSCL tSCLHx 1/2 pulse width SM0CK and SM0DA tsp pins input spike unit 2 pulse width tSCLx max Tfilt tSCLH Period typ 5 2.5 to 5.5 pulse width min SM1CK(PB4) • See Fig. 8. SM1DA(PB5) 2.5 to 5.5 1 Tfilt suppression time time between start and stop tBUF SM1CK(PB4) • See Fig. 8. SM1DA(PB5) Input Bus release 2.5 SM1CK(PB4) • Standard clock mode SM1DA(PB5) • Specified as interval up to time Output tBUFx Tfilt 2.5 to 5.5 5.5 when output state starts changing. μs • High-speed clock mode • Specified as interval up to time 1.6 when output state starts changing. Start/restart tHD;STA condition hold SM1DA(PB5) • When SMIIC register control bit, I2CSHDS=0 2.0 • See Fig. 8. Input time SM1CK(PB4) Tfilt • When SMIIC register control bit, 2 I CSHDS=1 • See Fig. 8. SM1CK(PB4) • Standard clock mode SM1DA(PB5) • Specified as interval up to time Output tHD;STAx 2.5 2.5 to 5.5 4.1 when output state starts changing. μs • High-speed clock mode • Specified as interval up to time 1.0 when output state starts changing. time tSU;STA SM1CK(PB4) • See Fig. 8. SM1DA(PB5) 1.0 tSU;STAx Output condition setup Input Restart SM1CK(PB4) • Standard clock mode SM1DA(PB5) • Specified as interval up to time 2.5 to 5.5 5.5 when output state starts changing. μs • High-speed clock mode • Specified as interval up to time Tfilt 1.6 when output state starts changing. Continued on next page. No.A1659-25/38 LC88F52H0A Continued from preceding page Parameter Symbol setup time tSU;STO Input Stop condition Specification Applicable Conditions Pin/Remarks SM1CK(PB4) VDD[V] SM1DA(PB5) typ max 1.0 SM1CK(PB4) • Standard clock mode SM1DA(PB5) • Specified as interval up to time Output tSU;STOx min unit • See Fig. 8. 2.5 to 5.5 Tfilt 4.9 when output state starts changing. μs • High-speed clock mode • Specified as interval up to time 1.1 when output state starts changing. tHD;DAT Input Data hold time Output Input Output SM1CK(PB4) SM1DA(PB5) • Specified as interval up to time 2.5 to 5.5 when output state starts changing. Tfilt 1 1.5 • See Fig. 8. 1 • Specified as interval up to time 2.5 to 5.5 when output state starts changing. Tfilt 1tSCL -1.5Tfilt tF Input time SM1CK(PB4) 0 SM1DA(PB5) tSU;DATx SM0DA pins fall SM1CK(PB4) SM1DA(PB5) tSU;DAT SM0CK and • See Fig. 8. SM1DA(PB5) tHD;DATx Data setup time SM1CK(PB4) SM1CK(PB4) • See Fig. 8. SM1DA(PB5) tF SM1CK(PB4) SM1DA(PB5) 2.5 to 5.5 • When SMIIC register control bits 5 PSLW=1, P5V=1 Output • When SMIIC register control bits 3 PSLW=1, P5V=0 300 20 +0.1Cb 20 +0.1Cb 250 ns 250 • SM0CK, SM0DA port output FAST mode 3 to 5.5 100 • Cb≤400pF Note 4-8-1: These specifications are theoretical values. Add margin depending on its use. Note 4-8-2: The value of Tfilt is determined by the values of the register SMIC1BRG, bits 7 and 6 (BRP1, BRP0) and the system clock frequency. BRP1 BRP0 Tfilt 0 0 tCYC×1 0 1 tCYC×2 1 0 tCYC×3 1 1 tCYC×4 Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range: 250ns ≥ Tfilt > 140ns Note 4-8-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 400pF Note 4-8-4: The standard clock mode refers to a mode that is entered by configuring SMIC1BRG as follows: 250ns ≥ Tfilt > 140ns BRDQ (bit5) = 1 SCL frequency setting ≤ 100kHz The high-speed clock mode refers to a mode that is entered by configuring SMIC1BRG as follows: 250ns ≥ Tfilt > 140ns BRDQ (bit5) = 0 SCL frequency setting ≤ 400kHz No.A1659-26/38 LC88F52H0A SLIIC0 Simple SIO Mode Input/Output Characteristics Input clock Serial clock Parameter Symbol Period tSCK(9) Low level tSCKL(9) Specification Applicable Conditions Pin/Remarks SL0CK(PA4) VDD[V] See Fig. 6. High level tSCKH(9) Serial input tsDI(7) SL0DA(PA5) unit tCYC 2 • Specified with respect to rising edge of SIOCLK • See Fig. 6. Data hold time max 2 pulse width Data setup time typ 4 2.5 to 5.5 pulse width min thDI(7) 0.03 2.5 to 5.5 0.03 Serial output μs Output delay time tdD0(9) SL0DO(PA6), SL0DA(PA5) • Specified with respect to falling edge of SIOCLK • Specified as interval up to time 2.5 to 5.5 when output state starts changing. 1tCYC +0.05 • See Fig. 6. Note 4-9-1: These specifications are theoretical values. Add margin depending on its use. No.A1659-27/38 LC88F52H0A SLIIC1 I2C Mode Input/Output Characteristics Input clock Clock Parameter Symbol Period tSCL Low level tSCLL Specification Applicable Conditions Pin/Remarks SL0CK(PA4) VDD[V] • See Fig. 8. High level tSCLH tsp pins input spike max unit Tfilt 2.5 2 pulse width SL0CK and SL0DA typ 5 2.5 to 5.5 pulse width min SL0CK(PA4) • See Fig. 8. SL0DA(PA5) 2.5 to 5.5 1 Tfilt suppression time time between start and stop tBUF Start/restart • See Fig. 8. 2.5 to 5.5 tHD;STA condition hold SL0CK(PA4) SL0DA(PA5) 2.5 Tfilt • When SMIIC register control bit, I2CSHDS=0 • See Fig. 8. Input time SL0CK(PA4) SL0DA(PA5) Input Bus release • When SMIIC register control bit 2.0 2.5 to 5.5 2 I CSHDS=1 Tfilt 2.5 • See Fig. 8. condition setup time tSU;STA setup time tSU;STO tHD;DAT SL0CK(PA4) SL0CK(PA4) Output SL0DA(PA5) Tfilt 2.5 to 5.5 1.0 Tfilt • See Fig. 8. • See Fig. 8. • Specified as interval up to time 2.5 to 5.5 Tfilt when output state starts changing. 1 tSU;DAT SL0CK(PA4) 1.5 • See Fig. 8. Input SL0DA(PA5) 1 tSU;DATx Output 1.0 0 tHD;DATx Data setup time SL0CK(PA4) 2.5 to 5.5 SL0DA(PA5) Input Data hold time • See Fig. 8. SL0DA(PA5) Input Stop condition SL0CK(PA4) SL0DA(PA5) Input Restart SL0CK(PA4) SL0DA(PA5) • Specified as interval up to time when output state starts changing. 2.5 to 5.5 Tfilt 1tSCL -1.5Tfilt No.A1659-28/38 LC88F52H0A UART0 Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Transfer rate Symbol UBR0 Applicable Pin/Remarks Specification Conditions VDD[V] min typ max unit U0RX(P13), U0TX(P14), 2.5 to 5.5 4 8 tBGCYC U0BRG(P07) Note 4-9: tBGCYC denotes one cycle of the baudrate clock source. UART2 Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Transfer rate Symbol UBR2 Applicable Pin/Remarks Specification Conditions VDD[V] U2RX(P16), min 2.5 to 5.5 U2TX(P17) typ max 8 4096 unit tBGCYC Note 4-10: tBGCYC denotes one cycle of the baudrate clock source. UART3 Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Transfer rate Symbol UBR3 Applicable Pin/Remarks Specification Conditions VDD[V] U3RX(P34), min 2.5 to 5.5 U3TX(P35) typ max 8 4096 unit tBGCYC Note 4-10: tBGCYC denotes one cycle of the baudrate clock source. UART4 Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Transfer rate Symbol UBR4 Applicable Pin/Remarks Specification Conditions VDD[V] U4RX(PB2), min 2.5 to 5.5 U4TX(PB3) typ max 8 4096 unit tBGCYC Note 4-10: tBGCYC denotes one cycle of the baudrate clock source. Pulse Input Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Applicable Pin/Remarks Specification Conditions VDD[V] High/low level tPIH(1) INT0(P30), • Interrupt source flag can be set. pulse width tPIL(1) INT1(P31), • Event inputs for timers 2 and 3 INT2(P32), min typ max unit are enabled. INT3(P33), INT4(P20), 2.5 to 5.5 2 tCYC 2.5 to 5.5 10 μs INT5(P21), INT6(P40), INT7(P41) tPIL(2) RESB Resetting is enabled. No.A1659-29/38 LC88F52H0A AD Converter Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V 12-bit AD Conversion Mode Parameter Applicable Pin Symbol /Remarks Resolution NAD AN0(P60) to Absolute accuracy ETAD AN7(P67), Conversion time TCAD12 AN8(P70) to Specification Conditions VDD[V] typ 3.0 to 5.5 max unit 12 bit (Note 6-1) 3.0 to 5.5 Conversion time calculated 4.5 to 5.5 27 209 3.0 to 5.5 67 209 3.0 to 5.5 VSS VDD AN15(P77) Analog input min VAIN voltage range Analog port IAINH VAIN=VDD 3.0 to 5.5 input current IAINL VAIN=VSS 3.0 to 5.5 ±16 1 -1 LSB μs V μA Conversion time calculation formula: TCAD12= ((52/(AD division ratio))+2) × tCYC 8-bit AD Conversion Mode Parameter Symbol Applicable Pin /Remarks Resolution NAD AN0(P60) to Absolute accuracy ETAD AN7(P67), Conversion time TCAD8 AN8(P70) to Specification Conditions VDD[V] typ max unit 8 bit (Note 6-1) 3.0 to 5.5 Conversion time calculated 4.5 to 5.5 17 129 3.0 to 5.5 42 129 3.0 to 5.5 VSS VDD AN15(P77) Analog input min 3.0 to 5.5 VAIN voltage range Analog port IAINH VAIN=VDD 3.0 to 5.5 input current IAINL VAIN=VSS 3.0 to 5.5 ±1.5 1 -1 LSB μs V μA Conversion time calculation formula: TCAD8= ((32/(AD division ratio))+2) × tCYC Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital value against the analog input value is loaded in the result register. The conversion time is twice the normal value when one of the following conditions occurs: • The first AD conversion is executed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode. DA Converter Characteristics at Ta=-40 to+85°C, VSS1=VSS2=VSS3=VSS4=0V Applicable Pin Parameter Symbol /Remarks Specification Conditions VDD[V] Resolution NDA DA00(PD0) to 3.0 to 5.5 Absolute accuracy ETDA DA02(PD2) 3.0 to 5.5 Output resistor DAOR Analog port VDAOUT output current DA10(PD3) to DA12(PD5) min typ max 8 3.0 to 5.5 9.5 3.0 to 5.5 VSS 16.0 unit bit ±2.0 LSB 22.9 kΩ VDD V No.A1659-30/38 LC88F52H0A Consumption Current Characteristics at Ta=-40 to +85°C, VSS1=VSS2=VSS3=VSS4=0V typ: 5.0V (VDD=4.5V to 5.5V), 3.3V (VDD=3.0V to 4.5V, 2.2V to 4.5V) Parameter Normal mode Symbol IDDOP(1) consumption current (Note 7-1) Applicable Pin/Remarks Specification Conditions VDD[V] VDD1 =VDD2 • FmCF=12MHz ceramic oscillation mode =VDD3 =VDD4 • System clock set to 12MHz min typ max unit • FmX'tal=32.768kHz crystal oscillation mode 4.5 to 5.5 10.4 19 4.5 to 5.5 8.50 17 3.0 to 4.5 4.91 13 • Internal RC oscillation stopped • 1/1 frequency division mode IDDOP(2) • FmCF=8MHz ceramic oscillator mode • FmX'tal=32.768kHz crystal oscillator mode IDDOP(3) • System clock set to 8MHz • Internal RC oscillation stopped • 1/1 frequency division mode IDDOP(4) • FmX'tal=32.768kHz crystal oscillator mode IDDOP(5) • Internal RC oscillation stopped • FmCF=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode IDDOP(7) • System clock set to internal RC oscillation • 1/1 frequency division mode IDDOP(8) 6.1 2.5 to 4.5 2.62 4.3 4.5 to 5.5 2.18 6.0 2.2 to 4.5 1.28 4.2 4.5 to 5.5 72.9 195 2.2 to 4.5 39.8 160 4.5 to 5.5 10.5 19.2 • System clock set to 32.768kHz • Internal RC oscillation stopped • 1/1 frequency division mode IDDOP(10) 4.02 • FmCF=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode IDDOP(9) 4.5 to 5.5 • System clock set to 4MHz • 1/2 frequency division mode IDDOP(6) mA • FmCF=4MHz ceramic oscillator mode μA • FmCF=0Hz (oscillation stopped) • FmVCO=11.1MHz oscillator mode • FmX'tal=32.768kHz crystal oscillator mode • System clock set to VCO • Internal RC oscillation stopped • 1/1 frequency division mode IDDOP(11) mA • FmCF=0Hz (oscillation stopped) • FmVCO=7.34MHz oscillator mode 4.5 to 5.5 9.07 17.3 3.0 to 4.5 5.23 13.8 • FmX'tal=32.768kHz crystal oscillator mode IDDOP(12) • System clock set to VCO • Internal RC oscillation stopped • 1/1 frequency division mode Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors. Continued on next page. No.A1659-31/38 LC88F52H0A Continued from preceding page. Parameter HALT mode Symbol IDDHALT(1) consumptio n current (Note 7-1) Specification Applicable Conditions Pin/Remarks VDD[V] VDD1 =VDD2 • HALT mode =VDD3 =VDD4 • FmX'tal=32.768kHz crystal oscillation mode min typ max unit • FmCF=12MHz ceramic mode • System clock set to 12MHz 4.5 to 5.5 3.70 6.5 4.5 to 5.5 2.60 5.0 3.0 to 4.5 1.34 3.5 • Internal RC oscillation stopped • 1/1 frequency division mode • HALT mode IDDHALT(2) • FmCF=10MHz ceramic oscillator mode • FmX'tal=32.768kHz crystal oscillator mode • System clock set to 10MHz IDDHALT(3) • Internal RC oscillation stopped • 1/1 frequency division mode mA • HALT mode IDDHALT(4) • FmCF=4MHz ceramic oscillator mode 4.5 to 5.5 1.08 3.1 2.2 to 4.5 0.50 2.2 4.5 to 5.5 0.53 3.0 2.2 to 4.5 0.26 2.1 4.5 to 5.5 27.3 145 • FmX'tal=32.768kHz crystal oscillator mode • System clock set to 4MHz IDDHALT(5) • Internal RC oscillation stopped • 1/2 frequency division mode • HALT mode IDDHALT(6) • FmCF=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode IDDHALT(7) • System clock set to internal RC oscillation • 1/1 frequency division mode • HALT mode IDDHALT(8) • FmCF=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode μA • System clock set to 32.768kHz IDDHALT(9) • Internal RC oscillation stopped 2.2 to 4.5 9.52 112 4.5 to 5.5 4.19 6.8 • 1/1 frequency division mode • HALT mode IDDHALT(10) • FmCF=0Hz (oscillation stopped) • FmVCO=11.1MHz oscillator mode • FmX'tal=32.768kHz crystal oscillator mode • System clock set to VCO • Internal RC oscillation stopped • 1/1 frequency division mode mA • HALT mode IDDHALT(11) • FmCF=0Hz (oscillation stopped) • FmVCO=7.34MHz oscillator mode 4.5 to 5.5 3.18 5.5 3.0 to 4.5 1.68 4.0 4.5 to 5.5 0.11 98 2.5 to 4.5 0.04 72 4.5 to 5.5 19.0 132 2.5 to 4.5 4.91 90 FmX'tal=32.768kHz crystal oscillator mode IIDHALT(12) • System clock set to VCO vInternal RC oscillation stopped • 1/1 frequency division mode HOLD mode consumption current HOLDX IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) current HOLD mode • CF1=VDD or open (external clock mode) HOLDX mode • CF1=VDD or open (external clock mode) mode consumption VDD1 IDDHOLD(4) • FmX'tal=32.768kHz crystal oscillator mode μA Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors. No.A1659-32/38 LC88F52H0A F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1=VSS2=VSS3=VSS4=0V Parameter Onboard Symbol IDDFW(1) Specification Applicable Conditions Pin/Remarks VDD1 programming VDD[V] min typ max unit • Microcontroller erase current current is excluded. 3.0 to 5.5 15 mA current Onboard tFW(1) • 512-/1K-byte erase operation 3.0 to 5.5 30 ms tFW(2) • 2-byte programming operation 3.0 to 5.5 60 μs programming time Power Pin Treatment Conditions 1 (VDD1, VSS1) Connect capacitors that meet the following conditions between the VDD1 and VSS1 pins: • Connect among the VDD1 and VSS1 pins and the capacitors C1 and C2 with the shortest possible lead wires, of the same length (L1=L1', L2=L2') wherever possible. • Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. The capacitance of C2 should be approximately 0.1μF or larger. • The VDD1 and VSS1 traces must be thicker than the other traces. L2 L1 VSS1 C1 C2 VDD1 L1’ L2’ Power Pin Treatment Conditions 2 (VDD(2, 3, 4), VSS(2, 3, 4)) Connect capacitors that meet the following condition between the VDD(2, 3, 4) and VSS(2, 3, 4) pins: • Connect among the VDD(2, 3, 4) and VSS(2, 3, 4) pins and the capacitor C3 with the shortest possible lead wires, of the same length (L3=L3') wherever possible. • The capacitance of C3 should be approximately 0.1μF or larger. • The VDD(2, 3, 4) and VSS(2, 3, 4) traces must be thicker than the other traces. L3 VSS (2, 3, 4) C3 VDD (2, 3, 4) L3’ No.A1659-33/38 LC88F52H0A Characteristics of a Sample OSC1 System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator Nominal Vendor Frequency Name 12MHz Circuit Constant Resonator Operating Oscillation Voltage Stabilization Time C3 C4 Rf Rd2 Range typ max [pF] [pF] [Ω] [Ω] [V] [ms] [ms] CSTCE12M0G52-R0 (10) (10) OPEN 470 2.4 to 5.5 0.02 0.2 CSTCE8M00G52-R0 (10) (10) OPEN 1k 2.3 to 5.5 0.02 0.2 CSTLS8M00G53-B0 (15) (15) OPEN 1k 2.5 to 5.5 0.02 0.2 CSTCR4M00G53-R0 (15) (15) OPEN 1.5k 2.2 to 5.5 0.02 0.2 CSTLS4M00G53-B0 (15) (15) OPEN 1.5k 2.3 to 5.5 0.02 0.2 8MHz MURATA 4MHz Remarks C1, C2 integrated type C1, C2 integrated type C1, C2 integrated type C1, C2 integrated type C1, C2 integrated type The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the lower limit level of the operating voltage range (see Figure 4) Characteristics of a Sample System Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Resonator Nominal Vendor Frequency Name 32.768kHz EPSON TOYOCOM Circuit Constant Oscillator Name Operating Oscillation Voltage Stabilization Time C3 C4 Rf2 Rd2 Range typ max [pF] [pF] [Ω] [Ω] [V] [s] [s] 10 10 OPEN 0 2.2 to 5.5 0.8 2 MC-306 Remarks Applicable CL value=7.0pF The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillator circuit is executed plus the time interval that is required for the oscillation to get stabilized after the HOLD mode is released (see Figure 4). Note: The traces to and from the components that are involved in oscillation should be kept as short as possible as the oscillation characteristics are affected by their trace pattern. CF2 CF1 Rf1 C1 XT1 Rf2 Rd1 C2 XT2 Rd2 C3 C4 CF X’tal Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A1659-34/38 LC88F52H0A VDD Operating VDD lower limit 0V Power Reset time RESB Internal RC oscillation tmsCF CF1, CF2 tmsX'tal XT1, XT2 Operating mode Unpredictable Reset Initialization instruction execution User instruction execution Reset Time and Oscillation Stabilization Time HOLD release No HOLD release signal HOLD release signal valid Interrupt operation Internal RC oscillation tmsCF CF1, CF2 tmsX'tal XT1, XT2 State HOLD HALT Instruction execution HOLD Release and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time Timing Charts No.A1659-35/38 LC88F52H0A VDD Note: Reset signal must be present when power supply rises. Determine the value of CRES and RRES so that the reset signal is present for 10μs after the supply voltage gets stabilized. RRES RES CRES Figure 5 Reset Circuit tSCKHBSY tSCKHBSY RUN: SIOCLK: DATAIN: DI0 DI1 DI6 DI7 DI8 DIx DATAOUT: DO0 DO1 DO6 DO7 DO8 DOx Data RAM transfer period (SIO0 and SIO1 only) tSCK SIOCLK: tSCKL tSCKH tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 and SIO1 only) SIOCLK: tSCKL tSCKHA tsDI thDI DATAIN: tdDO DATAOUT: *: * Remarks: DIx and DOx denote the last bits communicated; x = 0 to 32768 Figure 6 Serial I/O Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.A1659-36/38 LC88F52H0A P S Sr P SDA tBUF tHD;STA tR tF tHD;STA tsp SCK tLOW tHD;DAT tHIGH tSU;DAT tSU;STO tSU;STA S: Start condition P: Stop condition Sr: Restart condition Figure 8 I2C Timing 100Ω PC2/FILT + 1MΩ 33000pF 2.2μF - VSS1 Figure 9 FILT recommended circuit *Take at least 50ms to oscillation to stabilize after PLL is started. No.A1659-37/38 LC88F52H0A ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A1659-38/38