S i 5 3 4 7/46 D U AL /Q UA D DSPLL A NY - F RE QU EN CY, A NY -O UT P UT J ITTER A TT E NU AT OR S Features Four or two independent DSPLLs in a single monolithic IC Each DSPLL generates any output frequency from any input frequency Input frequency range: Differential: 8 kHz to 750 MHz LVCMOS: 8 kHz to 250 MHz Output frequency range: Differential: up to 712.5 MHz LVCMOS: up to 250 MHz Ultra low jitter: <100 fs typ (12 kHz–20 MHz) Flexible crosspoints route any input to any output clock Programmable jitter attenuation bandwidth per DSPLL: 0.1 Hz to 4 kHz programming range Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable signal amplitude Status monitoring (LOS, OOF, LOL) Hitless input clock switching: automatic or manual Locks to gapped clock inputs Automatic free-run and holdover modes Fastlock feature for low nominal bandwidths Glitchless on-the-fly DSPLL frequency changes DCO mode: as low as 0.01 ppb steps per DSPLL Core voltage: VDD: 1.8 V ±5% VDDA: 3.3 V ±5% Independent output clock supply pins: 3.3, 2.5, or 1.8 V Output-output skew: <20 ps (typ) per DSPLL Serial interface: I2C or SPI In-circuit programmable with non-volatile OTP memory ClockBuilderTM Pro software tool simplifies device configuration Si5347: Quad DSPLL, 4 input, 4 or 8 output, 64 QFN Si5346: Dual DSPLL, 4 input, 4 output, 44 QFN Temperature range: –40 to +85 °C Pb-free, RoHS-6 compliant 9x9 mm Ordering Information: See section 8 Functional Block Diagram XTAL/ REFCLK Si5347 Max Output Freq Frequency Synthesis Modes 4/8 712.5 MHz Integer + Fractional Si5347C 4/4 712.5 MHz Integer + Fractional Si5346A 2/4 712.5 MHz Integer + Fractional Si5347B 4/8 350 MHz Integer + Fractional Si5347D 4/4 350 MHz Integer + Fractional Si5346B 2/4 350 MHz Integer + Fractional IN0 ÷FRAC DSPLL A IN1 ÷FRAC DSPLL B IN2 ÷FRAC DSPLL C IN3 ÷FRAC DSPLL D NVM OTN Muxponders and Transponders 10/40/100G network line cards GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262) OUT0 ÷INT OUT1 ÷INT OUT2 ÷INT OUT3 ÷INT OUT4 ÷INT OUT5 ÷INT OUT6 ÷INT OUT7 I2C/SPI Control/ Status Applications ÷INT Si5347A/B PLLs/OUTs XB Si5347C/D Grade XA OSC Device Selector Guide Si5347A 7x7 mm Carrier Ethernet switches Broadcast video XTAL/ R EFC LK S i5 3 4 6 XA XB OSC Description IN 0 The Si5347 is a high performance jitter attenuating clock multiplier which integrates four any-frequency DSPLLs for applications that require maximum integration and independent timing paths. The Si5346 is a dual DSPLL version in a smaller package. Each DSPLL has access to any of the four inputs and can provide low jitter clocks on any of the device outputs. Based on 4th generation DSPLL technology, these devices provide any-frequency conversion with typical jitter performance under 100 fs. Each DSPLL supports independent free-run, holdover modes of operation, as well as automatic and hitless input clock switching. The Si5347/46 is programmable via a serial interface with in-circuit programmable non-volatile memory so that it always powers up in a known configuration. Programming the Si5347/46 is easy with Silicon Labs’ ClockBuilder Pro software. Factory pre-programmed devices are also available. Rev. 1.1 9/15 IN 1 ÷FR A C ÷FR A C IN 2 ÷FR A C IN 3 ÷FR A C Copyright © 2015 by Silicon Laboratories DSPLL A DSPLL B ÷ IN T OUT0 ÷ IN T OUT1 ÷ IN T OUT2 ÷ IN T OUT3 NVM I 2 C /S P I C o n tro l/ S ta tu s Si5347/46 Si5347/46 TABLE O F C ONTENTS 1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3. Typical Operating Characteristics (Jitter and Phase Noise) . . . . . . . . . . . . . . . . . . . . . 22 4. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4. Digitally-Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.5. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.6. Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 5.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 5.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 5.12. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.13. How to Enable Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . 42 6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.1. Ordering Part Number Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 9.1. Si5347 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 9.2. Si5346 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 12. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2 Rev. 1.1 Si5347/46 1. Typical Application Schematic OTN Muxponder Si5347 Client #1 Data Clock PD ÷ Gapped Clock PHY 10GbE PHY 10GbE PHY 10GbE PHY 10GbE LPF Mn_A Md_A DSPLL A Non-gapped Jitter Attenuated Clock Client #2 Data Clock 40G OTN PD LPF ÷ Gapped Clock Mn_B Md_B DSPLL B OTN De-Mapper Non-gapped Jitter Attenuated Clock Client #3 Data Clock PD LPF ÷ Gapped Clock Mn_C Md_C DSPLL C Non-gapped Jitter Attenuated Clock Client #4 Data Clock PD Gapped Clock LPF ÷ Mn_D Md_D DSPLL D Non-gapped Jitter Attenuated Clock Figure 1. Using the Si5347 to Clean Gapped Clocks in an OTN Application Rev. 1.1 3 Si5347/46 2. Electrical Specifications Table 1. Recommended Operating Conditions (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%,TA = –40 to 85 °C) Parameter Symbol Min Typ Max Unit Ambient Temperature TA –40 25 85 °C Junction Temperature TJMAX — — 125 °C Core Supply Voltage VDD 1.71 1.80 1.89 V VDDA 3.14 3.30 3.47 V VDDO 3.14 3.30 3.47 V 2.38 2.50 2.62 V 1.71 1.80 1.89 V 3.14 3.30 3.47 V 1.71 1.80 1.89 V Output Driver Supply Voltage Status Pin Supply Voltage VDDS Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. Table 2. DC Characteristics (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Core Supply Current Test Condition IDD Min Typ Max Unit — 175 240 mA Si5346 — 170 230 mA Si5347 — 120 130 mA 120 130 mA Si5347 IDDA Notes 1, 2 Si5346 Notes: 1. Si5347 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors. 2. Si5346 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors. 3. Differential outputs terminated into an AC coupled 100 load. 4. LVCMOS outputs measured into a 5-inch 50 PCB trace with 5 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3, which is the strongest driver setting. Refer to the Si5347/46 Family Reference Manual for more details on register settings. 5. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is not available. All EVBs support detailed current measurements for any configuration. LVCMOS Output Test Configuration Differential Output Test Configuration Trace length 5 inches IDDO 0.1 µF OUT IDDO 50 100 OUT 499 0.1 µF 50 Scope Input 50 OUT 4.7 pF 56 OUT 50 0.1 µF 499 0.1 µF 50 Scope Input 50 4.7 pF 4 Rev. 1.1 56 Si5347/46 Table 2. DC Characteristics (Continued) (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit IDDO LVPECL Output3 @ 156.25 MHz — 21 25 mA LVDS Output3 @ 156.25 MHz — 15 18 mA 3.3V LVCMOS4 output @ 156.25 MHz — 21 25 mA 2.5V LVCMOS4 output @ 156.25 MHz — 16 18 mA 1.8V LVCMOS4 output @ 156.25 MHz — 12 13 mA Output Buffer Supply Current Total Power Dissipation Pd Si5347 Note 1,5 — 980 1160 mW Si5346 Note 2,5 — 840 1000 mW Notes: 1. Si5347 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors. 2. Si5346 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors. 3. Differential outputs terminated into an AC coupled 100 load. 4. LVCMOS outputs measured into a 5-inch 50 PCB trace with 5 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3, which is the strongest driver setting. Refer to the Si5347/46 Family Reference Manual for more details on register settings. 5. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is not available. All EVBs support detailed current measurements for any configuration. LVCMOS Output Test Configuration Differential Output Test Configuration Trace length 5 inches IDDO 0.1 µF OUT IDDO 50 100 OUT 499 0.1 µF 50 Scope Input 50 OUT 4.7 pF 56 OUT 50 0.1 µF 499 0.1 µF 50 Scope Input 50 4.7 pF Rev. 1.1 56 5 Si5347/46 Table 3. Input Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Standard Differential or Single-Ended/LVCMOS — AC-coupled (IN0, IN1, IN2, IN3/FB_IN) Input Frequency Range Input Voltage Swing Input Voltage Amplitude fIN_DIFF VIN_DIFF VIN_SE Differential 0.008 — 750 MHz Single-ended/LVCMOS 0.008 — 250 fIN< 250 MHz, Differential 100 — 1800 mVpp_se 250 MHz < fIN< 750 MHz, Differential 225 — 1800 mVpp_se fIN< 250 MHz, Singleended 100 — 3600 mVpp_se Slew Rate1,2 SR 400 — — V/µs Duty Cycle DC 40 — 60 % Capacitance CIN — 2 — pF 0.008 — 250 MHz VIL –0.2 — 0.33 V VIH 0.49 — — V SR 400 — — V/µs 1.6 — — ns — 8 — k 48 — 54 MHz Pulsed CMOS — DC-coupled (IN0, IN1, IN2, IN3)3 Input Frequency fIN_PULSED Input Voltage Slew Rate1,2 Minimum Pulse Width PW Input Resistance RIN Pulse Input REFCLK (Applied to XA/XB) REFCLK Frequency fIN_REF Input Voltage Swing VIN_DIFF 365 — 2500 mVpp_diff VIN_SE 365 — 2000 mVpp_se 400 — — V/µs 40 — 60 % Slew rate1,2 SR Input Duty Cycle DC Frequency range for best output jitter performance Imposed for best jitter performance Notes: 1. Imposed for jitter performance. 2. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) x VIN_Vpp_se) / SR. 3. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, which must be dc-coupled because they have a duty cycle significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since the input thresholds (VIL, VIH) of this buffer are non-standard (0.33 and 0.49 V, respectively), refer to the input attenuator circuit for DC-coupled Pulsed LVCMOS in the Si5347-46 Family Reference Manual. Otherwise, for standard LVCMOS input clocks, use the Standard AC-coupled, Single-ended input mode. 6 Rev. 1.1 Si5347/46 Table 4. Serial and Control Input Pin Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Si5347 Serial and Control Input Pins (I2C_SEL, RST, OE0, A1/SDO, SCLK, A0/CS, FINC, A0/CS, SDA/SDIO, DSPLL_SEL[1:0]) VIL — — 0.3 x VDDIO1 V VIH 0.7 x VDDIO1 — — V Input Capacitance CIN — 2 — pF Input Resistance RL — 20 — k Minimum Pulse Width PW RST, FINC 100 — — ns Update Rate FUR FINC — — 1 MHz VIL — — 0.3 x VDDS V VIH 0.7 x VDDS — — V Input Capacitance CIN — 2 — pF Minimum Pulse Width PW FDEC 100 — — ns Update Rate FUR FDEC — — 1 MHz Input Voltage Si5347 Control Input Pins (FDEC, OE1) Input Voltage Si5346 Serial and Control Input Pins (I2C_SEL, RST, OE0, OE1, A1/SDO, SCLK, A0/CS, SDA/SDIO) VIL — — 0.3 x VDDIO1 V VIH 0.7 x VDDIO1 — — V Input Capacitance CIN — 2 — pF Input Resistance RL — 20 — k Minimum Pulse Width PW 100 — — ns Input Voltage RST Note: 1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Rev. 1.1 7 Si5347/46 Table 5. Differential Clock Output Specifications (VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Output Frequency fOUT Duty Cycle DC Output-Output Skew Test Condition Min Typ Max Unit 0.0001 — 712.5 MHz fOUT < 400 MHz 48 — 52 % 400 MHz < fOUT < 712.5 MHz 44 — 55 % Differential Output, Normal Swing Mode — 20 50 ps Differential Output, Low Power Swing Mode — 20 100 ps Measured from the positive to negative output pins — 0 100 ps mVpp_se TSK OUT-OUT Skew TSK_OUT Output Voltage Amplitude1 Normal Mode VOUT VDDO = 3.3 V, 2.5 V, or 1.8 V LVDS 350 470 550 VDDO = 3.3 V, 2.5 V LVPECL 660 810 1000 VDDO = 3.3 V, 2.5 V, or 1.8 V LVDS 300 420 530 VDDO = 3.3 V, 2.5 V LVPECL 620 820 1060 Low Power Mode VOUT mVpp_se Notes: 1. Output amplitude and common mode voltage are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum.Refer to the Si5347/46 Family Reference Manual for more suggested output settings. Not all combinations of voltage amplitude and common mode voltages settings are possible. 2. Driver output impedance depends on selected output mode (Normal, Low Power). Refer to the Si5347/46 Family Reference Manual for more information. 3. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/ 3.3 V = 100 mVpp) and noise spur amplitude measured. 4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to application note, “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems”, guidance on crosstalk minimization. Note that all active outputs must be terminated when measuring crosstalk. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTx 8 Rev. 1.1 Si5347/46 Table 5. Differential Clock Output Specifications (Continued) (VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Common Mode Voltage1,2,3 Test Condition Min Typ Max Unit LVDS 1.10 1.25 1.35 V LVPECL 1.90 2.05 2.15 VDDO = 2.5 V LVPECL, LVDS 1.15 1.25 1.35 VDDO = 1.8 V sub-LVDS 0.87 0.93 1.00 Normal Mode — 170 240 Low Power Mode — 300 430 Normal Mode — 100 — Low Power Mode — 650 — Normal Mode or Low Power Modes VCM Rise and Fall Times (20% to 80%) VDDO = 3.3 V tR/tF Differential Output Impedance2 ZO ps Notes: 1. Output amplitude and common mode voltage are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum.Refer to the Si5347/46 Family Reference Manual for more suggested output settings. Not all combinations of voltage amplitude and common mode voltages settings are possible. 2. Driver output impedance depends on selected output mode (Normal, Low Power). Refer to the Si5347/46 Family Reference Manual for more information. 3. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/ 3.3 V = 100 mVpp) and noise spur amplitude measured. 4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to application note, “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems”, guidance on crosstalk minimization. Note that all active outputs must be terminated when measuring crosstalk. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTx Rev. 1.1 9 Si5347/46 Table 5. Differential Clock Output Specifications (Continued) (VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Power Supply Noise Rejection3 PSRR Test Condition Min Typ Max Unit 10 kHz sinusoidal noise — –93 — dBc 100 kHz sinusoidal noise — –93 — 500 kHz sinusoidal noise — –84 — 1 MHz sinusoidal noise — –79 — 10 kHz sinusoidal noise — –98 — 100 kHz sinusoidal noise — –95 — 500 kHz sinusoidal noise — –84 — 1 MHz sinusoidal noise — –76 — Si5347 — –75 — dB Si5346 — –85 — dB Normal Mode Low Power Mode Output-output Crosstalk4 XTALK dBc Notes: 1. Output amplitude and common mode voltage are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum.Refer to the Si5347/46 Family Reference Manual for more suggested output settings. Not all combinations of voltage amplitude and common mode voltages settings are possible. 2. Driver output impedance depends on selected output mode (Normal, Low Power). Refer to the Si5347/46 Family Reference Manual for more information. 3. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/ 3.3 V = 100 mVpp) and noise spur amplitude measured. 4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to application note, “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems”, guidance on crosstalk minimization. Note that all active outputs must be terminated when measuring crosstalk. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTx 10 Rev. 1.1 Si5347/46 Table 6. LVCMOS Clock Output Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Output Frequency fOUT Duty Cycle DC Output-to-Output Skew TSK Output Voltage High1, 2, 3 VOH Test Condition Min Typ Max Unit 0.0001 — 250 MHz fOUT <100 MHz 47 — 53 % 100 MHz < fOUT < 250 MHz 44 — 55 LVCMOS outputs — — 100 ps VDDO x 0.75 — — V — — — — — — — — — — — — — — VDDO = 3.3 V OUTx_CMOS_DRV=1 IOH = –10 mA OUTx_CMOS_DRV=2 IOH = –12 mA OUTx_CMOS_DRV=3 IOH = –17 mA VDDO = 2.5 V OUTx_CMOS_DRV=1 IOH = –6 mA OUTx_CMOS_DRV=2 IOH = –8 mA OUTx_CMOS_DRV=3 IOH = –11 mA VDDO x 0.75 V VDDO = 1.8 V OUTx_CMOS_DRV=2 IOH = –4 mA OUTx_CMOS_DRV=3 IOH = –5 mA VDDO x 0.75 V Notes: 1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the Si5347/46 Family Reference Manual for more details on register settings. 2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration. 3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3. LVCMOS Output Test Configuration DC Test Configuration Trace length 5 inches IOL/IOH IDDO Zs VOL/VOH 499 0.1 µF 50 Scope Input 50 OUT 4.7 pF 56 OUT 499 0.1 µF 50 Scope Input 50 4.7 pF Rev. 1.1 56 11 Si5347/46 Table 6. LVCMOS Clock Output Specifications (Continued) (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Output Voltage Low1, 2, 3 VOL Test Condition Min Typ Max Unit VDDO x 0.15 V VDDO x 0.15 V VDDO x 0.15 V VDDO = 3.3 V OUTx_CMOS_DRV=1 IOL = 10 mA — — OUTx_CMOS_DRV=2 IOL = 12 mA — — OUTx_CMOS_DRV=3 IOL = 17 mA — — VDDO = 2.5 V OUTx_CMOS_DRV=1 IOL = 6 mA — — OUTx_CMOS_DRV=2 IOL = 8 mA — — OUTx_CMOS_DRV=3 IOL = 11 mA — — VDDO = 1.8 V LVCMOS Rise and Fall Times3 (20% to 80%) OUTx_CMOS_DRV=2 IOL = 4 mA — — OUTx_CMOS_DRV=3 IOL = 5 mA — — VDDO = 3.3V — 420 550 ps VDDO = 2.5 V — 475 625 ps VDDO = 1.8 V — 525 705 ps tr/tf Notes: 1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the Si5347/46 Family Reference Manual for more details on register settings. 2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration. 3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3. LVCMOS Output Test Configuration DC Test Configuration Trace length 5 inches IOL/IOH IDDO Zs VOL/VOH 499 0.1 µF 50 Scope Input 50 OUT 4.7 pF 56 OUT 499 0.1 µF 50 Scope Input 50 4.7 pF 12 Rev. 1.1 56 Si5347/46 Table 7. Output Serial and Status Pin Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Si5347 Serial and Status Output Pins (LOL_A, LOL_B, LOL_C, LOL_D, INTR, LOS_XAXB, SDA/SDIO1, A1/ SDO) Output Voltage VOH IOH = –2 mA VDDIO2 x 0.75 — — V VOL IOL = 2 mA — — VDDIO2 x 0.15 V Si5346 Status Output Pins (INTR, LOS_XAXB, SDA/SDIO1, A1/SDO) Output Voltage VOH IOH = –2 mA VDDIO2 x 0.75 — — V VOL IOL = 2 mA — — VDDIO2 x 0.15 V Si5346 Serial and Status Output Pins (LOL_A, LOL_B) Output Voltage VOH IOH = –2 mA VDDS x 0.75 — — V VOL IOL = 2 mA — — VDDS x 0.15 V Notes: 1. The VOH specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused with I2C_SEL pulled high. VOL remains valid in all cases. 2. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Users normally select this option in the ClockBuilder Pro GUI. Alternatively, refer to the Si5347-46 Family Reference Manual for more details on register settings. Rev. 1.1 13 Si5347/46 Table 8. Performance Characteristics (VDD = 1.8 V ±5%, or 3.3 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter PLL Loop Bandwidth Programming Range3 Initial Start-Up Time Symbol Test Condition fBW Min Typ Max Unit 0.1 — 4000 Hz tSTART Time from power-up to when the device generates free-running clocks — 30 45 ms PLL Lock Time tACQ With Fastlock enabled, fIN = 19.44 MHz1 — 500 600 ms POR to Serial Interface Ready2 tRDY — — 15 ms Jitter Peaking JPK Measured with a frequency plan running a 25 MHz input, 25 MHz output, and a loop bandwidth of 4 Hz — — 0.1 dB Jitter Tolerance JTOL Compliant with G.8262 Options 1&2 Carrier Frequency = 10.3125 GHz Jitter Modulation Frequency = 10 Hz — 3180 — UI pk-pk tSWITCH Only valid for a single switch between two input clocks running at the same frequency — — 2.8 ns P — 500 — ppm tIODELAY — 2 — ns — 0.090 0.165 ps RMS Maximum Phase Transient During a Hitless Switch Pull-in Range Input-to-Output Delay Variation RMS Phase Jitter4 JGEN 12 kHz to 20 MHz Notes: 1. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this case, lock time was measured with nominal and fastlock bandwidths, both set to 100 Hz, LOL set/clear thresholds of 3/ 0.3 ppm respectively, using IN0 as clock reference by removing the reference and enabling it again, then measuring the delta time between the first rising edge of the clock reference and the LOL indicator de-assertion. 2. Measured as time from valid VDD/VDDA rails (90% of their value) to when the serial interface is ready to respond to commands. 3. Actual loop bandwidth might be lower; please refer to CBPro for actual value on your frequency plan. 4. Jitter generation test conditions: fIN = 19.44 MHz, fOUT = 156.25 MHz LVPECL, loop bandwidth = 100 Hz. Does not include jitter from input reference. 14 Rev. 1.1 Si5347/46 Table 9. I2C Timing Specifications (SCL,SDA) Parameter SCL Clock Frequency SMBus Timeout Symbol Test Condition fSCL — When Timeout is Enabled Standard Mode 100 kbps Fast Mode 400 kbps Unit Min Max Min Max — 100 — 400 kHz 25 35 25 35 ms Hold Time (repeated) START Condition tHD:STA 4.0 — 0.6 — µs Low Period of the SCL Clock tLOW 4.7 — 1.3 — µs HIGH Period of the SCL Clock tHIGH 4.0 — 0.6 — µs Set-up Time for a Repeated START Condition tSU:STA 4.7 — 0.6 — µs Data Hold Time tHD:DAT 100 — 100 — ns Data Set-up Time tSU:DAT 250 — 100 — ns Rise Time of Both SDA and SCL Signals tr — 1000 20 300 ns Fall Time of Both SDA and SCL Signals tf — 300 — 300 ns tSU:STO 4.0 — 0.6 — µs tBUF 4.7 — 1.3 — µs Data Valid Time tVD:DAT — 3.45 — 0.9 µs Data Valid Acknowledge Time tVD:ACK — 3.45 — 0.9 µs Set-up Time for STOP Condition Bus Free Time between a STOP and START Condition Rev. 1.1 15 Si5347/46 Figure 2. I2C Serial Port Timing Standard and Fast Modes 16 Rev. 1.1 Si5347/46 Table 10. SPI Timing Specifications (4-Wire) (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Min Typ Max Unit SCLK Frequency fSPI — — 20 MHz SCLK Duty Cycle TDC 40 — 60 % SCLK Period TC 50 — — ns Delay Time, SCLK Fall to SDO Active TD1 — — 18 ns Delay Time, SCLK Fall to SDO TD2 — — 15 ns Delay Time, CS Rise to SDO Tri-State TD3 — — 15 ns Setup Time, CS to SCLK TSU1 5 — — ns Hold Time, SCLK Fall to CS TH1 5 — — ns Setup Time, SDI to SCLK Rise TSU2 5 — — ns Hold Time, SDI to SCLK Rise TH2 5 — — ns Delay Time Between Chip Selects (CS) TCS 2 — — TC TSU1 TD1 TC SCLK TH1 CS TSU2 TH2 TCS SDI TD2 TD3 SDO Figure 3. 4-Wire SPI Serial Interface Timing Rev. 1.1 17 Si5347/46 Table 11. SPI Timing Specifications (3-Wire) (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Min Typ Max Units SCLK Frequency fSPI — — 20 MHz SCLK Duty Cycle TDC 40 — 60 % SCLK Period TC 50 — — ns Delay Time, SCLK Fall to SDIO Turn-on TD1 — — 20 ns Delay Time, SCLK Fall to SDIO Next-bit TD2 — — 15 ns Delay Time, CS Rise to SDIO Tri-State TD3 — — 15 ns Setup Time, CS to SCLK TSU1 5 — — ns Hold Time, SCLK Fall to CS TH1 5 — — ns Setup Time, SDI to SCLK Rise TSU2 5 — — ns Hold Time, SDI to SCLK Rise TH2 5 — — ns Delay Time Between Chip Selects (CS) TCS 2 — — TC TSU1 TC SCLK TH1 TD1 TD2 CS TSU2 TH2 TCS SDIO TD3 Figure 4. 3-Wire SPI Serial Interface Timing 18 Rev. 1.1 Si5347/46 Table 12. Crystal Specifications Parameter Crystal Frequency Range Symbol Test Condition Min Typ Max Unit fXTAL_48-54 Frequency range for best jitter performance 48 — 54 MHz Load Capacitance CL_48-54 — 8 — pF Shunt Capacitance CO_48-54 — — 2 pF Crystal Drive Level dL_48-54 — — 200 µW Equivalent Series Resistance Crystal Frequency Range rESR_48-54 Refer to the Si5347/46 Family Reference Manual to determine ESR. fXTAL_25 — 25 — MHz Load Capacitance CL_25 — 8 — pF Shunt Capacitance CO_25 — — 3 pF Crystal Drive Level dL_25 — — 200 µW Equivalent Series Resistance rESR_25 Refer to the Si5347/46 Family Reference Manual to determine ESR. Notes: 1. The Si5347/46 is designed to work with crystals that meet the frequencies and specifications in Table 12. 2. Refer to the Si5347/46 Family Reference Manual for recommended 48 to 54 MHz crystals. Rev. 1.1 19 Si5347/46 Table 13. Thermal Characteristics Parameter Symbol Test Condition1 Value Unit JA Still Air 22 °C/W Air Flow 1 m/s 19.4 Air Flow 2 m/s 18.3 Si5347–64QFN Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case JC 9.5 Thermal Resistance Junction to Board JB 9.4 JB 9.3 JT 0.2 Thermal Resistance Junction to Top Center Si5346–44QFN Thermal Resistance Junction to Ambient JA Still Air 22.3 Air Flow 1 m/s 19.4 Air Flow 2 m/s 18.4 Thermal Resistance Junction to Case JC 10.9 Thermal Resistance Junction to Board JB 9.3 JB 9.2 JT 0.23 Thermal Resistance Junction to Top Center °C/W Notes: 1. Based on PCB Dimension: 3” x 4.5”, PCB Thickness: 1.6 mm, PCB Land/Via under GNP pad: 36, Number of Cu Layers: 4 20 Rev. 1.1 Si5347/46 Table 14. Absolute Maximum Ratings1,2,3 Parameter DC Supply Voltage Input Voltage Range Latch-up Tolerance Symbol Test Condition Value Unit VDD –0.5 to 3.8 V VDDA –0.5 to 3.8 V VDDO –0.5 to 3.8 V VDDS –0.5 to 3.8 V VI1 IN0 – IN3/FB_IN –0.85 to 3.8 V VI2 RST, OE0, OE1, I2C_SEL, FINC, FDEC, PLL_SEL[1:0] SDA/SDIO, A1/SDO, SCLK, A0/CS –0.5 to 3.8 V VI3 XA/XB –0.5 to 2.7 V LU ESD Tolerance HBM Junction Temperature JESD78 Compliant 2.0 kV TJCT –55 to 150 °C Storage Temperature Range TSTG –55 to +150 °C Soldering Temperature (Pb-free profile)3 TPEAK 260 °C TP 20–40 s Soldering Temperature Time at TPEAK (Pb-free profile)4 100 pF, 1.5 k Note: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. 64-QFN and 44-QFN packages are RoHS-6 compliant. 3. For detailed MSL and packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx. 4. The device is compliant with JEDEC J-STD-020. Rev. 1.1 21 Si5347/46 3. Typical Operating Characteristics (Jitter and Phase Noise) Figure 5. Input = 25 MHz; Output = 156.25 MHz, 2.5 V LVDS Figure 6. Input = 25 MHz; Output = 625 MHz, 2.5 V LVDS 22 Rev. 1.1 Si5347/46 Figure 7. Input = 19.44 MHz; Output = 644.53125 MHz, 2.5 V LVDS Figure 8. Input = 25 MHz; Output = 644.53125 MHz, 2.5 V LVDS Rev. 1.1 23 Si5347/46 48-54MHz XTAL or REFCLK VDDA VDD VDDS 4. Detailed Block Diagram 3 XA Si5347 XB OSC ÷PXAXB PD LPF Mn_A Md_A ÷ DSPLL A IN0 ÷ IN0 P0n P0d PD P ÷ 1n P1d IN1 IN1 IN2 ÷ IN2 IN3 Mn_B Md_B ÷ DSPLL B P2n P2d PD P ÷ 3n P3d IN3 LPF LPF Mn_C Md_C ÷ DSPLL C PD ÷R0 VDDO0 OUT0 OUT0 ÷R1 VDDO1 OUT1 OUT1 ÷R2 VDDO2 OUT2 OUT2 ÷R3 VDDO3 OUT3 OUT3 ÷R4 VDDO4 OUT4 OUT4 ÷R5 VDDO5 OUT5 OUT5 ÷R6 VDDO6 OUT6 OUT6 ÷R7 VDDO7 OUT7 OUT7 LPF ÷ DSPLL D Mn_D Md_D NVM I2C_SEL SDA/SDIO A1/SDO SCLK SPI/ I2C Status Monitors A0/CS Figure 9. Si5347A/B Detailed Block Diagram 24 Rev. 1.1 OE1 OE0 DSPLL_SEL[1:0] FINC FDEC INTR LOS_XAXB LOL_D LOL_C LOL_B LOL_A RST 2 VDDA VDD VDDS Si5347/46 4 2 Si5346 48-54MHz XTAL or REFCLK XA XB OSC ÷PREF P ÷ 0n P0d IN0 IN0 P ÷ 1n P1d IN1 IN1 P ÷ 2n P2d IN2 IN2 P ÷ 3n P3d IN3 IN3 PD Mn_A Md_A DSPLL A ÷R1 VDDO1 OUT1 OUT1 ÷R2 VDDO2 OUT2 OUT2 ÷R3 VDDO3 OUT3 OUT3 LPF Mn_B ÷ Md_B DSPLL B VDDO0 OUT0 OUT0 LPF ÷ PD ÷R0 I2C_SEL SDA/SDIO A1/SDO SCLK SPI/ I2C NVM Status Monitors OE1 OE0 INTR LOS_XAXB LOL_B LOL_A RST A0/CS Figure 10. Si5346 Detailed Block Diagram Rev. 1.1 25 Si5347/46 5. Functional Description The Si5347 takes advantage of Silicon Labs’ 4th generation DSPLL technology to offer the industry’s most integrated and flexible jitter attenuating clock generator solution. Each of the DSPLLs operate independently from each other and are controlled through a common serial interface. Each DSPLL has access to any of the four inputs (IN0 to IN3) with manual or automatic input selection. Any of the output clocks (OUT0 to OUT7) can be configured to any of the DSPLLs using a flexible crosspoint connection. The Si5346 is a smaller form factor dual DSPLL version with four inputs and four outputs. 5.1. Frequency Configuration The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), and integer output division (Rn) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro utility. 5.2. DSPLL Loop Bandwidth The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register-configurable DSPLL loop bandwidth settings in the range of 0.1 Hz to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally, each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection. 5.2.1. Fastlock Feature Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting as described in section “5.2. DSPLL Loop Bandwidth” . The fastlock feature can be enabled or disabled independently for each of the DSPLLs. 5.3. Modes of Operation Once initialization is complete, each of the DSPLLs operates independently in one of three modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in Figure 11. The following sections describe each of these modes in greater detail. 5.3.1. Initialization and Reset Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be restored to their initial state including the serial interface. A hard reset is initiated using the RST pin or by asserting the hard reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. A hard reset affects all DSPLLs, while a soft reset can either affect all or each DSPLL individually. 26 Rev. 1.1 Si5347/46 Power-Up Reset and Initialization No valid input clocks selected Free-run Valid input clock selected An input is qualified and available for selection Phase lock on selected input clock is achieved Holdover Mode No Ye Is holdover history valid? Lock Acquisition (Fast Lock) s Selected input clock fails Locked Mode Figure 11. Modes of Operation 5.3.2. Free-run Mode Once power is applied to the Si5347 and initialization is complete, all four DSPLLs will automatically enter Free-run Mode. The frequency accuracy of the generated output clocks in Free-run Mode is entirely dependent on the frequency accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in Freerun Mode. Any drift of the crystal frequency will be tracked at the output clock frequencies. A TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in Free-run Mode or Holdover Mode. 5.3.3. Lock Acquisition Mode Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchronization, a DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, a DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency. 5.3.4. Locked Mode Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point, any XTAL frequency drift will not affect the output frequency. Each DSPLL has its own LOL pin and status bit to indicate when lock is achieved. See "5.7.4. LOL Detection" on page 35 for more details on the operation of the loss of lock circuit. Rev. 1.1 27 Si5347/46 5.3.5. Holdover Mode Any of the DSPLLs will automatically enter Holdover Mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. Each DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for each DSPLL stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window within the stored historical frequency data. Both the window size and delay are programmable as shown in Figure 12. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency data that may be corrupt just before the input clock failure. Clock Failure and Entry into Holdover Historical Frequency Data Collected time 120s Programmable historical data window used to determine the final holdover value Programmable delay 30ms, 60ms, 1s,10s, 30s, 60s 0s 1s,10s, 30s, 60s Figure 12. Programmable Holdover Window When entering Holdover Mode, a DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in Holdover Mode, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB pins. If the clock input becomes valid, a DSPLL will automatically exit the Holdover Mode and reacquire lock to the new input clock. This process involves pulling the output clock frequencies to achieve frequency and phase lock with the input clock. This pull-in process is glitchless, and its rate is controlled by the DSPLL bandwidth or the fastlock bandwidth. These options are register programmable. 5.4. Digitally-Controlled Oscillator (DCO) Mode The DSPLLs support a DCO mode where their output frequencies are adjustable in predefined steps defined by frequency step words (FSW).The frequency adjustments are controlled through the serial interface or by pin control using frequency increment (FINC) or decrement (FDEC). A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it. The DCO mode is available when the DSPLL is operating in either Free-run or Locked Mode. 28 Rev. 1.1 Si5347/46 5.5. External Reference (XA/XB) An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra-low jitter reference clock for the DSPLLs and for providing a stable reference for the Free-run and Holdover Modes. A simplified diagram is shown in Figure 13. The device includes internal XTAL loading capacitors, which eliminates the need for external capacitors and also has the benefit of reduced noise coupling from external sources. Refer to Table 12 for crystal specifications. A crystal in the range of 48 MHz to 54 MHz is recommended for best jitter performance. Frequency offsets due to CL mismatch can be adjusted using the frequency adjustment feature, which allows frequency adjustments of ±200 ppm. The Si5347/46 Family Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. The device can also accommodate an external reference clock (REFCLK) instead of a crystal. Selection between the external XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in this mode. Refer to Table 3 for REFCLK requirements when using this mode. The Si5347/46 Family Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. A PREF divider is available to accommodate external clock frequencies higher than 54 MHz. Although the REFCLK frequency range of 25 MHz to 200 MHz is supported, frequencies in the range of 48 MHz to 54 MHz will achieve the best output jitter performance. 48-54MHz XO 48-54MHz XO 48-54MHz XTAL XA 100 XB 2xCL XA 2xCL OSC XA XB 2xCL 2xCL Si5347/46 Crystal Resonator Connection 2xCL 2xCL OSC OSC ÷PREF XB ÷PREF ÷PREF Si5347/46 Si5347/46 Differential XO Connection Single-Ended XO Connection Figure 13. Crystal Resonator and External Reference Clock Connection Options Rev. 1.1 29 Si5347/46 5.6. Inputs (IN0, IN1, IN2, IN3) There are four inputs that can be used to synchronize any of the DSPLLs. The inputs accept both differential and single-ended clocks. A crosspoint between the inputs and the DSPLLs allows any of the inputs to connect to any of the DSPLLs as shown in Figure 14. Si5347 Input Crosspoint IN0 IN0 IN1 IN1 IN2 IN2 IN3 IN3 ÷ P0n P0d ÷ P1n P1d P ÷ 2n P2d P ÷ 3n P3d 0 1 2 3 DSPLL A 0 1 2 3 DSPLL B 0 1 2 3 DSPLL C 0 1 2 3 DSPLL D Figure 14. DSPLL Input Selection Crosspoint 5.6.1. Input Selection Input selection for each of the DSPLLs can be made manually through register control or automatically using an internal state machine. 5.6.2. Manual Input Selection In Manual Mode, the input selection is made by writing to a register. If there is no clock signal on the selected input, the DSPLL will automatically enter Holdover Mode. 5.6.3. Automatic Input Selection When configured in this mode, the DSPLL automatically selects a valid input that has the highest configured priority. The priority scheme is independently configurable for each DSPLL and supports revertive or non-revertive selection. All inputs are continuously monitored for loss of signal (LOS) and/or invalid frequency range (OOF). Only inputs that do not assert both the LOS and OOF monitors can be selected for synchronization by the automatic state machine. The DSPLL(s) will enter the Holdover mode if there are no valid inputs available. 5.6.4. Input Configuration and Terminations Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are shown in Figure 15. Standard 50% duty cycle signals must be ac-coupled, while low duty cycle Pulsed CMOS signals can be dc-coupled. Unused inputs can be disabled and left unconnected when not in use. 30 Rev. 1.1 Si5347/46 Standard AC‐coupled Differential LVDS Si5347/46 50 INx Standard 100 3.3 V, 2.5 V LVDS or CML INx 50 Pulsed CMOS Standard AC‐coupled Differential LVPECL 50 INx Si5347/46 Standard 100 INx 50 3.3 V, 2.5 V LVPECL Pulsed CMOS Standard AC‐coupled Single‐ended 50 INx 3.3 V, 2.5 V, 1.8 V LVCMOS Si5347/46 Standard INx Pulsed CMOS Pulsed CMOS DC‐coupled Single‐ended Si5347/46 R1 INx 50 R2 3.3 V, 2.5 V, 1.8 V LVCMOS Resistor values for fIN_PULSED < 1 MHz VDD 1.8V 2.5V 3.3V R1 () 549 680 750 R2 () 442 324 243 Standard INx Pulsed CMOS Figure 15. Termination of Differential and LVCMOS Input Signals 5.6.5. Hitless Input Switching Hitless switching is a feature that prevents a phase transient from propagating to the output when switching between two clock inputs that have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked, meaning that they have to be exactly at the same frequency, or at a fractional frequency relationship to each other. When hitless switching is enabled, the DSPLL simply absorbs the phase difference between the two input clocks during an input switch. When disabled, the phase difference between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching feature supports clock frequencies down to the minimum input frequency of 8 kHz. Hitless switching can be enabled on a per DSPLL basis. 5.6.6. Glitchless Input Switching The DSPLLs have the ability of switching between two input clock frequencies that are up to ±500 ppm apart. The DSPLL will pull-in to the new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if it is enabled. The loss of lock (LOL) indicator will assert while the DSPLL is pulling-in to the new clock frequency. There will be no output runt pulses generated at the output during the transition. Rev. 1.1 31 Si5347/46 5.6.7. Synchronizing to Gapped Input Clocks Each of the DSPLLs support locking to an input clock that has missing periods. This is also referred to as a gapped clock. The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. Gapping a clock severely increases its jitter, so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter periodic clock. The resulting output will be a periodic nongapped clock with an average frequency of the input with its missing cycles. For example, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. This is shown in Figure 16. Gapped Input Clock Periodic Output Clock 100 MHz clock 1 missing period every 10 90 MHz non-gapped clock 100 ns 100 ns DSPLL 1 10 ns 2 3 4 5 6 7 8 9 1 10 Period Removed 2 3 4 5 6 7 8 9 11.11111... ns Figure 16. Generating an Averaged Clock Output Frequency from a Gapped Clock Input A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out of every 8. Locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the hitless switching specification in Table 8 when the switch occurs during a gap in either input clock. 32 Rev. 1.1 Si5347/46 5.7. Fault Monitoring All four input clocks (IN0, IN1, IN2, IN3) are monitored for LOS and OOF as shown in Figure 17. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLLs. Each of the DSPLLs also has an LOL indicator, which is asserted when synchronization is lost with their selected input clock. XA XB Si5347 OSC LOS DSPLL A LOL PD LPF ÷M IN0 IN0 IN1 IN1 IN2 P ÷ 0n P0d LOS P1n P1d LOS ÷ P2n P2d LOS OOF Precision Fast ÷ P3n P3d LOS OOF Precision Fast ÷ IN2 Precision OOF Fast OOF DSPLL B LOL PD Precision Fast LPF ÷M DSPLL C LOL PD IN3 IN3 LPF ÷M DSPLL D LOL PD LPF ÷M Figure 17. Si5347 Fault Monitors 5.7.1. Input LOS Detection The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An option to disable any of the LOS monitors is also available. Monitor Sticky LOS LOS LOS en Live Figure 18. LOS Status Indicators Rev. 1.1 33 Si5347/46 5.7.2. XA/XB LOS Detection A LOS monitor is available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when XAXB_LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB_LOS is detected. 5.7.3. OOF Detection Each input clock is monitored for frequency accuracy with respect to an OOF reference, which it considers as its “0_ppm” reference. This OOF reference can be selected as either: XA/XB pins Any input clock (IN0, IN1, IN2, IN3) The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in Figure 19. An option to disable either monitor is also available. The live OOF register always displays the current OOF state and its sticky register bit stays asserted until cleared. Monitor Sticky en Precision OOF LOS OOF Fast Live en Figure 19. OOF Status Indicator 5.7.3.1. Precision OOF Monitor The precision OOF monitor circuit measures the frequency of all input clocks to within ±1 ppm accuracy with respect to the selected OOF frequency reference. A valid input clock frequency is one that remains within the OOF frequency range, which is register configurable from ±2 ppm to ±500 ppm in steps of 2 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example is shown in Figure 20. In this case, the OOF monitor is configured with a valid frequency range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0 – IN3) as the 0 ppm OOF reference instead of the XA/XB pins is available. This option is register-configurable. OOF Declared fIN Hysteresis Hysteresis OOF Cleared -6 ppm (Set) -4 ppm (Clear) 0 ppm OOF Reference +4 ppm (Clear) +6 ppm (Set) Figure 20. Example of Precise OOF Monitor Assertion and De-assertion Triggers 5.7.3.2. Fast OOF Monitor Because the precision OOF monitor needs to provide 1 ppm of frequency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by greater than ±4000 ppm. 34 Rev. 1.1 Si5347/46 5.7.4. LOL Detection There is an LOL monitor for each of the DSPLLs. The LOL monitor asserts an LOL register bit when a DSPLL has lost synchronization with its selected input clock. There is also a dedicated loss of lock pin that reflects the loss of lock condition for each of the DSPLLs (LOL_A, LOL_B, LOL_C, LOL_D). The LOL monitor functions by measuring the frequency difference between the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set) and another that clears the indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in Figure 21. The live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL pin reflects the current state of the LOL monitor. Si5347 Sticky LOS LOL Status Registers Live DSPLL D DSPLL C DSPLL B DSPLL A LOL_D LOL Monitor LOL_C LOL Clear t LOL_B LOL_A LOL Set DSPLL A fIN PD LPF ÷M Figure 21. LOL Status Indicators Each of the LOL frequency monitors has adjustable sensitivity, which is register-configurable from 0.1 ppm to 10000 ppm. Having two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is indicated when there is less than 0.2 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there is more than 2 ppm frequency difference is shown in Figure 22. Clear LOL Threshold Set LOL Threshold Lock Acquisition LOL Hysteresis Lost Lock LOCKED 0 0.2 2 20,000 Phase Detector Frequency Difference (ppm) Figure 22. LOL Set and Clear Thresholds Rev. 1.1 35 Si5347/46 An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using the ClockBuilderPro utility. 5.7.5. Interrupt Pin (INTR) An interrupt pin (INTR) indicates a change in state with any of the status indicators for any of the DSPLLs. All status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTR pin is reset by clearing the sticky status registers. mask IN0_LOS_STKY mask IN0 IN0_OOF_STKY mask IN1_LOS_STKY mask IN1 IN1_OOF_STKY mask IN2_LOS_STKY mask IN2 IN2_OOF_STKY INTR mask IN3_LOS_STKY mask IN3 IN3_OOF_STKY mask XAXB_LOS_STKY mask LOLA_STKY mask LOLB_STKY mask LOL LOLC_STKY mask LOLD_STKY mask HOLDA_STKY mask HOLDB_STKY mask HOLD HOLDC_STKY mask HOLDD_STKY Figure 23. Interrupt Triggers and Masks 36 Rev. 1.1 Si5347/46 5.8. Outputs The Si5347 supports up to eight differential output drivers and the Si5346 supports four. Each driver has a configurable voltage amplitude and common mode voltage covering a wide variety of differential signal formats including LVPECL, LVDS, HCSL, and CML. In addition to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing up to 16 single-ended outputs, or any combination of differential and single-ended outputs. 5.8.1. Output Crosspoint A crosspoint allows any of the output drivers to connect with any of the DSPLLs as shown in Figure 24. The crosspoint configuration is programmable and can be stored in NVM so that the desired output configuration is ready at power-up. Si5347A/B Output Crosspoint A B C D DSPLL A DSPLL B DSPLL C DSPLL D ÷R0 VDDO0 OUT0 OUT0 A B C D ÷R1 VDDO1 OUT1 OUT1 A B C D ÷R2 VDDO2 OUT2 OUT2 A B C D ÷R3 VDDO3 OUT3 OUT3 A B C D ÷R4 VDDO4 OUT4 OUT4 A B C D ÷R5 VDDO5 OUT5 OUT5 A B C D ÷R6 VDDO6 OUT6 OUT6 A B C D ÷R7 VDDO7 OUT7 OUT7 Figure 24. Si5347A/B DSPLL to Output Driver Crosspoint Rev. 1.1 37 Si5347/46 5.8.2. Differential Output Terminations Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling standards. The differential output drivers support both ac-coupled and dc-coupled terminations as shown in Figure 25. AC-coupled LVDS/LVPECL DC-coupled LVDS VDDO = 3.3V, 2.5V, 1.8V VDDO = 3.3V, 2.5V, 1.8V 50 OUTx OUTx 100 OUTx 100 OUTx 50 50 50 AC-coupled LVPECL DC-coupled LVCMOS 3.3V, 2.5V, 1.8V LVCMOS VDDO = 3.3V, 2.5V, 1.8V VDD – 1.3V VDDO = 3.3V, 2.5V 50 50 Rs OUTx OUTx OUTx 50 OUTx 50 50 Si5347/46 Si5347/46 Rs AC-coupled HCSL VDDRX VDDO = 3.3V, 2.5V, 1.8V R1 OUTx R1 50 OUTx Standard HCSL Receiver 50 Si5347/46 R2 R2 For VCM = 0.35V VDDRX R1 R2 3.3V 442 56.2 2.5V 332 59 1.8V 243 63.4 Figure 25. Supported Differential Output Terminations 38 Internally self-biased Si5347/46 Si5347/46 Rev. 1.1 50 Si5347/46 5.8.3. LVCMOS Output Terminations LVCMOS outputs are dc-coupled as shown in Figure 26. 3.3 V, 2.5 V, 1.8 V LVCMOS VDDO = 3.3 V, 2.5 V, 1.8 V 50 OUTx Rs OUTx 50 Si5347/46 Rs Figure 26. LVCMOS Output Terminations 5.8.4. Output Signal Format The differential output amplitude and common mode voltage are both fully programmable and compatible with a wide variety of signal formats, including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 20 single-ended outputs or any combination of differential and single-ended outputs. 5.8.5. Differential Output Amplitude Modes There are two selectable differential output amplitude modes: normal and low power. Each output can support a unique mode. Differential Normal Mode: When an output driver is configured in normal amplitude mode, its output amplitude is selectable as one of 8 settings ranging from 130 mVpp_se to 920 mVpp_se in increments of 100 mV. The output impedance in the normal mode is 100 differentialAny of the ac-coupled terminations shown in Figure 25 are supported in this mode. Differential Low Power Mode: When an output driver is configured in low power mode, its output amplitude is configurable as one of 8 settings ranging from 200 mVpp_se to 1600 mVpp_se in increments of 200 mV. The output driver is in high impedance mode and supports standard 50 PCB traces. Any of the ac-coupling terminations shown in Figure 25 are supported in this mode. 5.8.6. Programmable Common Mode Voltage For Differential Outputs The common mode voltage (VCM) for the differential normal and low power modes is programmable in 100 mV increments from 0.7 V to 2.3 V depending on the voltage available at the output’s VDDO pin. Setting the common mode voltage is useful when dc-coupling the output drivers. 5.8.7. LVCMOS Output Impedance Selection Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programmable output impedance selections for each VDDO options as shown in Table 15. Note that selecting a lower source impedance may result in higher output power consumption. Table 15. Typical Output Impedance (ZS) CMOS_DRIVE_Selection VDDO OUTx_CMOS_DRV=1 OUTx_CMOS_DRV=2 OUTx_CMOS_DRV=3 3.3 V 38 30 22 2.5 V 43 35 24 1.8 V — 46 31 Rev. 1.1 39 Si5347/46 5.8.8. LVCMOS Output Signal Swing The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. Each output driver automatically detects the voltage on the VDDO pin to properly determine the correct output voltage. 5.8.9. LVCMOS Output Polarity When a driver is configured as an LVCMOS output, it generates a clock signal on both pins (OUTx and OUTx). By default the clock on the OUTx pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configurable, which enables complementary clock generation and/or inverted polarity with respect to other output drivers. 5.8.10. Output Enable/Disable The Si5347/46 allows enabling/disabling outputs by pin or register control, or a combination of both. Two output enable pins are available (OE0, OE1). The output enable pins can be mapped to any of the outputs (OUTx) through register configuration. By default OE0 controls all of the outputs while OE1 remains unmapped and has no effect until configured. Figure 27 shows an example of an output enable mapping scheme that is register configurable and can be stored in NVM as the default at power-up. Enabling and disabling outputs can also be controlled by register control. This allows disabling one or more output when the OE pin(s) has them enabled. By default the output enable register settings are configured to allow the OE pins to have full control. Si5346 Output Crosspoint DSPLL A Si5346 Output Crosspoint DSPLL A OUT0 A B ÷R0 A B ÷R1 OUT1 A B ÷R2 OUT2 OUT0 OUT1 A B ÷R0 A B ÷R1 OUT0 OUT0 OUT1 OUT1 OE0 DSPLL B A B ÷R3 OUT2 DSPLL B OUT3 A B ÷R2 OUT2 A B ÷R3 OUT3 OUT2 OUT3 OUT3 OE0 OE1 OE1 An example of a configurable output enable scheme. In this case OE0 controls the outputs associated with DSPLL A, while OE1 controls the outputs of DSPLL B. In its default state the OE0 pin enables/ disables all outputs. The OE1 pin is not mapped and has no effect on outputs. Figure 27. Example of Configuring Output Enable Pins 5.8.11. Output Disable During LOL By default a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option to disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover. 40 Rev. 1.1 Si5347/46 5.8.12. Output Disable During XAXB_LOS The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the DSPLLs. In the event of a crystal failure the device will assert an XAXB_LOS alarm. By default all outputs will be disabled during assertion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an XAXB_LOS alarm, but the frequency accuracy and stability will be indeterminate during this fault condition. 5.8.13. Output Driver State When Disabled The disabled state of an output driver is register configurable as disable low, disable high, or disable highimpedance. 5.8.14. Synchronous/Asynchronous Output Disable Outputs can be configured to disable synchronously or asynchronously. In synchronous disable mode the output will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. In asynchronous disable mode, the output clock will disable immediately without waiting for the period to complete. 5.8.15. Output Divider (R) Synchronization All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable phase alignment across all output drivers. Resetting the device using the RST pin or asserting the hard reset bit will have the same result. 5.9. Power Management Unused inputs, output drivers, and DSPLLs can be powered down when unused. Consult the Si5347/46 Family Reference Manual and ClockBuilder Pro configuration utility for details. 5.10. In-Circuit Programming The Si5347/46 is fully configurable using the serial interface (I2C or SPI). At power-up the device downloads its default register values from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD and VDDA pins. The NVM is two time writable. Once a new configuration has been written to NVM, the old configuration is no longer accessible. Refer to the Si5347/46 Family Reference Manual for a detailed procedure for writing registers to NVM. 5.11. Serial Interface Configuration and operation of the Si5347/46 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL pin selects I2C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in either 4-wire or 3-wire mode. See the Si5347/46 Family Reference Manual for details. 5.12. Custom Factory Preprogrammed Parts For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered with a specific configuration written into NVM. A factory pre-programmed part will generate clocks at power-up. Custom, factory-preprogrammed devices are available. Use the ClockBuilder Pro custom part number wizard (www.silabs.com/clockbuilderpro) to quickly and easily request and generate a custom part number for your configuration. In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local Silicon Labs sales representative. Samples of your pre-programmed device will typically ship in about two weeks. Rev. 1.1 41 Si5347/46 5.13. How to Enable Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices As with essentially all modern software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at www.silabs.com, you will be notified whenever changes are made and what the impact of those changes are. This update process will ultimately enable ClockBuilder Pro users to access all features and register setting values documented in this data sheet and the Si347/46 Family Reference Manual. However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register setting, but the feature or register setting is not yet available in CBPro, you must contact a Silicon Labs applications engineer for assistance. One example of this type of feature or custom setting is the customizable output amplitude and common voltages for the clock outputs. After careful review of your project file and requirements, the Silicon Labs applications engineer will email back your CBPro project file with your specific features and register settings enabled using what is referred to as the manual "settings override" feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in a CBPro design report are shown in Table 16. Table 16. Setting Overrides Location Customer Name Engineering Name Type Target Dec Value Hex Value 0x0535[0] FORCE_HOLD_PLLB OLA_HO_FORCE No NVM N/A 1 0x1 0x0B48[4:0] OOF_DIV_CLK_DIS OOF_DIV_CLK_DIS User OPN&EVB 31 0x1F Once you receive the updated design file, simply open it in CBPro. The device will begin operation after startup with the values in the NVM file. The flowchart for this process is shown in Figure 28. 42 Rev. 1.1 Si5347/46 End: Place sample order Start Do I need a pre‐programmed device with a feature or setting which is unavailable in ClockBuilder Pro? No Configure device using CBPro Generate Custom OPN in CBPro Yes Contact Silicon Labs Technical Support to submit & review your non‐standard configuration request & CBPro project file Receive updated CBPro project file from Silicon Labs with “Settings Override” Yes Load project file into CBPro and test Does the updated CBPro Project file match your requirements? Figure 28. Process for Requesting Non-Standard CBPro Features Rev. 1.1 43 Si5347/46 6. Register Map The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains frequently accessed registers, such as alarm status, resets, device identification, etc. Other pages contain registers that need less frequent access such as frequency configuration and general device settings. Refer to the Si534746 Family Reference Manual for a complete list of register descriptions and settings. 44 Rev. 1.1 Si5347/46 7. Pin Descriptions Si5347A/B 64QFN Top View VDD OE1 OUT3 OUT3 VDDO3 37 35 34 IN3 VDD 41 I2C_SEL IN3 42 38 IN0 43 39 IN0 44 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 IN0 IN0 IN3 IN3 VDD OUT7 OUT7 VDDO7 RSVD RSVD OUT6 OUT6 VDDO6 OUT5 OUT5 VDDO5 Si5346 44QFN Top View 48 FINC 2 47 LOL_D LOL_A 3 46 VDD IN1 1 33 LOS_XAXB LOL_B LOL_C 4 45 OUT4 IN1 2 32 5 44 OUT4 RST 3 31 VDD OUT2 RST X1 6 43 VDDO4 X1 4 30 OUT2 7 42 FDEC 5 29 VDDO2 XA 8 41 OE1 XA XB XB 9 40 VDDS X2 VDDA 7 VDDA GND Pad 36 1 IN1 40 IN1 GND Pad 28 LOL_A 27 LOL_B 8 26 VDDS 9 25 OUT1 6 17 18 19 20 21 22 INTR VDDO0 OUT0 OUT0 VDD NC 16 32 A1/SDO SDA/SDIO A0/CS RSVD RSVD VDDO0 OUT0 OUT0 LOS_XAXB DSPLL_SEL0 DSPLL_SEL1 NC VDDO1 OUT1 OUT1 VDD A0/CS VDDO2 15 OUT2 33 A1/SDO 34 14 IN2 15 SCLK 16 SCLK OUT2 13 35 12 VDDO1 IN2 14 OE0 SDA/SDIO 23 31 11 30 IN2 29 VDDO3 28 36 27 OUT1 VDDA 13 26 24 25 10 24 IN2 23 OUT3 22 37 21 INTR 12 20 I2C_SEL OUT3 19 38 18 39 17 X2 10 OE0 11 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 IN0 IN0 IN3 IN3 VDD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD OUT3 OUT3 VDDO3 Si5347C/D 64QFN Top View IN1 1 48 FINC IN1 2 47 LOL_D LOL_A 3 46 VDD LOL_B LOL_C 4 45 OUT2 5 44 OUT2 RST X1 6 43 VDDO2 7 42 FDEC XA 8 41 OE1 XB 9 40 VDDS X2 10 39 I2C_SEL OE0 11 38 OUT1 GND Pad 32 31 RSVD RSVD RSVD VDD A1/SDO SDA/SDIO A0/CS RSVD RSVD VDDO0 OUT0 OUT0 LOS_XAXB DSPLL_SEL0 DSPLL_SEL1 NC Rev. 1.1 30 RSVD 29 33 28 16 27 RSVD SCLK 26 34 25 15 24 RSVD IN2 23 35 22 14 21 VDDO1 IN2 20 OUT1 36 19 37 13 18 12 17 INTR VDDA 45 Si5347/46 Table 17. Si5347/46 Pin Descriptions1 Pin Name Pin Number Si5347A/B Si5347C/D Si5346 Pin Type2 Function Inputs XA 8 8 5 I XB 9 9 6 I X1 7 7 4 I X2 10 10 7 I IN0 63 63 43 I IN0 64 64 44 I IN1 1 1 1 I IN1 2 2 2 I IN2 14 14 10 I IN2 15 15 11 I IN3 61 61 41 I IN3 62 62 42 I Crystal Input. Input pin for external crystal (XTAL). Alternatively these pins can be driven with an external reference clock (REFCLK). An internal register bit selects XTAL or REFCLK mode. Default is XTAL mode. XTAL Ground. Connect these pins directly to the XTAL ground pins. X1, X2, and the XTAL ground pins should be separated from the PCB ground plane. Refer to the Si5347/46 Family Reference Manual for layout guidelines. These pins should be left disconnected when connecting XA/XB pins to an external reference clock (REFCLK). Clock Inputs. These pins accept an input clock for synchronizing the device. They support both differential and single-ended clock signals. Refer to “5.6.4. Input Configuration and Terminations” for input termination options. These pins are high-impedance and must be terminated externally. The negative side of the differential input must be grounded when accepting a single-ended clock. Notes: 1. Refer to the Si5347/46 Family Reference Manual for more information on register setting names. 2. I = Input, O = Output, P = Power. 3. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation. 4. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. 46 Rev. 1.1 Si5347/46 Table 17. Si5347/46 Pin Descriptions1 (Continued) Pin Name Pin Number Si5347A/B Si5347C/D Si5346 Pin Type2 Function Outputs OUT0 24 24 20 O OUT0 23 23 19 O OUT1 31 38 25 O OUT1 30 37 24 O OUT2 35 45 31 O OUT2 34 44 30 O OUT3 38 51 36 O OUT3 37 50 35 O OUT4 45 — — O OUT4 44 — — O OUT5 51 — — O OUT5 50 — — O OUT6 54 — — O OUT6 53 — — O OUT7 59 — — O OUT7 58 — — O Output Clocks. These output clocks support a programmable signal amplitude and common mode voltage. Desired output signal format is configurable using register control. Termination recommendations are provided in “5.8.2. Differential Output Terminations” and “5.8.3. LVCMOS Output Terminations” Unused outputs should be left unconnected. Notes: 1. Refer to the Si5347/46 Family Reference Manual for more information on register setting names. 2. I = Input, O = Output, P = Power. 3. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation. 4. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. Rev. 1.1 47 Si5347/46 Table 17. Si5347/46 Pin Descriptions1 (Continued) Pin Name Pin Number Si5347A/B Si5347C/D Si5346 Pin Type2 Function Serial Interface I2C Select. This pin selects the serial interface mode as I2C (I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is internally pulled high. See Note 3. I2C_SEL 39 39 38 I SDA/ SDIO 18 18 13 I/O Serial Data Interface. This is the bidirectional data pin (SDA) for the I2C mode, or the bidirectional data pin (SDIO) in the 3-wire SPI mode, or the input data pin (SDI) in 4-wire SPI mode. When in I2C mode, this pin must be pulled-up using an external resistor of > 1 k. No pull-up resistor is needed when in SPI mode. See Note 3. A1/SDO 17 17 15 I/O Address Select 1/Serial Data Output. In I2C mode this pin functions as the A1 address input pin. In 4-wire SPI mode this is the serial data output (SDO) pin. See Note 3. SCLK 16 16 14 I Serial Clock Input. This pin functions as the serial clock input for both I2C and SPI modes. When in I2C mode, this pin must be pulled-up using an external resistor of > 1 k. No pull-up resistor is needed when in SPI mode. See Note 3. A0/CS 19 19 16 I Address Select 0/Chip Select. This pin functions as the hardware controlled address A0 in I2C mode. In SPI mode, this pin functions as the chip select input (active low). This pin is internally pulled-up. See Note 3. Notes: 1. Refer to the Si5347/46 Family Reference Manual for more information on register setting names. 2. I = Input, O = Output, P = Power. 3. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation. 4. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. 48 Rev. 1.1 Si5347/46 Table 17. Si5347/46 Pin Descriptions1 (Continued) Pin Name Pin Number Si5347A/B Si5347C/D Si5346 Pin Type2 Function Control/Status INTR 12 12 17 O Interrupt. This pin is asserted low when a change in device status has occurred. It should be left unconnected when not in use. See Note 3. RST 6 6 3 I Device Reset. Active low input that performs power-on reset (POR) of the device. Resets all internal logic to a known state and forces the device registers to their default values. Clock outputs are disabled during reset. This pin is internally pulled-up. See Note 3. Output Enable 0. This pin is used to enable (when held low) and disable (when held high) the output clocks. By default this pin controls all outputs. It can also be configured to control a subset of outputs. See section “5.8.10. Output Enable/Disable” for details. This pin is internally pulled-down. See Note 3. OE0 11 11 12 OE1 41 41 — Output Enable 1. (Si5347) This is an additional output enable pin that can be configured to control a subset of outputs. By default it has no control on the outputs until configured. See section “5.8.10. Output Enable/Disable” for details. There is no internal pull-up/pulldown for this pin. See Note 4. This pin must be pulled up or down externally (do not leave floating when not in use). — — 37 Output Enable 1. (Si5346) This is an additional output enable pin that can be configured to control a subset of outputs. By default it has no control on the outputs until configured. See section “5.8.10. Output Enable/Disable” for details. This pin is internally pulleddown. See Note 3. LOL_A 3 3 28 O LOL_B 4 4 27 O LOL_C 5 5 — O LOL_D 47 47 — O LOS_XAXB 25 25 33 O Status Pins. This pin indicates a loss of signal alarm on the XA/XB pins. This either indicates a XTAL failure or a loss of external signal on the XA/XB pins. This pin can be left unconnected when unused. Si5347: See Note 3, Si5346: See Note 3. DSPLL_SEL0 26 26 — I DSPLL_SEL1 27 27 — I DSPLL Select Pins (Si5347 only). These pins are used in conjunction with the FINC and FDEC pins. The DSPLL_SEL[1:0] pins determine which DSPLL is affected by a frequency change using the FINC and FDEC pins. See section “5.4. Digitally-Controlled Oscillator (DCO) Mode” for details. These pins are internally pulled-down. See Note 3. I Loss Of Lock_A/B/C/D. These output pins indicate when DSPLL A, B, C, D is out-of-lock (low) or locked (high). They can be left unconnected when not in use. Si5347: See Note 3, Si5346: See Note 4. Notes: 1. Refer to the Si5347/46 Family Reference Manual for more information on register setting names. 2. I = Input, O = Output, P = Power. 3. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation. 4. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. Rev. 1.1 49 Si5347/46 Table 17. Si5347/46 Pin Descriptions1 (Continued) Pin Name Pin Number Si5347A/B Si5347C/D Si5346 Pin Type2 Function FDEC 42 42 — I Frequency Decrement Pin (Si5347 only). This pin is used to stepdown the output frequency of a selected DSPLL. The frequency change step size is register configurable. The DSPLL that is affected by the frequency change is determined by the DSPLL_SEL[1:0] pins. See Note 4. This pin must be pulled up or down externally (do not leave floating when not in use). FINC 48 48 — I Frequency Increment Pin (Si5347 only). This pin is used to stepup the output frequency of a selected DSPLL. The frequency change step size is register configurable. The DSPLL that is affected by the frequency change is determined by the DSPLL_SEL[1:0] pins. See Note 3. This pin is pulled low internally and can be left unconnected when not in use. RSVD 20 20 — — 21 21 — — — 29 — — — 30 — — — 31 — — — 33 — — — 34 — — — 35 — — — 52 — — — 53 — — — 54 — — 55 55 — — 56 56 — — — 57 — — — 58 — — — 59 — — 28 28 22 — NC Reserved. These pins are connected to the die. Leave disconnected. No Connect. These pins are not connected to the die. Leave disconnected. Notes: 1. Refer to the Si5347/46 Family Reference Manual for more information on register setting names. 2. I = Input, O = Output, P = Power. 3. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation. 4. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. 50 Rev. 1.1 Si5347/46 Table 17. Si5347/46 Pin Descriptions1 (Continued) Pin Name Pin Number Si5347A/B Si5347C/D Si5346 Pin Type2 P Core Supply Voltage. The device core operates from a 1.8 V supply. See the Si5347/46 Family Reference Manual for power supply filtering recommendations. A 0402 1 µF capacitor should be placed very near each of these pins. Core Supply Voltage 3.3 V. This core supply pin requires a 3.3 V power source. See the Si5347/46 Family Reference Manual for power supply filtering recommendations. A 0402 1 µF capacitor should be placed very near each of these pins. Function Power VDD 32 32 21 46 46 32 60 60 39 — — 40 13 13 8 P — — 9 P VDDS 40 40 26 P Status Output Voltage. The voltage on this pin determines VOL/ VOH on the Si5346 LOL_A and LOL_B outputs. On the Si5347, this pin determines VIL/VIH for the FDEC and OE1 inputs. Connect to either 3.3 V or 1.8 V. A 0.1 µF bypass capacitor should be placed very close to this pin. VDDO0 22 22 18 P VDDO1 29 36 23 P VDDO2 33 43 29 P VDDO3 36 49 34 P VDDO4 43 — — P Output Clock Supply Voltage 0–7. Supply voltage (3.3 V, 2.5 V, 1.8 V) for OUTn, OUTn outputs. A 0.1 uF bypass capacitor should be placed very close to this pin. Leave VDDO pins of unused output drivers unconnected. An alternate option is to connect the VDDO pin to a power supply and disable the output driver to minimize current consumption. A 0402 1 µF capacitor should be placed very near each of these pins. VDDO5 49 — — P VDDO6 52 — — P VDDO7 57 — — P GND PAD — — — P VDDA Ground Pad. This pad provides connection to ground and must be connected for proper operation. Use as many vias as practical and keep the via length to an internal ground plan as short as possible. Notes: 1. Refer to the Si5347/46 Family Reference Manual for more information on register setting names. 2. I = Input, O = Output, P = Power. 3. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation. 4. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. Rev. 1.1 51 Si5347/46 8. Ordering Guide Ordering Part Number Number Of Number of DSPLLs Outputs Si5347A-B-GM1,2 Si5347C-B-GM 0.0001 to 712.5 MHz 4 Si5346A-B-GM1,2 Si5346B-B-GM 0.0001 to 350 MHz 4 Si5347D-B-GM1,2 1,2 Package RoHS-6, Pb-Free Temp Range Yes –40 to 85 °C — — — — 0.0001 to 712.5 MHz 8 Si5347B-B-GM1,2 1,2 Output Clock Frequency Range 0.0001 to 350 MHz 0.0001 to 712.5 MHz 2 4 64-Lead 9x9 QFN 0.0001 to 350 MHz Si5347-EVB — — — Si5346-EVB — — — 44-Lead 7x7 QFN Evaluation Board Notes: 1. Add an R at the end of the device part number to denote tape and reel ordering options. 2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by the ClockBuilder Pro software. Part number format is: Si5347A-Bxxxxx-GM or Si5346A-Bxxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed configuration. 8.1. Ordering Part Number Fields Si534fg-Rxxxxx-GM Timing product family f = Multi-PLL clock family member (7, 6) g = Device grade (A, B, C, D) Product Revision* Custom ordering part number (OPN) sequence ID** Package, ambient temperature range (QFN, -40°C to +85°C) *See Ordering Guide table for current product revision ** 5 digits; assigned by ClockBuilder Pro 52 Rev. 1.1 Si5347/46 9. Package Outlines 9.1. Si5347 9x9 mm 64-QFN Package Diagram Figure 29 illustrates the package details for the Si5347. Table 18 lists the values for the dimensions shown in the illustration. Figure 29. 64-Pin Quad Flat No-Lead (QFN) Table 18. Package Dimensions Dimension Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 9.00 BSC 5.10 5.20 e 0.50 BSC E 9.00 BSC 5.30 E2 5.10 5.20 5.30 L 0.30 0.40 0.50 aaa — — 0.15 bbb — — 0.10 ccc — — 0.08 ddd — — 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.1 53 Si5347/46 9.2. Si5346 7x7 mm 44-QFN Package Diagram Figure 30 illustrates the package details for the Si5346. Table 19 lists the values for the dimensions shown in the illustration. Figure 30. 44-Pin Quad Flat No-Lead (QFN) Table 19. Package Dimensions Dimension Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 7.00 BSC 5.10 5.20 e 0.50 BSC E 7.00 BSC 5.30 E2 5.10 5.20 5.30 L 0.30 0.40 0.50 aaa — — 0.15 bbb — — 0.10 ccc — — 0.08 ddd — — 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 54 Rev. 1.1 Si5347/46 10. PCB Land Pattern Figure 31 illustrates the PCB land pattern details for the devices. Table 20 lists the values for the dimensions shown in the illustration. Refer to the Si5347-46 Family Reference Manual for information about thermal via recommendations. Si5347 Si5346 Figure 31. PCB Land Pattern Table 20. PCB Land Pattern Dimensions Dimension Si5347 (Max) Si5346 (Max) C1 8.90 6.90 C2 8.90 6.90 E 0.50 0.50 X1 0.30 0.30 Y1 0.85 0.85 X2 5.30 5.30 Y2 5.30 5.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication Allowance of 0.05 mm. Solder Mask Design 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 8. A 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad. Card Assembly 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.1 55 Si5347/46 11. Top Marking Si5347gRxxxxx-GM YYWWTTTTTT e4 TW Line Characters 1 Si5347gSi5346g- 2 Rxxxxx-GM 3 YYWWTTTTTT 4 Description Base part number and Device Grade. Si5347: Quad PLL; 64-QFN Si5346: Dual PLL; 44-QFN g = Device Grade. See section “8. Ordering Guide” for more information. – = Dash character. R = Product revision. (See section “8. Ordering Guide” for current revision.) xxxxx = Customer specific NVM sequence number. (Optional NVM code assigned for custom, factory pre-programmed devices. Characters are not included for standard, factory default configured devices). See section “8. Ordering Guide” for more information. -GM = Package (QFN) and temperature range (–40 to +85 °C). YYWW = Characters correspond to the year (YY) and work week (WW) of package assembly. TTTTTT = Manufacturing trace code. Circle w/ 1.6 mm (64-QFN) or Pin 1 indicator; left-justified 1.4 mm (44-QFN) diameter e4 TW 56 Si5346gRxxxxx-GM YYWWTTTTTT TW e4 Pb-free symbol; Center-Justified TW = Taiwan; Country of Origin (ISO Abbreviation) Rev. 1.1 Si5347/46 12. Device Errata Please log in or register at www.silabs.com to access the device errata document. Rev. 1.1 57 Si5347/46 DOCUMENT CHANGE LIST Revision 0.9 to Revision 0.95 Removed advanced product information revision history. Updated Ordering Guide and changed references to revision B. Updated parametric tables 2,3,5,6,7,8 to reflect production characterization release. Updated terminology to align with ClockBuilder Pro software. Corrected Table 3 references and specifications from "LVCMOS — DC-coupled" to "Pulsed CMOS — DCcoupled". Corrected Table 9: I2C data hold time specification to 100 ns from 5 µs. Revision 0.95 to Revision 1.0 Added 4-Output Si5347C and Si5347D grade devices to the data sheet. Corrected AC Test Configuration schematic in Tables 2 and 6. Corrected minimum input frequency down to 0.008 MHz in Table 3. Corrected XAXB VIN_DIFF minimum input voltage swing in Table 3. Corrected VIN input voltage swing and split into VIN_DIFF and VIN_SE for differential and singleended inputs in Table 3. Added FINC/FDEC maximum update rates of 1 MHz in Table 4. Added common-mode voltage for 1.8 V sub-LVDS in Table 5. Added typical crosstalk spec for Si5346 in Table 5. Updated TSK, output-to-output skew, in Table 5. Updated ZO, differential output impedance for Low Power Mode in Table 5. Updated LVPECL VOUT maximum value in Table 5. Adjusted LVCMOS VOH specification in Table 6. Corrected tSTART, tACQ, and tRDY in Table 8. Updated SPI timing diagrams and specifications and removed SPI rise/fall time in Tables 10 and 11. Revision 1.0 to Revision 1.1 58 Corrected Si5347C/D pin list numbers in Table 17 to match the pinout. Rev. 1.1 Si5347/46 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.siliconlabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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