Si861x/2x Data Sheet Low-Power Single and Dual-Channel Digital Isolators Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages over legacy isolation technologies. The operating parameters of these products remain stable across wide temperature ranges and throughout device service life for ease of design and highly uniform performance. All device versions have Schmitt trigger inputs for high noise immunity and only require VDD bypass capacitors. Data rates up to 150 Mbps are supported, and all devices achieve propagation delays of less than 10 ns. Ordering options include a choice of isolation ratings (2.5, 3.75 and 5 kV) and a selectable fail-safe operating mode to control the default output state during power loss. All products are safety certified by UL, CSA, VDE, and CQC, and products in wide-body packages support reinforced insulation withstanding up to 5 kVRMS. Applications • Industrial automation systems • Medical electronics • Hybrid electric vehicles • Isolated switch mode supplies • Isolated ADC, DAC • Motor control • Power inverters • Communications systems Safety Regulatory Approvals • UL 1577 recognized • Up to 5000 VRMS for 1 minute • CSA component notice 5A approval • IEC 60950-1, 61010-1, 60601-1 (reinforced insulation) • VDE certification conformity • Si862xxT options certified to reinforced VDE 0884-10 • All other options certified to IEC 60747-5-5 and reinforced 60950-1 • CQC certification approval • GB4943.1 KEY FEATURES • High-speed operation • DC to 150 Mbps • No start-up initialization required • Wide Operating Supply Voltage • 2.5–5.5 V • Up to 5000 VRMS isolation • Reinforced VDE 0884-10, 10 kV surgecapable (Si862xxT) • 60-year life at rated working voltage • High electromagnetic immunity • Ultra low power (typical) 5 V Operation • 1.6 mA per channel at 1 Mbps • 5.5 mA per channel at 100 Mbps 2.5 V Operation • 1.5 mA per channel at 1 Mbps • 3.5 mA per channel at 100 Mbps • Schmitt trigger inputs • Selectable fail-safe mode • Default high or low output (ordering option) • Precise timing (typical) • 10 ns propagation delay • 1.5 ns pulse width distortion • 0.5 ns channel-channel skew • 2 ns propagation delay skew • 5 ns minimum pulse width • Transient Immunity 50 kV/µs • AEC-Q100 qualification • Wide temperature range • –40 to 125 °C • RoHS-compliant packages • SOIC-16 wide body • SOIC-8 narrow body silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 Si861x/2x Data Sheet Ordering Guide 1. Ordering Guide Table 1.1. Ordering Guide for Valid OPNs1, 2 Ordering Part Number (OPN) Number of Inputs VDD1 Side Number of Inputs VDD2 Side Max Data Rate (Mbps) Default Output State Isolation Rating (kV) Temp (C) Package Si8610BB-B-IS 1 0 150 Low 2.5 –40 to 125 °C SOIC-8 Si8610BC-B-IS 1 0 150 Low 3.75 –40 to 125 °C SOIC-8 Si8610EC-B-IS 1 0 150 High 3.75 –40 to 125 °C SOIC-8 Si8610BD-B-IS 1 0 150 Low 5.0 –40 to 125 °C WB SOIC-16 Si8610ED-B-IS 1 0 150 High 5.0 –40 to 125 °C WB SOIC-16 Si8620BB-B-IS 2 0 150 Low 2.5 –40 to 125 °C SOIC-8 Si8620EB-B-IS 2 0 150 High 2.5 –40 to 125 °C SOIC-8 Si8620BC-B-IS 2 0 150 Low 3.75 –40 to 125 °C SOIC-8 Si8620EC-B-IS 2 0 150 High 3.75 –40 to 125 °C SOIC-8 Si8620BD-B-IS 2 0 150 Low 5.0 –40 to 125 °C WB SOIC-16 Si8620ED-B-IS 2 0 150 High 5.0 –40 to 125 °C WB SOIC-16 Si8621BB-B-IS 1 1 150 Low 2.5 –40 to 125 °C SOIC-8 Si8621BC-B-IS 1 1 150 Low 3.75 –40 to 125 °C SOIC-8 Si8621EC-B-IS 1 1 150 High 3.75 –40 to 125 °C SOIC-8 Si8621BD-B-IS 1 1 150 Low 5.0 –40 to 125 °C WB SOIC-16 Si8621ED-B-IS 1 1 150 High 5.0 –40 to 125 °C WB SOIC-16 Si8622BB-B-IS 1 1 150 Low 2.5 –40 to 125 °C SOIC-8 Si8622EB-B-IS 1 1 150 High 2.5 –40 to 125 °C SOIC-8 Si8622BC-B-IS 1 1 150 Low 3.75 –40 to 125 °C SOIC-8 Si8622EC-B-IS 1 1 150 High 3.75 –40 to 125 °C SOIC-8 Si8622BD-B-IS 1 1 150 Low 5.0 –40 to 125 °C WB SOIC-16 Si8622ED-B-IS 1 1 150 High 5.0 –40 to 125 °C WB SOIC-16 Product Options with Reinforced VDE 0884-10 Rating with 10 kV Surge Capability Si8620BT-IS 2 0 150 Low 5.0 –40 to 125 °C WB SOIC-16 Si8620ET-IS 2 0 150 High 5.0 –40 to 125 °C WB SOIC-16 Si8621BT-IS 1 1 150 Low 5.0 –40 to 125 °C WB SOIC-16 Si8621ET-IS 1 1 150 High 5.0 –40 to 125 °C WB SOIC-16 Si8622BT-IS 1 1 150 Low 5.0 –40 to 125 °C WB SOIC-16 Si8622ET-IS 1 1 150 High 5.0 –40 to 125 °C WB SOIC-16 Note: 1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. 2. “Si” and “SI” are used interchangeably. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 1 Si861x/2x Data Sheet System Overview 2. System Overview 2.1 Theory of Operation The operation of an Si861x/2x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si861x/2x channel is shown in the figure below. Figure 2.1. Simplified Channel Diagram A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and improved immunity to magnetic fields. See the following figure for more details. Figure 2.2. Modulation Scheme silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 2 Si861x/2x Data Sheet System Overview 2.2 Eye Diagram The figure below illustrates an eye diagram taken on an Si8610. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8610 were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width distortion and 350 ps peak jitter were exhibited. Figure 2.3. Eye Diagram silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 3 Si861x/2x Data Sheet Device Operation 3. Device Operation Device behavior during start-up, normal operation, and shutdown is shown in Figure 3.1 Device Behavior during Normal Operation on page 5, where UVLO+ and UVLO– are the respective positive-going and negative-going thresholds. Refer to the following table to determine outputs when power supply (VDD) is not present. Table 3.1. Si86xx Logic Operation VI Input1, 2 VDDI State1, 3, 4 VDDO State1, 3, 4 VO Output1, 2 H P P H L P P L X5 UP P L6 H6 X5 P UP Undetermined Comments Normal operation. Upon transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 µs. Upon transition of VDDO from unpowered to powered, VO returns to the same state as VI within 1 µs. Note: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. 2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance. 3. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V. 4. “Unpowered” state (UP) is defined as VDD = 0 V. 5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current. 6. See Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). Some devices have default output state = H, and some have default output state = L, depending on the ordering part number (OPN). For default high devices, the data channels have pull-ups on inputs/outputs. For default low devices, the data channels have pull-downs on inputs/outputs. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 4 Si861x/2x Data Sheet Device Operation 3.1 Device Startup Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow the states of inputs. 3.2 Undervoltage Lockout Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply. Figure 3.1. Device Behavior during Normal Operation 3.3 Layout Recommendations To ensure safety in the end-user application, high-voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low-voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 4.6 Insulation and Safety-Related Specifications on page 21 and Table 4.8 IEC 60747-5-5 Insulation Characteristics for Si86xxxx1 on page 22 detail the working voltage and creepage/clearance capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the endsystem specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator. 3.3.1 Supply Bypass The Si861x/2x family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 Ω ) in series with the inputs and outputs if the system is excessively noisy. 3.3.2 Output Pin Termination The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the onchip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 3.4 Fail-Safe Operating Mode Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered) can either be a logic high or logic low when the output supply is powered. See Table 3.1 Si86xx Logic Operation on page 4 and 1. Ordering Guide for more information. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 5 Si861x/2x Data Sheet Device Operation 3.5 Typical Performance Characteristis The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to 4. Electrical Specifications for actual specification limits. Figure 3.2. Si8610 Typical VDD1 Supply Current vs. Data Rate Figure 3.3. Si8610 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.50 V Operation 5, 3.3, and 2.50 V Operation (15 pF Load) Figure 3.4. Si8620 Typical VDD1 Supply Current vs. Data Rate Figure 3.5. Si8620 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.50 V Operation 5, 3.3, and 2.50 V Operation (15 pF Load) Figure 3.6. Si8621 Typical VDD1 or VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.50 V Operation (15 pF Load) silabs.com | Smart. Connected. Energy-friendly. Figure 3.7. Si8622 Typical VDD1 or VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.50 V Operation (15 pF Load) Rev. 1.6 | 6 Si861x/2x Data Sheet Device Operation Figure 3.8. Propagation Delay vs. Temperature (5.0 V Data) silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 7 Si861x/2x Data Sheet Electrical Specifications 4. Electrical Specifications Table 4.1. Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Ambient Operating Temperature1 TA –40 25 1251 °C Supply Voltage VDD1 2.5 — 5.5 V VDD2 2.5 — 5.5 V Note: 1. The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage. Table 4.2. Electrical Characteristics1 Parameter Symbol Test Condition Min Typ Max Unit VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V Negative-Going Input Threshold VT– All inputs falling 1.0 1.23 1.4 V Input Hysteresis VHYS 0.38 0.44 0.50 V High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1, VDD2 – 0.4 4.8 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V — — ±10 µA — — ±15 — 50 — Input Leakage Current Si86xxxB/C/D IL Si86xxxT Output Impedance2 ZO Ω DC Supply Current (All Inputs 0 V or at Supply) Si8610Bx, Ex VDD1 VI = 0(Bx), 1(Ex) — 0.6 1.2 VDD2 VI = 0(Bx), 1(Ex) — 0.8 1.5 VDD1 VI = 1(Bx), 0(Ex) — 1.8 2.9 VDD2 VI = 1(Bx), 0(Ex) — 0.8 1.5 silabs.com | Smart. Connected. Energy-friendly. mA Rev. 1.6 | 8 Si861x/2x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max VDD1 VI = 0(Bx), 1(Ex) — 0.8 1.4 VDD2 VI = 0(Bx), 1(Ex) — 1.4 2.2 VDD1 VI = 1(Bx), 0(Ex) — 3.3 5.3 VDD2 VI = 1(Bx), 0(Ex) — 1.4 2.2 VDD1 VI = 0(Bx), 1(Ex) — 1.2 1.9 VDD2 VI = 0(Bx), 1(Ex) — 1.2 1.9 VDD1 VI = 1(Bx), 0(Ex) — 2.4 3.8 VDD2 VI = 1(Bx), 0(Ex) — 2.4 3.8 VDD1 VI = 0(Bx), 1(Ex) — 2.6 4.2 VDD2 VI = 0(Bx), 1(Ex) — 3.3 5.3 VDD1 VI = 1(Bx), 0(Ex) — 4.0 6.4 VDD2 VI = 1(Bx), 0(Ex) — 4.8 7.7 VDD1 — 1.2 2.0 VDD2 — 0.9 1.5 VDD1 — 2.1 3.1 VDD2 — 1.6 2.4 VDD1 — 1.9 2.9 VDD2 — 1.9 2.9 VDD1 — 3.4 5.1 VDD2 — 4.2 6.2 VDD1 — 1.2 2.0 VDD2 — 1.2 2.0 VDD1 — 2.1 3.1 VDD2 — 2.2 3.3 Unit Si8620Bx, Ex mA Si8621Bx, Ex mA Si8622Bx, Ex mA 1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs) Si8610Bx, Ex mA Si8620Bx, Ex mA Si8621Bx, Ex mA Si8622Bx, Ex mA 10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs) Si8610Bx, Ex mA Si8620Bx, Ex silabs.com | Smart. Connected. Energy-friendly. mA Rev. 1.6 | 9 Si861x/2x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit VDD1 — 2.2 3.3 mA VDD2 — 2.2 3.3 VDD1 — 3.7 5.5 VDD2 — 4.4 6.7 Si8621Bx, Ex Si8622Bx, Ex mA 100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs) Si8610Bx, Ex VDD1 — 1.2 2.0 VDD2 — 4.8 6.7 VDD1 — 2.1 3.1 VDD2 — 8.9 12.5 VDD1 — 5.8 8.1 VDD2 — 5.8 8.1 VDD1 — 7.6 10.6 VDD2 — 8.2 11.4 Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 5.0 ns 5.0 8.0 13 ns — 0.2 4.5 ns tPSK(P-P) — 2.0 4.5 ns tPSK — 0.4 2.5 ns — 2.5 4.0 ns mA Si8620Bx, Ex mA Si8621Bx, Ex mA Si8622Bx, Ex mA Timing Characteristics Si861x/2x Bx, Ex Propagation Delay tPHL, tPLH Pulse Width Distortion |tPLH – tPHL| Propagation Delay Skew3 Channel-Channel Skew PWD See Figure 4.1 Propagation Delay Timing on page 12 See Figure 4.1 Propagation Delay Timing on page 12 All Models CL = 15 pF Output Rise Time silabs.com | Smart. Connected. Energy-friendly. tr See Figure 4.1 Propagation Delay Timing on page 12 Rev. 1.6 | 10 Si861x/2x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit CL = 15 pF Output Fall Time Peak Eye Diagram Jitter tf See Figure 4.1 Propagation Delay Timing on page 12 — 2.5 4.0 ns tJIT(PK) See Figure 2.3 Eye Diagram on page 3 — 350 — ps VI = VDD or 0 V VCM = 1500 V Common Mode Transient Immunity CMTI Si86xxxB/C/D Si86xxxT Start-up Time4 See Figure 4.2 Common-Mode Transient Immunity Test Circuit on page 12 tSU kV/µs 35 50 — 60 100 — — 15 40 µs Note: 1. VDD1 = 5 V ±10%; VDD2 = 5 V ±10%, TA = –40 to 125 °C 2. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces. 3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. Start-up time is the time period from the application of power to the appearance of valid data at the output. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 11 Si861x/2x Data Sheet Electrical Specifications Figure 4.1. Propagation Delay Timing Figure 4.2. Common-Mode Transient Immunity Test Circuit silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 12 Si861x/2x Data Sheet Electrical Specifications Table 4.3. Electrical Characteristics1 Parameter Symbol Test Condition Min Typ Max Unit VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V Negative-Going Input Threshold VT– All inputs falling 1.0 1.23 1.4 V Input Hysteresis VHYS 0.38 0.44 0.50 V High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1, VDD2 – 0.4 3.1 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V — — ±10 µA — — ±15 — 50 — Input Leakage Current Si86xxxB/C/D IL Si86xxxT Output Impedance2 ZO Ω DC Supply Current (All Inputs 0 V or at Supply) Si8610Bx, Ex VDD1 VI = 0(Bx), 1(Ex) — 0.6 1.2 VDD2 VI = 0(Bx), 1(Ex) — 0.8 1.5 VDD1 VI = 1(Bx), 0(Ex) — 1.8 2.9 VDD2 VI = 1(Bx), 0(Ex) — 0.8 1.5 VDD1 VI = 0(Bx), 1(Ex) — 0.8 1.4 VDD2 VI = 0(Bx), 1(Ex) — 1.4 2.2 VDD1 VI = 1(Bx), 0(Ex) — 3.3 5.3 VDD2 VI = 1(Bx), 0(Ex) — 1.4 2.2 VDD1 VI = 0(Bx), 1(Ex) — 1.2 1.9 VDD2 VI = 0(Bx), 1(Ex) — 1.2 1.9 VDD1 VI = 1(Bx), 0(Ex) — 2.4 3.8 VDD2 VI = 1(Bx), 0(Ex) — 2.4 3.8 mA Si8620Bx, Ex mA Si8621Bx, Ex silabs.com | Smart. Connected. Energy-friendly. mA Rev. 1.6 | 13 Si861x/2x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max VDD1 VI = 0(Bx), 1(Ex) — 2.6 4.2 VDD2 VI = 0(Bx), 1(Ex) — 3.3 5.3 VDD1 VI = 1(Bx), 0(Ex) — 4.0 6.4 VDD2 VI = 1(Bx), 0(Ex) — 4.8 7.7 VDD1 — 1.2 2.0 VDD2 — 0.9 1.5 VDD1 — 2.1 3.1 VDD2 — 1.6 2.4 VDD1 — 1.9 2.9 VDD2 — 1.9 2.9 VDD1 — 3.4 5.1 VDD2 — 4.2 6.2 VDD1 — 1.2 2.0 VDD2 — 1.0 1.8 VDD1 — 2.1 3.1 VDD2 — 1.9 2.8 VDD1 — 2.0 3.0 VDD2 — 2.0 3.0 VDD1 — 3.5 5.3 VDD2 — 4.3 6.4 Unit Si8622Bx, Ex mA 1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs) Si8610Bx, Ex mA Si8620Bx, Ex mA Si8621Bx, Ex mA Si8622Bx, Ex mA 10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs) Si8610Bx, Ex mA Si8620Bx, Ex mA Si8621Bx, Ex mA Si8622Bx, Ex mA 100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs) Si8610Bx, Ex VDD1 — 1.2 2.0 VDD2 — 3.4 5.1 silabs.com | Smart. Connected. Energy-friendly. mA Rev. 1.6 | 14 Si861x/2x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit VDD1 — 2.1 3.1 mA VDD2 — 6.3 8.8 VDD1 — 4.4 6.1 VDD2 — 4.4 6.1 VDD1 — 5.9 8.2 VDD2 — 6.6 9.3 Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 5.0 ns 5.0 8.0 13 ns — 0.2 4.5 ns tPSK(P-P) — 2.0 4.5 ns tPSK — 0.4 2.5 ns — 2.5 4.0 ns Si8620Bx, Ex Si8621Bx, Ex mA Si8622Bx, Ex mA Timing Characteristics Si861x/2x Bx, Ex Propagation Delay tPHL, tPLH Pulse Width Distortion |tPLH – tPHL| Propagation Delay Skew3 Channel-Channel Skew PWD See Figure 4.1 Propagation Delay Timing on page 12 See Figure 4.1 Propagation Delay Timing on page 12 All Models CL = 15 pF Output Rise Time tr See Figure 4.1 Propagation Delay Timing on page 12 CL = 15 pF Output Fall Time Peak Eye Diagram Jitter tf See Figure 4.1 Propagation Delay Timing on page 12 — 2.5 4.0 ns tJIT(PK) See Figure 2.3 Eye Diagram on page 3 — 350 — ps VI = VDD or 0 V VCM = 1500 V Common Mode Transient Immunity CMTI Si86xxxB/C/D Si86xxxT Start-up Time4 silabs.com | Smart. Connected. Energy-friendly. tSU See Figure 4.2 Common-Mode Transient Immunity Test Circuit on page 12 kV/µs 35 50 — 60 100 — — 15 40 µs Rev. 1.6 | 15 Si861x/2x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Note: 1. VDD1 = 3.3 V ±10%; VDD2 = 3.3 V ±10%, TA = –40 to 125 °C 2. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces. 3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. Start-up time is the time period from the application of power to the appearance of valid data at the output. Table 4.4. Electrical Characteristics1 Parameter Symbol Test Condition Min Typ Max Unit VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV Positive-Going Input Threshold VT+ All inputs rising 1.6 — 1.9 V Negative-Going Input Threshold VT– All inputs falling 1.1 — 1.4 V Input Hysteresis VHYS 0.40 0.45 0.50 V High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1, VDD2 – 0.4 2.3 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V — — ±10 µA — — ±15 — 50 — Input Leakage Current Si86xxxB/C/D IL Si86xxxT Output Impedance2 ZO Ω DC Supply Current (All Inputs 0 V or at Supply) Si8610Bx, Ex VDD1 VI = 0(Bx), 1(Ex) — 0.6 1.2 VDD2 VI = 0(Bx), 1(Ex) — 0.8 1.5 VDD1 VI = 1(Bx), 0(Ex) — 1.8 2.9 VDD2 VI = 1(Bx), 0(Ex) — 0.8 1.5 VDD1 VI = 0(Bx), 1(Ex) — 0.8 1.4 VDD2 VI = 0(Bx), 1(Ex) — 1.4 2.2 VDD1 VI = 1(Bx), 0(Ex) — 3.3 5.3 VDD2 VI = 1(Bx), 0(Ex) — 1.4 2.2 mA Si8620Bx, Ex silabs.com | Smart. Connected. Energy-friendly. mA Rev. 1.6 | 16 Si861x/2x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max VDD1 VI = 0(Bx), 1(Ex) — 1.2 1.9 VDD2 VI = 0(Bx), 1(Ex) — 1.2 1.9 VDD1 VI = 1(Bx), 0(Ex) — 2.4 3.8 VDD2 VI = 1(Bx), 0(Ex) — 2.4 3.8 VDD1 VI = 0(Bx), 1(Ex) — 2.6 4.2 VDD2 VI = 0(Bx), 1(Ex) — 3.3 5.3 VDD1 VI = 1(Bx), 0(Ex) — 4.0 6.4 VDD2 VI = 1(Bx), 0(Ex) — 4.8 7.7 VDD1 — 1.2 2.0 VDD2 — 0.9 1.5 VDD1 — 2.1 3.1 VDD2 — 1.6 2.4 VDD1 — 1.9 2.9 VDD2 — 1.9 2.9 VDD1 — 3.4 5.1 VDD2 — 4.2 6.2 VDD1 — 1.2 2.0 VDD2 — 1.0 1.6 VDD1 — 2.1 3.1 VDD2 — 1.7 2.6 VDD1 — 2.0 2.9 VDD2 — 2.0 2.9 Unit Si8621Bx, Ex mA Si8622Bx, Ex mA 1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs) Si8610Bx, Ex mA Si8620Bx, Ex mA Si8621Bx, Ex mA Si8622Bx, Ex mA 10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs) Si8610Bx, Ex mA Si8620Bx, Ex mA Si8621Bx, Ex silabs.com | Smart. Connected. Energy-friendly. mA Rev. 1.6 | 17 Si861x/2x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit VDD1 — 3.5 5.2 mA VDD2 — 4.2 6.3 Si8622Bx, Ex 100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs) Si8610Bx, Ex VDD1 — 1.2 2.0 VDD2 — 2.7 4.4 VDD1 — 2.1 3.1 VDD2 — 5.1 7.1 VDD1 — 3.7 5.2 VDD2 — 3.7 5.2 VDD1 — 5.2 7.3 VDD2 — 6.0 8.4 Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 5.0 ns 5.0 8.0 14 ns — 0.2 5.0 ns tPSK(P-P) — 2.0 5.0 ns tPSK — 0.4 2.5 ns — 2.5 4.0 ns mA Si8620Bx, Ex mA Si8621Bx, Ex mA Si8622Bx, Ex mA Timing Characteristics Si861x/2x Bx, Ex Propagation Delay tPHL, tPLH Pulse Width Distortion |tPLH – tPHL| Propagation Delay Skew3 Channel-Channel Skew PWD See Figure 4.1 Propagation Delay Timing on page 12 See Figure 4.1 Propagation Delay Timing on page 12 All Models CL = 15 pF Output Rise Time tr See Figure 4.1 Propagation Delay Timing on page 12 CL = 15 pF Output Fall Time Peak Eye Diagram Jitter silabs.com | Smart. Connected. Energy-friendly. tf See Figure 4.1 Propagation Delay Timing on page 12 — 2.5 4.0 ns tJIT(PK) See Figure 2.3 Eye Diagram on page 3 — 350 — ps Rev. 1.6 | 18 Si861x/2x Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit VI = VDD or 0 V VCM = 1500 V Common Mode Transient Immunity CMTI Si86xxxB/C/D Si86xxxT Start-up Time4 See Figure 4.2 Common-Mode Transient Immunity Test Circuit on page 12 tSU kV/µs 35 50 — 60 100 — — 15 40 µs Note: 1. VDD1 = 2.5 V ±5%; VDD2 = 2.5 V ±5%, TA = –40 to 125 °C 2. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces. 3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. Start-up time is the time period from the application of power to the appearance of valid data at the output. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 19 Si861x/2x Data Sheet Electrical Specifications Table 4.5. Regulatory Information1, 2, 3, 4 For All Product Options Except Si86xxxT CSA The Si861x/2x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. 61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. 60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage. VDE The Si861x/2x is certified according to IEC 60747-5-5. For more details, see File 5006301-4880-0001. 60747-5-5: Up to 1200 Vpeak for basic insulation working voltage. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. UL The Si861x/2x is certified under UL1577 component recognition program. For more details, see File E257455. Rated up to 5000 VRMS isolation voltage for basic protection. CQC The Si861x/2x is certified under GB4943.1-2011. For more details, see certificates CQC13001096110 and CQC13001096239. Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. For All Si86xxxT Product Options CSA Certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. 60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. VDE Certified according to VDE 0884-10. UL Certified under UL1577 component recognition program. For more details, see File E257455. Rated up to 5000 VRMS isolation voltage for basic protection. CQC Certified under GB4943.1-2011. Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage. Note: 1. Regulatory Certifications apply to 2.5 kVRMS rated devices, which are production tested to 3.0 kVRMS for 1 s. 2. Regulatory Certifications apply to 3.75 kVRMS rated devices, which are production tested to 4.5 kVRMS for 1 s. 3. Regulatory Certifications apply to 5.0 kVRMS rated devices, which are production tested to 6.0 kVRMS for 1 s. 4. For more information, see 1. Ordering Guide. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 20 Si861x/2x Data Sheet Electrical Specifications Table 4.6. Insulation and Safety-Related Specifications Parameter Symbol Test Condition Value Unit WB SOIC-16 NB SOIC-8 Nominal Air Gap (Clearance)1 L(IO1) 8.0 4.9 mm Nominal External Tracking1 L(IO2) 8.0 4.01 mm 0.014 0.014 mm 600 600 VRMS Minimum Internal Gap (Internal Clearance) Tracking Resistance PTI IEC60112 (Proof Tracking Index) Erosion Depth ED 0.019 0.019 mm Resistance (Input-Output)2 RIO 1012 1012 W Capacitance (Input-Output)2 CIO 2.0 2.0 pF 4.0 4.0 pF f = 1 MHz CI Input Capacitance3 Note: 1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-16 package and 8.5 mm minimum for the WB SOIC-16 package. UL does not impose a clearance and creepage minimum for component-level certifications. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-16 and 7.6 mm minimum for the WB SOIC-16 package. 2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 (1–4 on NB SOIC-8) are shorted together to form the first terminal, and pins 9–16 (5–8 on NB SOIC-8) are shorted together to form the second terminal. The parameters are then measured between these two terminals. 3. Measured from input pin to ground. Table 4.7. IEC 60664-1 Ratings Parameter Test Conditions Specification WB SOIC-16 NB SOIC-8 I I Basic Isolation Group Material Group Installation Classification Rated Mains Voltages < 150 VRMS I-IV I-IV Rated Mains Voltages < 300 VRMS I-IV I-III Rated Mains Voltages < 400 VRMS I-III I-II Rated Mains Voltages < 600 VRMS I-III I-II silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 21 Si861x/2x Data Sheet Electrical Specifications Table 4.8. IEC 60747-5-5 Insulation Characteristics for Si86xxxx1 Parameter Symbol Maximum Working Insulation Voltage VIORM Input to Output Test Voltage VPR Test Condition Characteristic Unit WB SOIC-16 NB SOIC-8 1200 630 Vpeak 2250 1182 Vpeak 6000 6000 Vpeak Si86xxxT tested with magnitude 6250 V x 1.6 = 10 kV 6250 — Vpeak Si86xxxB/C/D tested with 4000 V 4000 4000 2 2 >109 >109 Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) Transient Overvoltage VIOTM t = 60 sec Tested per IEC 60065 with surge voltage of 1.2 µs/50 µs VIOSM Surge Voltage Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V RS Ω Note: 1. Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21. Table 4.9. IEC Safety Limiting Values1 Parameter Symbol Case Temperature TS Safety Input, Output, or Supply Current IS Test Condition θJA = 140 °C/W (NB SOIC-8) Max Unit WB SOIC-16 NB SOIC-8 150 150 °C 220 160 mA 150 150 mW 100 °C/W (WB SOIC-16) VI = 5.5 V, TJ = 150 °C, TA = 25 °C Device Power Dissipation2 PD Note: 1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 4.3 (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-5/VDE 0884-10, as Applies on page 23 and Figure 4.4 (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-5/VDE 0884-10, as Applies on page 23. 2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V; TJ = 150 ºC; CL = 15 pF, input a 150 Mbps 50% duty cycle square wave. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 22 Si861x/2x Data Sheet Electrical Specifications Table 4.10. Thermal Characteristics Parameter IC Junction-to-Air Thermal Resistance Symbol WB SOIC-16 NB SOIC-8 Unit θJA 100 140 °C/W Figure 4.3. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-5/VDE 0884-10, as Applies Figure 4.4. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-5/VDE 0884-10, as Applies silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 23 Si861x/2x Data Sheet Electrical Specifications Table 4.11. Absolute Maximum Ratings1 Parameter Symbol Min Max Unit Storage Temperature2 TSTG –65 150 °C Operating Temperature TA –40 125 °C Junction Temperature TJ — 150 °C VDD1, VDD2 –0.5 7.0 V Input Voltage VI –0.5 VDD + 0.5 V Output Voltage VO –0.5 VDD + 0.5 V Output Current Drive Channel IO — 10 mA Lead Solder Temperature (10 s) — 260 °C Maximum Isolation (Input to Output) (1 sec) — 4500 VRMS — 6500 VRMS Supply Voltage NB SOIC-16 Maximum Isolation (Input to Output) (1 sec) WB SOIC-16 Note: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum ratings for exteneded periods may degrade performance. 2. VDE certifies storage temperature from –40 to 150 °C. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 24 Si861x/2x Data Sheet Pin Descriptions (Wide-Body SOIC) 5. Pin Descriptions (Wide-Body SOIC) GND2 GND1 NC VDD1 A1 RF XMITR NC NC I s o l a t i o n RF RCVR GND1 NC Si8610 WB SOIC-16 Name GND2 GND1 NC NC VDD2 VDD1 B1 A1 RF XMITR NC A2 RF XMITR NC NC NC GND1 GND2 NC I s o l a t i o n GND2 GND1 NC NC VDD2 VDD1 RF RCVR B1 A1 RF XMITR RF RCVR B2 A2 RF RCVR NC NC NC GND1 GND2 Si8620 WB SOIC-16 NC I s o l a t i o n GND2 GND1 NC NC VDD2 VDD1 NC RF RCVR B1 A1 RF RCVR RF XMITR B2 A2 RF XMITR NC NC NC GND1 Si8621 WB SOIC-16 GND2 Type NC I s o l a t i o n VDD2 RF XMITR B1 RF RCVR B2 NC NC Si8622 WB SOIC-16 SOIC-16 Pin# SOIC-16 Pin# Si8610 Si862x GND1 1 1 Ground NC1 2, 5, 6, 8,10, 2, 6, 8,10, No Connect 11, 12, 15 11, 15 VDD1 3 3 Supply A1 4 4 Digital I/O Side 1 digital input or output. A2 NC 5 Digital I/O Side 1 digital input or output. GND1 7 7 Ground Side 1 ground. GND2 9 9 Ground Side 2 ground. B2 NC 12 Digital I/O Side 2 digital input or output. B1 13 13 Digital I/O Side 2 digital input or output. VDD2 14 14 Supply Side 2 power supply. GND2 16 16 Ground Side 2 ground. GND2 Description Side 1 ground. NC Side 1 power supply. Note: 1. No Connect. These pins are not internally connected. They can be left floating, tied to VDD, or tied to GND. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 25 Si861x/2x Data Sheet Pin Descriptions (Narrow-Body SOIC) 6. Pin Descriptions (Narrow-Body SOIC) VDD1 A1 RF XMITR VDD1/NC GND1 I s o l a t i o n VDD2 GND2/NC RF RCVR Si8610 NB SOIC-8 Name B1 VDD1 A1 RF XMITR A2 RF XMITR GND2 GND1 I s o l a t i o n VDD2 VDD1 RF RCVR B1 A1 RF XMITR RF RCVR B2 A2 RF RCVR GND2 Si8620 NB SOIC-8 GND1 I s o l a t i o n VDD2 VDD1 RF RCVR B1 A1 RF RCVR RF XMITR B2 A2 RF XMITR Si8621 NB SOIC-8 Type GND2 GND1 I s o l a t i o n VDD2 RF XMITR B1 RF RCVR B2 Si8622 NB SOIC-8 SOIC-8 Pin# SOIC-8 Pin# Si861x Si862x VDD1/NC1 1, 3 1 Supply Side 1 power supply. GND1 4 4 Ground Side 1 ground. A1 2 2 Digital I/O Side 1 digital input or output. A2 NA 3 Digital I/O Side 1 digital input or output. B1 6 7 Digital I/O Side 2 digital input or output. B2 NA 6 Digital I/O Side 2 digital input or output. VDD2 8 8 Supply Side 2 power supply. GND2/NC1 5.7 5 Ground Side 2 ground. GND2 Description Note: 1. No connect. These pins are not internally connected. They can be left floating, tied to VDD, or tied to GND. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 26 Si861x/2x Data Sheet Package Outline: 16-Pin Wide Body SOIC 7. Package Outline: 16-Pin Wide Body SOIC The figure below illustrates the package details for the Triple-Channel Digital Isolator. The table lists the values for the dimensions shown in the illustration. Figure 7.1. 16-Pin Wide Body SOIC silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 27 Si861x/2x Data Sheet Package Outline: 16-Pin Wide Body SOIC Table 7.1. 16-Pin Wide Body SOIC Package Diagram Dimensions1, 2, 3, 4 Dimension Min Max A — 2.65 A1 0.10 0.30 A2 2.05 — b 0.31 0.51 c 0.20 0.33 D 10.30 BSC E 10.30 BSC E1 7.50 BSC e 1.27 BSC L 0.40 1.27 h 0.25 0.75 θ 0° 8° aaa — 0.10 bbb — 0.33 ccc — 0.10 ddd — 0.25 eee — 0.10 fff — 0.20 Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Outline MS-013, Variation AA. 4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 28 Si861x/2x Data Sheet Land Pattern: 16-Pin Wide Body SOIC 8. Land Pattern: 16-Pin Wide Body SOIC The figure below illustrates the recommended land pattern details for the Si861x/2x in a 16-pin wide-body SOIC package. The table lists the values for the dimensions shown in the illustration. Figure 8.1. PCB Land Pattern: 16-Pin Wide Body SOIC Table 8.1. 16-Pin Wide Body SOIC Land Pattern Dimensions1, 2 Dimension Feature (mm) C1 Pad Column Spacing 9.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.90 Note: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 29 Si861x/2x Data Sheet Package Outline: 8-Pin Narrow Body SOIC 9. Package Outline: 8-Pin Narrow Body SOIC The figure below illustrates the package details for the Si86xx. The table lists the values for the dimensions shown in the illustration. Figure 9.1. 8-Pin Small Outline Integrated Circuit (SOIC) Package Table 9.1. 8-Pin Small Outline Integrated Circuit (SOIC) Package Diagram Dimensions Symbol Millimeters Min Max A 1.35 1.75 A1 0.10 0.25 A2 1.40 REF 1.55 REF B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BSC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 m 0° 8° silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 30 Si861x/2x Data Sheet Land Pattern: 8-Pin Narrow Body SOIC 10. Land Pattern: 8-Pin Narrow Body SOIC The figure below illustrates the recommended land pattern details for the Si86xx in an 8-pin narrow-body SOIC. The table lists the values for the dimensions shown in the illustration. Figure 10.1. PCB Land Pattern: 8-Pin Narrow Body SOIC Table 10.1. 8-Pin Narrow Body SOIC Land Pattern Dimensions1, 2 Dimension Feature (mm) C1 Pad Column Spacing 5.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.55 Note: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 31 Si861x/2x Data Sheet Top Marking: 16-Pin Wide Body SOIC 11. Top Marking: 16-Pin Wide Body SOIC Si86XYSV YYWWRTTTTT e4 TW Figure 11.1. 16-Pin Wide Body SOIC Top Marking Table 11.1. 16-Pin Wide Body SOIC Top Marking Explanation Line 1 Marking: Base Part Number Si86 = Isolator product series Ordering Options X = # of data channels (2, 1) (See Ordering Guide for more information.) Y = # of reverse channels (2, 1, 0)1 S = Speed Grade (max data rate) and operating mode: B = 150 Mbps (default output = low) E = 150 Mbps (default output = high) V = Insulation rating B = 2.5 kV; C = 3.75 kV; D = 5.0 kV; T = 5.0 kV with 10 kV surge capability. Line 2 Marking: YY = Year WW = Workweek RTTTTT = Mfg Code Assigned by assembly subcontractor. Corresponds to the year and workweek of the mold date. Manufacturing code from assembly house “R” indicates revision Line 3 Marking: Circle = 1.7 mm Diameter “e4” Pb-Free Symbol (Center-Justified) Country of Origin ISO Code Ab- TW = Taiwan breviation Note: 1. The Si8622 has 1 forward and 1 reverse channel, but directionality is reversed compared to the Si8621, as shown in 5. Pin Descriptions (Wide-Body SOIC) and 6. Pin Descriptions (Narrow-Body SOIC) silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 32 Si861x/2x Data Sheet Top Marking: 8-Pin Narrow Body SOIC 12. Top Marking: 8-Pin Narrow Body SOIC Si86XYSV YYWWRF e3 AIXX Figure 12.1. 8-Pin Narrow Body SOIC Top Marking Table 12.1. 8-Pin Narrow Body SOIC Top Marking Explanation Line 1 Marking: Base Part Number Si86 = Isolator product series Ordering Options X = # of data channels (2, 1) (See Ordering Guide for more information). Y = # of reverse channels (2, 1, 0)1 S = Speed Grade (max data rate) and operating mode: B = 150 Mbps (default output = low) E = 150 Mbps (default output = high) V = Insulation rating B = 2.5 kV; C = 3.75 kV Line 2 Marking: YY = Year WW = Workweek Assigned by assembly subcontractor. Corresponds to the year and workweek of the mold date. R = Product (OPN) Revision F = Wafer Fab Line 3 Marking: Circle = 1.1 mm Diameter “e3” Pb-Free Symbol. Left-Justified First two characters of the manufacturing code. A = Assembly Site Last four characters of the manufacturing code. I = Internal Code XX = Serial Lot Number Note: 1. The Si8622 has 1 forward and 1 reverse channel, but directionality is reversed compared to the Si8621, as shown in 5. Pin Descriptions (Wide-Body SOIC) and 6. Pin Descriptions (Narrow-Body SOIC) silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 33 Si861x/2x Data Sheet Document Change List 13. Document Change List Revision 0.1 to Revision 0.2 • Added chip graphics on page 1. • Moved Tables 1 and 11 to page 21. • Updated Table 6, “Insulation and Safety-Related Specifications,” on page 18. • Updated Table 8, “IEC 60747-5-5 Insulation Characteristics for Si86xxxx*,” on page 19. • Moved Table 1 to page 4. • Moved “Typical Performance Characteristics” to page 7. • Updated "3. Pin Descriptions (Wide-Body SOIC)" on page 9. • Updated "4. Pin Descriptions (Narrow-Body SOIC)" on page 10. • Updated "5. Ordering Guide" on page 11. Revision 0.2 to Revision 0.3 • Added chip graphics on page 1. • Updated Table 6, “Insulation and Safety-Related Specifications,” on page 18. • Updated Table 8, “IEC 60747-5-5 Insulation Characteristics for Si86xxxx*,” on page 19. • Updated "3. Pin Descriptions (Wide-Body SOIC)" on page 9. • Updated "4. Pin Descriptions (Narrow-Body SOIC)" on page 10. • Updated "5. Ordering Guide" on page 11. Revision 0.3 to Revision 1.0 • Updated “Table 3. Electrical Characteristics”. • Reordered spec tables to conform to new convention. • Removed “pending” throughout document. Revision 1.0 to Revision 1.1 • Updated High Level Output Voltage VOH to 3.1 V in Table 3, “Electrical Characteristics,” on page 9. • Updated High Level Output Voltage VOH to 2.3 V in Table 4, “Electrical Characteristics,” on page 13. Revision 1.1 to Revision 1.2 • Updated Table 1 on page 4. • Deleted reference to EN. • Updated "5. Ordering Guide" on page 11 to include MSL2A. Revision 1.2 to Revision 1.3 • Updated Table 11 on page 21. • Added junction temperature spec. • Updated "2.3.1. Supply Bypass" on page 6. • Removed “3.3.2. Pin Connections” on page 22. • Updated "5. Ordering Guide" on page 11. • Removed Rev A devices. • Updated "6. Package Outline: 16-Pin Wide Body SOIC" on page 13. • Updated Top Marks. • Added revision description. Revision 1.3 to Revision 1.4 • Added Figure 2, “Common Mode Transient Immunity Test Circuit,” on page 8. • Added references to CQC throughout. • Added references to 2.5 kVRMS devices throughout. • Updated "5. Ordering Guide" on page 11. • Updated "10.1. 16-Pin Wide Body SOIC Top Marking" on page 18. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 34 Si861x/2x Data Sheet Document Change List Revision 1.4 to Revision 1.5 • Updated Table 5 on page 17. • Added CQC certificate numbers. • Updated "5. Ordering Guide" on page 11. • Removed references to moisture sensitivity levels. • Removed Note 2. Revision 1.5 to Revision 1.6 • Added product options Si862xxT in 1. Ordering Guide. • Added spec line items for Input Leakage Current pertaining to Si862xxT in 4. Electrical Specifications. • Updated IEC 60747-5-2 to IEC 60747-5-5 in all instances in document. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.6 | 35 Table of Contents 1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . . 3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Layout Recommendations. 3.3.1 Supply Bypass . . . . 3.3.2 Output Pin Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 . 5 . 5 3.4 Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.5 Typical Performance Characteristis. . . . . . . . . . . . . . . . . . . . . . . 6 4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5. Pin Descriptions (Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . 25 6. Pin Descriptions (Narrow-Body SOIC) . . . . . . . . . . . . . . . . . . . . . 26 7. Package Outline: 16-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . . 27 8. Land Pattern: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . 29 9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . 30 10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . 31 11. Top Marking: 16-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . . . 32 12. Top Marking: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . 33 13. Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table of Contents 36 Smart. Connected. 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