Si8640/Si8641/Si8642/Si8645 Low-Power Quad-Channel Digital Isolators

Si864x Data Sheet
Low-Power Quad-Channel Digital Isolators
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages over legacy isolation technologies. The operating parameters of these products remain stable across wide temperature ranges and throughout device service life for ease
of design and highly uniform performance. All device versions have Schmitt trigger inputs
for high noise immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve propagation delays of
less than 10 ns. Enable inputs provide a single point control for enabling and disabling
output drive. Ordering options include a choice of isolation ratings (1.0, 2.5, 3.75 and 5
kV) and a selectable fail-safe operating mode to control the default output state during
power loss. All products >1 kV are safety certified by UL, CSA, VDE, and CQC, and
products in wide-body packages support reinforced insulation withstanding up to 5
kVRMS.
Applications
• Industrial automation systems
• Medical electronics
• Hybrid electric vehicles
• Isolated switch mode supplies
• Isolated ADC, DAC
• Motor control
• Power inverters
• Communications systems
Safety Regulatory Approvals
• UL 1577 recognized
• Up to 5000 VRMS for 1 minute
• CSA component notice 5A approval
• IEC 60950-1, 61010-1, 60601-1 (reinforced insulation)
• VDE certification conformity
• Si864xxT options certified to reinforced VDE 0884-10
• All other options certified to IEC 60747-5-5 and reinforced 60950-1
• CQC certification approval
• GB4943.1
KEY FEATURES
• High-speed operation
• DC to 150 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage
• 2.5–5.5 V
• Up to 5000 VRMS isolation
• Reinforced VDE 0884-10, 10 kV surgecapable (Si864xxT)
• 60-year life at rated working voltage
• High electromagnetic immunity
• Ultra low power (typical)
5 V Operation
• 1.6 mA per channel at 1 Mbps
• 5.5 mA per channel at 100 Mbps
2.5 V Operation
• 1.5 mA per channel at 1 Mbps
• 3.5 mA per channel at 100 Mbps
• Tri-state outputs with ENABLE
• Schmitt trigger inputs
• Selectable fail-safe mode
• Default high or low output (ordering
option)
• Precise timing (typical)
• 10 ns propagation delay
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient Immunity 50 kV/µs
• AEC-Q100 qualification
• Wide temperature range
• –40 to 125 °C
• RoHS-compliant packages
• SOIC-16 wide body
• SOIC-16 narrow body
• QSOP-16
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Rev. 1.9
Si864x Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Ordering Guide for Valid OPNs1, 2
Max Data
Rate (Mbps)
Default
Output
State
Isolation
Rating
(kV)
Temp (°C)
Package
0
150
Low
1.0
–40 to 125 °C
QSOP-16
4
0
150
Low
2.5
–40 to 125 °C NB SOIC-16
Si8640BB-B-IS
4
0
150
Low
2.5
–40 to 125 °C WB SOIC-16
Si8640BC-B-IS1
4
0
150
Low
3.75
–40 to 125 °C NB SOIC-16
Si8640EC-B-IS1
4
0
150
High
3.75
–40 to 125 °C NB SOIC-16
Si8640BD-B-IS
4
0
150
Low
5.0
–40 to 125 °C WB SOIC-16
Si8640ED-B-IS
4
0
150
High
5.0
–40 to 125 °C WB SOIC-16
Si8641BA-B-IU
3
1
150
Low
1.0
–40 to 125 °C
QSOP-16
Si8641BA-C-IU
3
1
150
Low
1.0
–40 to 125 °C
QSOP-16
Si8641BB-B-IU
3
1
150
Low
2.5
–40 to 125 °C
QSOP-16
Si8641BB-B-IS1
3
1
150
Low
2.5
–40 to 125 °C NB SOIC-16
Si8641BB-B-IS
3
1
150
Low
2.5
–40 to 125 °C WB SOIC-16
Si8641BC-B-IS1
3
1
150
Low
3.75
–40 to 125 °C NB SOIC-16
Si8641EC-B-IS1
3
1
150
High
3.75
–40 to 125 °C NB SOIC-16
Si8641BD-B-IS
3
1
150
Low
5.0
–40 to 125 °C WB SOIC-16
Si8641ED-B-IS
3
1
150
High
5.0
–40 to 125 °C WB SOIC-16
Si8642BA-B-IU
2
2
150
Low
1.0
–40 to 125 °C
QSOP-16
Si8642BA-C-IU
2
2
150
Low
1.0
–40 to 125 °C
QSOP-16
Si8642EA-B-IU
2
2
150
High
1.0
–40 to 125 °C
QSOP-16
Si8642BB-B-IS1
2
2
150
Low
2.5
–40 to 125 °C NB SOIC-16
Si8642BB-B-IS
2
2
150
Low
2.5
–40 to 125 °C WB SOIC-16
Si8642BC-B-IS1
2
2
150
Low
3.75
–40 to 125 °C NB SOIC-16
Si8642EC-B-IS1
2
2
150
High
3.75
–40 to 125 °C NB SOIC-16
Si8642BD-B-IS
2
2
150
Low
5.0
–40 to 125 °C WB SOIC-16
Si8642ED-B-IS
2
2
150
High
5.0
–40 to 125 °C WB SOIC-16
Si8645BA-B-IU
4
0
150
Low
1.0
–40 to 125 °C
QSOP-16
Si8645BA-C-IU
4
0
150
Low
1.0
–40 to 125 °C
QSOP-16
Si8645BB-B-IU
4
0
150
Low
2.5
–40 to 125 °C
QSOP-16
Si8645BB-B-IS1
4
0
150
Low
2.5
–40 to 125 °C NB SOIC-16
Si8645BB-B-IS
4
0
150
Low
2.5
–40 to 125 °C WB SOIC-16
Si8645BC-B-IS1
4
0
150
Low
3.75
–40 to 125 °C NB SOIC-16
Si8645BD-B-IS
4
0
150
Low
5.0
–40 to 125 °C WB SOIC-16
Number of
Inputs
Number of
Inputs
VDD1 Side
VDD2 Side
Si8640BA-B-IU
4
Si8640BB-B-IS1
Ordering Part Number (OPN)
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Rev. 1.9 | 1
Si864x Data Sheet
Ordering Guide
Ordering Part Number (OPN)
Number of
Inputs
Number of
Inputs
VDD1 Side
VDD2 Side
Max Data
Rate (Mbps)
Default
Output
State
Isolation
Rating
(kV)
Temp (°C)
Package
Product Options with Reinforced VDE 0884-10 Rating with 10 kV Surge Capability
Si8640BT-IS
4
0
150
Low
5.0
–40 to 125 °C WB SOIC-16
Si8640ET-IS
4
0
150
High
5.0
–40 to 125 °C WB SOIC-16
Si8641BT-IS
3
1
150
Low
5.0
–40 to 125 °C WB SOIC-16
Si8641ET-IS
3
1
150
High
5.0
–40 to 125 °C WB SOIC-16
Si8642BT-IS
2
2
150
Low
5.0
–40 to 125 °C WB SOIC-16
Si8642ET-IS
2
2
150
High
5.0
–40 to 125 °C WB SOIC-16
Si8645BT-IS
4
0
150
Low
5.0
–40 to 125 °C WB SOIC-16
Si8645ET-IS
4
0
150
Low
5.0
–40 to 125 °C WB SOIC-16
Note:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
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Rev. 1.9 | 2
Si864x Data Sheet
System Overview
2. System Overview
2.1 Theory of Operation
The operation of an Si864x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si864x channel is shown in the figure below.
Figure 2.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and improved immunity
to magnetic fields. See the following figure for more details.
Figure 2.2. Modulation Scheme
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Si864x Data Sheet
System Overview
2.2 Eye Diagram
The figure below illustrates an eye diagram taken on an Si8640. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern
Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8640 were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width
distortion and 350 ps peak jitter were exhibited.
Figure 2.3. Eye Diagram
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Si864x Data Sheet
Device Operation
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 3.1 Device Behavior during Normal Operation on
page 7, where UVLO+ and UVLO– are the respective positive-going and negative-going thresholds. Refer to the following tables to
determine outputs when power supply (VDD) is not present and for logic conditions when enable pins are used.
Table 3.1. Si86xx Logic Operation
VI Input1, 2 EN Input1, 2, 3, 4
VDDI State1, 5, 6
VDDO State1, 5, 6
VO Output1, 2
H
H or NC
P
P
H
L
H or NC
P
P
L
X7
L
P
P
Hi-Z8
X7
H or NC
UP
P
L9
H9
X7
L
UP
P
X7
X7
P
UP
Hi-Z8
Comments
Enabled, normal operation.
Disabled.
Upon transition of VDDI from unpowered to
powered, VO returns to the same state as VI
in less than 1 µs.
Disabled.
Undetermined Upon transition of VDDO from unpowered to
powered, VO returns to the same state as VI
within 1 µs, if EN is in either the H or NC
state. Upon transition of VDDO from unpowered to powered, VO returns to Hi-Z within 1
µs if EN is L.
Note:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the
enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si86xx is operating in noisy
environments.
4. No Connect (NC) replaces EN1 on Si8640/45. No Connect replaces EN2 on the Si8645. No Connects are not internally connected and can be left floating, tied to VDD, or tied to GND.
5. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled
(EN = 0).
9. See 1. Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). Some devices have default
output state = H, and some have default output state = L, depending on the ordering part number (OPN). For default high devices, the data channels have pull-ups on inputs/outputs. For default low devices, the data channels have pull-downs on inputs/
outputs.
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Si864x Data Sheet
Device Operation
Table 3.2. Enable Input Truth
Part Number
EN11, 2
EN21, 2
Si8640
—
H
Outputs B1, B2, B3, B4 are enabled and follow the input state.
—
L
Outputs B1, B2, B3, B4 are disabled and in high impedance state.3
H
X
Output A4 enabled and follows the input state.
L
X
Output A4 disabled and in high impedance state.3
X
H
Outputs B1, B2, B3 are enabled and follow the input state.
X
L
Outputs B1, B2, B3 are disabled and in high impedance state.3
H
X
Outputs A3 and A4 are enabled and follow the input state.
L
X
Outputs A3 and A4 are disabled and in high impedance state.3
X
H
Outputs B1 and B2 are enabled and follow the input state.
X
L
Outputs B1 and B2 are disabled and in high impedance state.3
—
—
Outputs B1, B2, B3, B4 are enabled and follow the input state.
Si8641
Si8642
Si8645
Operation
Note:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. EN1, EN2 logic operation is
summarized for each isolator product in Table 2. These inputs are internally pulled-up to local VDD allowing them to be connected to an external logic level (high or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2
if they are left floating. If EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the
Si86xx is operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled
(EN = 0).
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Si864x Data Sheet
Device Operation
3.1 Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow
the states of inputs.
3.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or
exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when
VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.
Figure 3.1. Device Behavior during Normal Operation
3.3 Layout Recommendations
To ensure safety in the end-user application, high-voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the
safety extra-low-voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a
digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large
high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 4.6 Insulation and Safety-Related
Specifications on page 21 and Table 4.8 IEC 60747-5-5 Insulation Characteristics for Si86xxxx 1 on page 22 detail the working voltage and creepage/clearance capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA
5A), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the endsystem specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator.
3.3.1 Supply Bypass
The Si864x family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed
as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 Ω ) in series
with the inputs and outputs if the system is excessively noisy.
3.3.2 Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the onchip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will
be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
3.4 Fail-Safe Operating Mode
Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered)
can either be a logic high or logic low when the output supply is powered. See Table 3.1 Si86xx Logic Operation on page 5 and
1. Ordering Guide for more information.
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Si864x Data Sheet
Device Operation
3.5 Typical Performance Characteristics
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to 4. Electrical
Specifications for actual specification limits.
Figure 3.2. Si8640/45 Typical VDD1 Supply Current vs. Data
Rate 5, 3.3, and 2.5 V Operation
Figure 3.3. Si8640/45 Typical VDD2 Supply Current vs. Data
Rate 5, 3.3, and 2.5 V
Figure 3.4. Si8641 Typical VDD1 Supply Current vs. Data
Rate 5, 3.3, and 2.5 V Operation
Figure 3.5. Si8641 Typical VDD2 Supply Current vs. Data Rate
5, 3.3, and 2.5 V Operation (15 pF Load)
Figure 3.7. Propagation Delay vs. Temperature (5.0 V Data)
Figure 3.6. Si8642 Typical VDD1 or VDD2 Supply Current vs.
Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load)
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Si864x Data Sheet
Electrical Specifications
4. Electrical Specifications
Table 4.1. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Ambient Operating Temperature 1
TA
–40
25
125 1
°C
Supply Voltage
VDD1
2.5
—
5.5
V
VDD2
2.5
—
5.5
V
Note:
1. The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply
voltage.
Table 4.2. Electrical Characteristics 1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD Undervoltage Threshold
VDDUV+
VDD1, VDD2 rising
1.95
2.24
2.375
V
VDD Undervoltage Threshold
VDDUV–
VDD1, VDD2 falling
1.88
2.16
2.325
V
VDD Undervoltage Hysteresis
VDDHYS
50
70
95
mV
Positive-Going Input Threshold
VT+
All inputs rising
1.4
1.67
1.9
V
Negative-Going Input Threshold
VT–
All inputs falling
1.0
1.23
1.4
V
Input Hysteresis
VHYS
0.38
0.44
0.50
V
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1, VDD2 – 0.4
4.8
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
—
—
±10
µA
—
—
±15
—
50
—
Ω
—
2.0
—
µA
—
10.0
—
Input Leakage Current
Si864xxA/B/C/D
IL
Si864xxT
Output Impedance 2
ZO
Enable Input Current
Si864xxA/B/C/D
IENH, IENL
VENx = VIH or VIL
Si864xxT
DC Supply Current (All Inputs 0 V or at Supply)
Si8640Bx, Ex, Si8645Bx
VDD1
VI = 0(Bx), 1(Ex)
—
1.0
1.6
VDD2
VI = 0(Bx), 1(Ex)
—
2.4
3.8
VDD1
VI = 1(Bx), 0(Ex)
—
6.1
9.2
VDD2
VI = 1(Bx), 0(Ex)
—
2.5
4.0
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mA
Rev. 1.9 | 9
Si864x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
VDD1
VI = 0(Bx), 1(Ex)
—
1.4
2.2
VDD2
VI = 0(Bx), 1(Ex)
—
2.3
3.7
VDD1
VI = 1(Bx), 0(Ex)
—
5.2
7.8
VDD2
VI = 1(Bx), 0(Ex)
—
3.6
5.4
VDD1
VI = 0(Bx), 1(Ex)
—
1.8
2.9
VDD2
VI = 0(Bx), 1(Ex)
—
1.8
2.9
VDD1
VI = 1(Bx), 0(Ex)
—
4.4
6.6
VDD2
VI = 1(Bx), 0(Ex)
—
4.4
6.6
VDD1
—
3.6
5.0
VDD2
—
2.9
4.0
VDD1
—
3.4
4.8
VDD2
—
3.3
4.6
VDD1
—
3.3
4.6
VDD2
—
3.3
4.6
VDD1
—
3.6
5.0
VDD2
—
4.0
5.6
VDD1
—
3.7
5.2
VDD2
—
4.1
5.8
VDD1
—
3.9
5.4
VDD2
—
3.9
5.4
VDD1
—
3.6
5.0
VDD2
—
17.5
22.8
Unit
Si8641Bx, Ex
mA
Si8642Bx, Ex
mA
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
mA
Si8641Bx, Ex
mA
Si8642Bx, Ex
mA
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
mA
Si8641Bx, Ex
mA
Si8642Bx, Ex
mA
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
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mA
Rev. 1.9 | 10
Si864x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD1
—
7.3
9.8
mA
VDD2
—
14.3
18.5
VDD1
—
11
14.3
VDD2
—
11
14.3
Maximum Data Rate
0
—
150
Mbps
Minimum Pulse Width
—
—
5.0
ns
5.0
8.0
13
ns
—
0.2
4.5
ns
tPSK(P-P)
—
2.0
4.5
ns
tPSK
—
0.4
2.5
ns
—
2.5
4.0
ns
—
2.5
4.0
ns
—
350
—
ps
See Figure 4.3 CommonMode Transient Immunity Test
Circuit on page 13
35
50
—
60
100
—
Si8641Bx, Ex
Si8642Bx, Ex
mA
Timing Characteristics
Si864xBx, Ex
Propagation Delay
Pulse Width Distortion
|tPLH – tPHL|
Propagation Delay Skew 3
Channel-Channel Skew
tPHL, tPLH
PWD
See Figure 4.2 Propagation
Delay Timing on page 13
See Figure 4.2 Propagation
Delay Timing on page 13
All Models
CL = 15 pF
Output Rise Time
tr
See Figure 4.2 Propagation
Delay Timing on page 13
CL = 15 pF
Output Fall Time
Peak Eye Diagram Jitter
tf
tJIT(PK)
See Figure 4.2 Propagation
Delay Timing on page 13
See Figure 2.3 Eye Diagram
on page 4
VI = VDD or 0 V
Common Mode Transient Immunity
CMTI
Si86xxxA/B/C/D
Si86xxxT
VCM = 1500 V
kV/µs
Enable to Data Valid
ten1
See Figure 4.1 ENABLE Timing Diagram on page 13
—
6.0
11
ns
Enable to Data Tri-State
ten2
See Figure 4.1 ENABLE Timing Diagram on page 13
—
8.0
12
ns
Input power loss to valid default output
tSD
See Figure 3.1 Device Behavior during Normal Operation
on page 7
—
8.0
12
ns
Start-up Time 4
tSU
—
15
40
µs
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Si864x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. VDD1 = 5 V ±10%; VDD2 = 5 V ±10%, TA = –40 to 125 °C
2. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to the appearance of valid data at the output.
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Si864x Data Sheet
Electrical Specifications
Figure 4.1. ENABLE Timing Diagram
Figure 4.2. Propagation Delay Timing
Figure 4.3. Common-Mode Transient Immunity Test Circuit
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Si864x Data Sheet
Electrical Specifications
Table 4.3. Electrical Characteristics 1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD Undervoltage Threshold
VDDUV+
VDD1, VDD2 rising
1.95
2.24
2.375
V
VDD Undervoltage Threshold
VDDUV–
VDD1, VDD2 falling
1.88
2.16
2.325
V
VDD Undervoltage Hysteresis
VDDHYS
50
70
95
mV
Positive-Going Input Threshold
VT+
All inputs rising
1.4
1.67
1.9
V
Negative-Going Input Threshold
VT–
All inputs falling
1.0
1.23
1.4
V
Input Hysteresis
VHYS
0.38
0.44
0.50
V
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1, VDD2 – 0.4
3.1
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
—
—
±10
µA
—
—
±15
—
50
—
Ω
—
2.0
—
µA
—
10.0
—
Input Leakage Current
Si864xxA/B/C/D
IL
Si864xxT
Output Impedance 2
ZO
Enable Input Current
Si864xxA/B/C/D
IENH, IENL
VENx = VIH or VIL
Si864xxT
DC Supply Current (All Inputs 0 V or at Supply)
Si8640Bx, Ex, Si8645Bx
VDD1
VI = 0(Bx), 1(Ex)
—
1.0
1.6
VDD2
VI = 0(Bx), 1(Ex)
—
2.4
3.8
VDD1
VI = 1(Bx), 0(Ex)
—
6.1
9.2
VDD2
VI = 1(Bx), 0(Ex)
—
2.5
4.0
VDD1
VI = 0(Bx), 1(Ex)
—
1.4
2.2
VDD2
VI = 0(Bx), 1(Ex)
—
2.3
3.7
VDD1
VI = 1(Bx), 0(Ex)
—
5.2
7.8
VDD2
VI = 1(Bx), 0(Ex)
—
3.6
5.4
VDD1
VI = 0(Bx), 1(Ex)
—
1.8
2.9
VDD2
VI = 0(Bx), 1(Ex)
—
1.8
2.9
VDD1
VI = 1(Bx), 0(Ex)
—
4.4
6.6
VDD2
VI = 1(Bx), 0(Ex)
—
4.4
6.6
mA
Si8641Bx, Ex
mA
Si8642Bx, Ex
mA
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
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Si864x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD1
—
3.6
5.0
mA
VDD2
—
2.9
4.0
VDD1
—
3.4
4.8
VDD2
—
3.3
4.6
VDD1
—
3.3
4.6
VDD2
—
3.3
4.6
VDD1
—
3.6
5.0
VDD2
—
3.4
4.7
VDD1
—
3.5
4.9
VDD2
—
3.6
5.1
VDD1
—
3.6
5.0
VDD2
—
3.6
5.0
VDD1
—
3.6
5.0
VDD2
—
12.3
15.9
VDD1
—
5.9
7.9
VDD2
—
10.3
13.4
VDD1
—
8.2
10.7
VDD2
—
8.2
10.7
Maximum Data Rate
0
—
150
Mbps
Minimum Pulse Width
—
—
5.0
ns
5.0
8.0
13
ns
Si8640Bx, Ex, Si8645Bx
Si8641Bx, Ex
mA
Si8642Bx, Ex
mA
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
mA
Si8641Bx, Ex
mA
Si8642Bx, Ex
mA
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
mA
Si8641Bx, Ex
mA
Si8642Bx, Ex
mA
Timing Characteristics
Si864xBx, Ex
Propagation Delay
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tPHL, tPLH
See Figure 4.2 Propagation
Delay Timing on page 13
Rev. 1.9 | 15
Si864x Data Sheet
Electrical Specifications
Parameter
Pulse Width Distortion
|tPLH – tPHL|
Propagation Delay Skew 3
Channel-Channel Skew
Symbol
Test Condition
Min
Typ
Max
Unit
PWD
See Figure 4.2 Propagation
Delay Timing on page 13
—
0.2
4.5
ns
tPSK(P-P)
—
2.0
4.5
ns
tPSK
—
0.4
2.5
ns
—
2.5
4.0
ns
—
2.5
4.0
ns
—
350
—
ps
See Figure 4.3 CommonMode Transient Immunity
Test Circuit on page 13
35
50
—
60
100
—
All Models
CL = 15 pF
Output Rise Time
tr
See Figure 4.2 Propagation
Delay Timing on page 13
CL = 15 pF
Output Fall Time
Peak Eye Diagram Jitter
tf
tJIT(PK)
See Figure 4.2 Propagation
Delay Timing on page 13
See Figure 2.3 Eye Diagram
on page 4
VI = VDD or 0 V
Common Mode Transient Immunity
CMTI
Si86xxxA/B/C/D
Si86xxxT
VCM = 1500 V
kV/µs
Enable to Data Valid
ten1
See Figure 4.1 ENABLE
Timing Diagram on page 13
—
6.0
11
ns
Enable to Data Tri-State
ten2
See Figure 4.1 ENABLE
Timing Diagram on page 13
—
8.0
12
ns
Input power loss to valid default output
tSD
See Figure 3.1 Device Behavior during Normal Operation on page 7
—
8.0
12
ns
Start-up Time 4
tSU
—
15
40
µs
Note:
1. VDD1 = 3.3 V ±10%; VDD2 = 3.3 V ±10%, TA = –40 to 125 °C
2. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to the appearance of valid data at the output.
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Si864x Data Sheet
Electrical Specifications
Table 4.4. Electrical Characteristics 1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD Undervoltage Threshold
VDDUV+
VDD1, VDD2 rising
1.95
2.24
2.375
V
VDD Undervoltage Threshold
VDDUV–
VDD1, VDD2 falling
1.88
2.16
2.325
V
VDD Undervoltage Hysteresis
VDDHYS
50
70
95
mV
Positive-Going Input Threshold
VT+
All inputs rising
1.4
1.67
1.9
V
Negative-Going Input Threshold
VT–
All inputs falling
1.0
1.23
1.4
V
Input Hysteresis
VHYS
0.38
0.44
0.50
V
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1, VDD2 – 0.4
2.3
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
—
—
±10
µA
—
—
±15
—
50
—
Ω
—
2.0
—
µA
—
10.0
—
Input Leakage Current
Si864xxA/B/C/D
IL
Si864xxT
Output Impedance2
ZO
Enable Input Current
Si864xxA/B/C/D
IENH, IENL
VENx = VIH or VIL
Si864xxT
DC Supply Current (All Inputs 0 V or at Supply)
Si8640Bx, Ex, Si8645Bx
VDD1
VI = 0(Bx), 1(Ex)
—
1.0
1.6
VDD2
VI = 0(Bx), 1(Ex)
—
2.4
3.8
VDD1
VI = 1(Bx), 0(Ex)
—
6.1
9.2
VDD2
VI = 1(Bx), 0(Ex)
—
2.5
4.0
VDD1
VI = 0(Bx), 1(Ex)
—
1.4
2.2
VDD2
VI = 0(Bx), 1(Ex)
—
2.3
3.7
VDD1
VI = 1(Bx), 0(Ex)
—
5.2
7.8
VDD2
VI = 1(Bx), 0(Ex)
—
3.6
5.4
VDD1
VI = 0(Bx), 1(Ex)
—
1.8
2.9
VDD2
VI = 0(Bx), 1(Ex)
—
1.8
2.9
VDD1
VI = 1(Bx), 0(Ex)
—
4.4
6.6
VDD2
VI = 1(Bx), 0(Ex)
—
4.4
6.6
mA
Si8641Bx, Ex
mA
Si8642Bx, Ex
mA
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
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Si864x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD1
—
3.6
5.0
mA
VDD2
—
2.9
4.0
VDD1
—
3.4
4.8
VDD2
—
3.3
4.6
VDD1
—
3.3
4.6
VDD2
—
3.3
4.6
VDD1
—
3.6
5.0
VDD2
—
3.1
4.3
VDD1
—
3.5
4.8
VDD2
—
3.4
4.8
VDD1
—
3.4
4.8
VDD2
—
3.4
4.8
VDD1
—
3.6
5.0
VDD2
—
9.9
12.8
VDD1
—
5.2
7.0
VDD2
—
8.5
11.1
VDD1
—
6.9
9.0
VDD2
—
6.9
9.0
Maximum Data Rate
0
—
150
Mbps
Minimum Pulse Width
—
—
5.0
ns
5.0
8.0
14
ns
Si8640Bx, Ex, Si8645Bx
Si8641Bx, Ex
mA
Si8642Bx, Ex
mA
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
mA
Si8641Bx, Ex
mA
Si8642Bx, Ex
mA
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8640Bx, Ex, Si8645Bx
mA
Si8641Bx, Ex
mA
Si8642Bx, Ex
mA
Timing Characteristics
Si864xBx, Ex
Propagation Delay
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tPHL, tPLH
See Figure 4.2 Propagation
Delay Timing on page 13
Rev. 1.9 | 18
Si864x Data Sheet
Electrical Specifications
Parameter
Pulse Width Distortion
|tPLH -tPHL|
Propagation Delay Skew 3
Channel-Channel Skew
Symbol
Test Condition
Min
Typ
Max
Unit
PWD
See Figure 4.2 Propagation
Delay Timing on page 13
—
0.2
5.0
ns
tPSK(P-P)
—
2.0
5.0
ns
tPSK
—
0.4
2.5
ns
—
2.5
4.0
ns
—
2.5
4.0
ns
—
350
—
ps
See Figure 4.3 CommonMode Transient Immunity
Test Circuit on page 13
35
50
—
60
100
—
All Models
CL = 15 pF
Output Rise Time
tr
See Figure 4.2 Propagation
Delay Timing on page 13
CL = 15 pF
Output Fall Time
Peak Eye Diagram Jitter
tf
tJIT(PK)
See Figure 4.2 Propagation
Delay Timing on page 13
See Figure 2.3 Eye Diagram
on page 4
VI = VDD or 0 V
Common Mode Transient Immunity
CMTI
Si86xxxA/B/C/D
Si86xxxT
VCM = 1500 V
kV/µs
Enable to Data Valid
ten1
See Figure 4.1 ENABLE
Timing Diagram on page 13
—
6.0
11
ns
Enable to Data Tri-State
ten2
See Figure 4.1 ENABLE
Timing Diagram on page 13
—
8.0
12
ns
Input power loss to valid default output
tSD
See Figure 3.1 Device Behavior during Normal Operation on page 7
—
8.0
12
ns
Start-up Time 4
tSU
—
15
40
µs
Note:
1. VDD1 = 2.5 V ±5%; VDD2 = 2.5 V ±5%, TA = –40 to 125 °C
2. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to the appearance of valid data at the output.
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Si864x Data Sheet
Electrical Specifications
Table 4.5. Regulatory Information 1, 2, 3, 4
For all Product Options Except Si864xxT
CSA
The Si864x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
VDE
The Si864x is certified according to IEC 60747-5-5. For more details, see File 5006301-4880-0001.
60747-5-5: Up to 1200 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si864x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si864x is certified under GB4943.1-2011. For more details, see certificates CQC13001096110 and CQC13001096239.
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
For All Si864xxT Product Options
CSA
Certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
VDE
Certified according to VDE 0884-10.
UL
Certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
Certified under GB4943.1-2011
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
Note:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices, which are production tested to 3.0 kVRMS for 1 s.
2. Regulatory Certifications apply to 3.75 kVRMS rated devices, which are production tested to 4.5 kVRMS for 1 s.
3. Regulatory Certifications apply to 5.0 kVRMS rated devices, which are production tested to 6.0 kVRMS for 1 s.
4. For more information, see the Ordering Guide.
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Si864x Data Sheet
Electrical Specifications
Table 4.6. Insulation and Safety-Related Specifications
Parameter
Symbol
Test
Condition
Value
Unit
WB SOIC-16
NB SOIC-16
QSOP-16
Nominal Air Gap (Clearance) 1
L(IO1)
8.0
4.9
3.6
mm
Nominal External Tracking (Creepage) 1
L(IO2)
8.0
4.01
3.6
mm
0.014
0.014
0.014
mm
600
600
600
VRMS
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
PTI
IEC60112
(Proof Tracking Index)
Erosion Depth
ED
0.019
0.019
0.031
mm
Resistance (Input-Output) 2
RIO
1012
1012
1012
Ω
Capacitance (Input-Output) 2
CIO
2.0
2.0
2.0
pF
4.0
4.0
4.0
pF
f = 1 MHz
CI
Input Capacitance 3
Note:
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and creepage
limits as 4.7 mm minimum for the NB SOIC-16 package and QSOP-16 packages and 8.5 mm minimum for the WB SOIC-16
package. UL does not impose a clearance and creepage minimum for component-level certifications. CSA certifies the clearance
and creepage limits as 3.9 mm minimum for the NB SOIC-16, 3.6 mm for QSOP-16 packages, and 7.6 mm minimum for the WB
SOIC-16 package.
2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 are shorted together to form
the first termina and pins 9–16 are shorted together to form the second terminal. The parameters are then measured between
these two terminals.
3. Measured from input pin to ground.
Table 4.7. IEC 60664-1 Ratings
Parameter
Test Conditions
Specification
WB SOIC-16
NB SOIC-16
QSOP-16
I
I
I
Basic Isolation Group
Material Group
Installation Classification
Rated Mains Voltages < 150
VRMS
I-IV
I-IV
I-IV
Rated Mains Voltages < 300
VRMS
I-IV
I-III
I-III
Rated Mains Voltages < 400
VRMS
I-III
I-II
I-II
Rated Mains Voltages < 600
VRMS
I-III
I-II
I-II
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Si864x Data Sheet
Electrical Specifications
Table 4.8. IEC 60747-5-5 Insulation Characteristics for Si86xxxx 1
Parameter
Maximum Working Insulation
Voltage
Symbol
Test Condition
Characteristic
Unit
WB SOIC-16
NB SOIC-16
QSOP-16
1200
630
630
Vpeak
2250
1182
1182
Vpeak
6000
6000
6000
Vpeak
Si864xxT tested with magnitude
6250 V x 1.6 = 10 kV
6250
—
—
Si864xxB/C/D tested with 4000 V
4000
4000
4000
2
2
2
>109
>109
>109
VIORM
Method b1
Input to Output Test Voltage
VPR
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
Transient Overvoltage
VIOTM
t = 60 sec
Tested per IEC 60065 with surge
voltage of 1.2 µs/50 µs
Surge Voltage
VIOSM
Vpeak
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at TS, VIO
= 500 V
RS
Ω
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21.
Table 4.9. IEC Safety Limiting Values 1
Parameter
Case Temperature
Symbol
Test Condition
TS
Max
WB SOIC-16 NB SOIC-16
QSOP-16
Unit
150
150
150
°C
220
210
210
mA
275
275
275
mW
θJA = 100 °C/W (WB SOIC-16)
Safety Input, Output, or Supply
Current
IS
105 °C/W (NB SOIC-16, QSOP-16)
VI = 5.5 V, TJ = 150 °C, TA = 25 °C
Device Power Dissipation 2
PD
Note:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 4.4 (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-5/VDE 0884-10, as Applies on
page 23 and Figure 4.5 (NB SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case
Temperature per DIN EN 60747-5-5/VDE 0884-10, as Applies on page 23.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V; TJ = 150 ºC; CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.
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Si864x Data Sheet
Electrical Specifications
Table 4.10. Thermal Characteristics
Parameter
IC Junction-to-Air Thermal Resistance
Symbol
WB SOIC-16
NB SOIC-16/QSOP-16
Unit
θJA
100
105
°C/W
Figure 4.4. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN
60747-5-5/VDE 0884-10, as Applies
Figure 4.5. (NB SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature
per DIN EN 60747-5-5/VDE 0884-10, as Applies
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Si864x Data Sheet
Electrical Specifications
Table 4.11. Absolute Maximum Ratings 1
Parameter
Symbol
Min
Max
Unit
Storage Temperature 2
TSTG
–65
150
°C
Operating Temperature
TA
–40
125
°C
Junction Temperature
TJ
—
150
°C
VDD1, VDD2
–0.5
7.0
V
Input Voltage
VI
–0.5
VDD + 0.5
V
Output Voltage
VO
–0.5
VDD + 0.5
V
Output Current Drive Channel
IO
—
10
mA
Lead Solder Temperature (10 s)
—
260
°C
Maximum Isolation (Input to Output) (1 sec)
—
4500
VRMS
—
6500
VRMS
Supply Voltage
NB SOIC-16
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum ratings for exteneded periods may degrade performance.
2. VDE certifies storage temperature from –40 to 150 °C.
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Si864x Data Sheet
Pin Descriptions
5. Pin Descriptions
VDD1
VDD2
GND2
GND1
A1
RF
XMITR
A2
RF
XMITR
A3
RF
XMITR
A4
RF
XMITR
I
s
o
l
a
t
i
o
n
RF
RCVR
B1
RF
RCVR
B2
RF
RCVR
B3
RF
RCVR
B4
VDD1
GND2
GND1
A1
RF
XMITR
A2
RF
XMITR
A3
RF
XMITR
A4
RF
RCVR
I
s
o
l
a
t
i
o
n
EN2/NC
NC
RF
RCVR
B1
RF
RCVR
B2
RF
RCVR
B3
RF
XMITR
B4
GND2
Si8640/45
VDD2
GND2
GND1
A1
RF
XMITR
A2
RF
XMITR
A3
RF
RCVR
A4
RF
RCVR
Si8641
RF
RCVR
B1
RF
RCVR
B2
RF
RF
XMITR
RCVR
B3
RF
XMITR
B4
EN2
GND1
GND1
I
s
o
l
a
t
i
o
n
EN1
EN2
EN1
GND1
VDD1
VDD2
Si8642
GND2
Name
SOIC-16 Pin#
Type
VDD1
1
Supply
Side 1 power supply.
GND1
21
Ground
Side 1 ground.
A1
3
Digital Input
Side 1 digital input.
A2
4
Digital Input
Side 1 digital input.
A3
5
Digital I/O
Side 1 digital input or output.
A4
6
Digital I/O
Side 1 digital input or output.
EN1/NC2
7
Digital Input
GND1
81
Ground
Side 1 ground.
GND2
91
Ground
Side 2 ground.
EN2/NC2
10
Digital Input
B4
11
Digital I/O
Side 2 digital input or output.
B3
12
Digital I/O
Side 2 digital input or output.
B2
13
Digital Output
Side 2 digital output.
B1
14
Digital Output
Side 2 digital output.
GND2
151
Ground
Side 2 ground.
VDD2
16
Supply
Side 2 power supply.
GND2
Description
Side 1 active high enable. NC on Si8640/45.
Side 2 active high enable. NC on Si8645.
Note:
1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15 must also be
connected to external ground.
2. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
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Rev. 1.9 | 25
Si864x Data Sheet
Package Outline: 16-Pin Wide Body SOIC
6. Package Outline: 16-Pin Wide Body SOIC
The figure below illustrates the package details for the the Si864x Digital Isolator. The table lists the values for the dimensions shown in
the illustration.
Figure 6.1. 16-Pin Wide Body SOIC
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Rev. 1.9 | 26
Si864x Data Sheet
Package Outline: 16-Pin Wide Body SOIC
Table 6.1. 16-Pin Wide Body SOIC Package Diagram Dimensions1, 2, 3, 4
Dimension
Min
Max
A
—
2.65
A1
0.10
0.30
A2
2.05
—
b
0.31
0.51
c
0.20
0.33
D
10.30 BSC
E
10.30 BSC
E1
7.50 BSC
e
1.27 BSC
L
0.40
1.27
h
0.25
0.75
θ
0°
8°
aaa
—
0.10
bbb
—
0.33
ccc
—
0.10
ddd
—
0.25
eee
—
0.10
fff
—
0.20
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components.
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Rev. 1.9 | 27
Si864x Data Sheet
Land Pattern: 16-Pin Wide Body SOIC
7. Land Pattern: 16-Pin Wide Body SOIC
The figure below illustrates the recommended land pattern details for the Si864x in a 16-pin wide-body SOIC package. The table lists
the values for the dimensions shown in the illustration.
Figure 7.1. PCB Land Pattern: 16-Pin Wide Body SOIC
Table 7.1. 16-Pin Wide Body SOIC Land Pattern Dimensions1, 2
Dimension
Feature
(mm)
C1
Pad Column Spacing
9.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.90
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 1.9 | 28
Si864x Data Sheet
Package Outline: 16-Pin Narrow Body SOIC
8. Package Outline: 16-Pin Narrow Body SOIC
The figure below illustrates the package details for the Si864x in a 16-pin narrow-body SOIC (SO-16). The table lists the values for the
dimensions shown in the illustration.
Figure 8.1. 16-Pin Narrow Body SOIC
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Rev. 1.9 | 29
Si864x Data Sheet
Package Outline: 16-Pin Narrow Body SOIC
Table 8.1. 16-Pin Narrow Body SOIC Package Diagram Dimensions1, 2, 3, 4
Dimension
Min
Max
A
—
1.75
A1
0.10
0.25
A2
1.25
—
b
0.31
0.51
c
0.17
0.25
D
9.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L
0.40
L2
1.27
0.25 BSC
h
0.25
0.50
θ
0°
8°
aaa
0.10
bbb
0.20
ccc
0.10
ddd
0.25
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 1.9 | 30
Si864x Data Sheet
Land Pattern: 16-Pin Narrow Body SOIC
9. Land Pattern: 16-Pin Narrow Body SOIC
The figure below illustrates the recommended land pattern details for the Si864x in a 16-pin narrow-body SOIC. The table lists the values for the dimensions shown in the illustration.
Figure 9.1. PCB Land Pattern: 16-Pin Narrow Body SOIC
Table 9.1. 16-Pin Narrow Body SOIC Land Pattern Dimensions1, 2
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 1.9 | 31
Si864x Data Sheet
Package Outline: 16-Pin QSOP
10. Package Outline: 16-Pin QSOP
The figure below illustrates the package details for the Si864x in a 16-pin QSOP package. The table lists the values for the dimensions
shown in the illustration.
Figure 10.1. 16-Pin QSOP
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Rev. 1.9 | 32
Si864x Data Sheet
Package Outline: 16-Pin QSOP
Table 10.1. 16-Pin QSOP Package Diagram Dimensions1, 2, 3, 4
Dimension
Min
Max
A
—
1.75
A1
0.10
0.25
A2
1.25
—
b
0.20
0.30
c
0.17
0.25
D
4.89 BSC
E
6.00 BSC
E1
3.90 BSC
e
0.635 BSC
L
0.40
L2
1.27
0.25 BSC
h
0.25
0.50
θ
0°
8°
aaa
0.10
bbb
0.20
ccc
0.10
ddd
0.25
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body Components.
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Rev. 1.9 | 33
Si864x Data Sheet
Land Pattern: 16-Pin QSOP
11. Land Pattern: 16-Pin QSOP
The figure below illustrates the recommended land pattern details for the Si864x in a 16-pin QSOP package. The table lists the values
for the dimensions shown in the illustration.
Figure 11.1. PCB Land Pattern: 16-Pin QSOP
Table 11.1. 16-Pin Wide Body SOIC Land Pattern Dimensions1, 2
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
0.635
X1
Pad Width
0.40
Y1
Pad Length
1.55
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOP63P602X173-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 1.9 | 34
Si864x Data Sheet
Top Marking: 16-Pin Wide Body SOIC
12. Top Marking: 16-Pin Wide Body SOIC
Si86XYSV
YYWWRTTTTT
e4
TW
Figure 12.1. 16-Pin Wide Body SOIC Top Marking
Table 12.1. 16-Pin Wide Body SOIC Top Marking Explanation
Line 1 Marking:
Base Part Number
Si86 = Isolator product series
Ordering Options
X = # of data channels (4)
(See 1. Ordering Guide for more
information.)
Y = # of reverse channels (5, 2, 1, 0)1
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV; T = 5.0 kV with 10
kV surge capability.
Line 2 Marking:
YY = Year
WW = Workweek
RTTTTT = Mfg Code
Assigned by assembly subcontractor. Corresponds to the year
and workweek of the mold date.
Manufacturing code from assembly house
“R” indicates revision
Line 3 Marking:
Circle = 1.7 mm Diameter
“e4” Pb-Free Symbol
(Center-Justified)
Country of Origin ISO Code Ab- TW = Taiwan
breviation
Note:
1. Si8645 has 0 reverse channels.
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Rev. 1.9 | 35
Si864x Data Sheet
Top Marking: 16-Pin Narrow Body SOIC
13. Top Marking: 16-Pin Narrow Body SOIC
e3
Si86XYSV
YYWWRTTTTT
Figure 13.1. 16-Pin Narrow Body SOIC Top Marking
Table 13.1. 16-Pin Narrow Body SOIC Top Marking Explanation
Line 1 Marking:
Base Part Number
Si86 = Isolator product series
Ordering Options
X = # of data channels (4)
(See 1. Ordering Guide for more
information.)
Y = # of reverse channels (5, 2, 1, 0)1
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Line 2 Marking:
Circle = 1.2 mm Diameter
“e3” Pb-Free Symbol
YY = Year
Assigned by the Assembly House. Corresponds to the year and
work week of the mold date.
WW = Work Week
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Note:
1. Si8645 has 0 reverse channels.
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Rev. 1.9 | 36
Si864x Data Sheet
Top Marking: QSOP
14. Top Marking: QSOP
Figure 14.1. QSOP Top Marking
Table 14.1. QSOP Top Marking Explanation
Line 1 Marking:
Base Part Number
86 = Isolator product series
Ordering Options
X = # of data channels (4)
(See 1. Ordering Guide for more
information.)
Y = # of reverse channels (5, 2, 1, 0)1
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Line 2 Marking:
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Line 3 Marking:
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the year and
work week of the mold date.
Note:
1. Si8645 has 0 reverse channels.
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Rev. 1.9 | 37
Si864x Data Sheet
Document Change List
15. Document Change List
Revision 0.1 to Revision 0.2
• Added chip graphics on page 1.
• Moved Tables 1 and 11 to page 18.
• Updated Table 6, “Insulation and Safety-Related Specifications,” on page 15.
• Updated Table 8, “IEC 60747-5-5 Insulation Characteristics for Si86xxxx*,” on page 16.
• Moved Table 1 to page 4.
• Moved Table 2 to page 5.
• Moved “Typical Performance Characteristics” to page 8.
• Updated "3. Pin Descriptions" on page 9.
• Updated "4. Ordering Guide" on page 10.
Revision 0.2 to Revision 1.0
• Reordered spec tables to conform to new convention.
• Removed “pending” throughout document.
Revision 1.0 to Revision 1.1
• Updated High Level Output Voltage VOH to 3.1 V in Table 3, “Electrical Characteristics,” on page 8.
• Updated High Level Output Voltage VOH to 2.3 V in Table 4, “Electrical Characteristics,” on page 11.
Revision 1.1 to Revision 1.2
• Updated Table 3, “Ordering Guide for Valid OPNs” on page 10.
• Updated Note 1 with MSL2A.
• Updated Current Revision Devices.
Revision 1.2 to Revision 1.3
• Updated "4. Ordering Guide" on page 10 to include MSL2A.
Revision 1.3 to Revision 1.4
• Updated Table 11 on page 18.
• Added junction temperature spec.
• Updated "2.3.1. Supply Bypass" on page 7.
• Removed “3.3.2 Pin Connections” on page 23.
• Updated "3. Pin Descriptions" on page 9.
• Updated table notes.
• Updated "4. Ordering Guide" on page 10.
• Removed Rev A devices.
• Updated "5. Package Outline: 16-Pin Wide Body SOIC" on page 12.
• Updated Top Marks.
• Added revision description.
Revision 1.4 to Revision 1.5
• Updated "4. Ordering Guide" on page 10.
• Updated "11.5. Top Marking (16-Pin QSOP)" on page 22.
Revision 1.5 to Revision 1.6
• Added Figure 3, “Common Mode Transient Immunity Test Circuit,” on page 7.
• Added references to CQC throughout.
• Added references to 2.5 kVRMS devices throughout.
• Updated "4. Ordering Guide" on page 10.
• Updated "11.1. Top Marking (16-Pin Wide Body SOIC)" on page 20.
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Rev. 1.9 | 38
Si864x Data Sheet
Document Change List
Revision 1.6 to Revision 1.7
• Updated Table 5 on page 14.
• Added CQC certificate numbers.
• Updated "4. Ordering Guide" on page 10.
• Added Si8640BA OPN.
• Removed references to moisture sensitivity levels.
• Removed Note 2.
Revision 1.7 to Revision 1.8
• Added product options Si8641BB-B-IU, Si8645BB-B-IU and Si864xxT in 1. Ordering Guide.
• Added spec line items for Input and Enable Leakage Currents pertaining to Si864xxT in Electrical Specifications.
• Added new spec for tSD in 4. Electrical Specifications.
• Updated IEC 60747-5-2 to IEC 60747-5-5 throughout document.
Revision 1.8 to Revision 1.9
• Deleted duplicate Si8641BB-B-IU OPN listing and corrected Si8645BB-B-IU listing in 1. Ordering Guide.
• Added QSOP-16 information to Table 4.7 IEC 60664-1 Ratings on page 21.
• Added QSOP-16 information to Table 4.8 IEC 60747-5-5 Insulation Characteristics for Si86xxxx 1 on page 22.
• Added QSOP-16 information to Table 4.9 IEC Safety Limiting Values 1 on page 22.
• Added QSOP-16 reference to Figure 4.5 (NB SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-5/VDE 0884-10, as Applies on page 23.
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Rev. 1.9 | 39
Table of Contents
1. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Theory of Operation .
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2.2 Eye Diagram .
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3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Device Startup
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3.2 Undervoltage Lockout .
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3.3 Layout Recommendations.
3.3.1 Supply Bypass . . . .
3.3.2 Output Pin Termination .
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3.4 Fail-Safe Operating Mode .
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3.5 Typical Performance Characteristics .
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4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
6. Package Outline: 16-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . .
26
7. Land Pattern: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . .
28
8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . .
29
9. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . .
31
10. Package Outline: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . .
32
11. Land Pattern: 16-Pin QSOP
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34
12. Top Marking: 16-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . . .
35
13. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . .
36
14. Top Marking: QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
15. Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . .
38
Table of Contents
40
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Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
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