CP2130
S INGLE - C HIP USB- T O - S P I B R ID GE
Single-Chip USB-to-SPI Bridge
SPI Controller
Integrated
clock; no external crystal required
Integrated USB transceiver; no external resistors
required
Integrated 348 Byte one-time programmable ROM for
product customization
On-chip power-on reset circuit
On-chip voltage regulator: 3.45 V output
Uses USB Bulk Mode transactions for high throughput
- Configurable priority for reads and writes
USB Peripheral Function Controller
USB
Specification 2.0 compliant; full-speed (12 Mbps)
USB suspend states supported and indicated via
suspend output pins
USB Interface
8®, 7®, Vista®, and XP®
Open access to interface specification
Windows
Windows Libraries
APIs
for quick application development
Supports
Windows 8®, 7®, Vista®, and XP® (SP2 &
SP3)
3
or 4-wire master mode operation
clock rate
- 12 MHz, 6 MHz, 3 MHz, 1.5 MHz, 750 kHz, 375 kHz,
187.5 kHz, 93.75 kHz
Clock phase and polarity control
Chip select mode and toggle
Programmable SPI delay (post-assert, inter-byte, predeassert)
Configurable
11 Configurable GPIO Pins with Alternate Functions
Usable
as inputs, open-drain outputs, or push-pull
outputs
Up to 11 chip select outputs
Ready-to-read pin allows for external signal to trigger
SPI read operations
Ability to count edges or pulses using the Event Counter
Up to 11 USB remote wakeup sources
SPI activity indication (toggles to indicate SPI activity)
Configurable clock output (93.75 kHz to 24 MHz)
Supply Voltage
Self
powered (regulator disabled): 3.0 to 3.6 V
powered (regulator enabled): 3.0 to 5.25 V
USB bus powered: 4.0 to 5.25 V
I/O voltage: 1.8 V to VDD
Self
Packages
RoHS-compliant
24-QFN package (4x4 mm)
Ordering Part Numbers
CP2130-F01-GM
Temperature Range: –40 to +85 °C
CP2130
Connect to VBUS
or External Supply
VREGIN
VDD
USB
Connector
GND
VBUS
VBUS
D+
D+
D-
D-
GND
Voltage
Regulator
48 MHz
Oscillator
USB Interface
Full-Speed
12 Mbps
Transceiver
Peripheral
Function
Controller
MISO
SPI Controller
GPIO
SPI Chip Select
SPI ReadyToRead
RESET
VPP
348 Byte PROM
(Product Customization)
Clock Output
SPI Activity
USB Suspend
Logic Level
Supply
(1.8 V to VDD)
VIO
SCK
To SPI
Slave
Devices
Multi-Function
Signals
SPI Event Counter
Hardware Reset
MOSI
Remote Wakeup
GPIO.0_CS0
GPIO.1_CS1
GPIO.2_CS2
GPIO.3_CS3_RTR
GPIO.4_CS4_EVTCNTR
GPIO.5_CS5_CLKOUT
GPIO.6_CS6
GPIO.7_CS7
GPIO.8_CS8_SPIACT
MultiFunction
Signals to
External
Circuitry
GPIO.9_CS9_SUSPEND
GPIO.10_CS10_SUSPEND
I/O Power and Logic Levels
Figure 1. Example System Diagram
Rev. 0.7 1/14
Copyright © 2014 by Silicon Laboratories
CP2130
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
CP2130
2
Rev. 0.7
CP2130
TABLE O F C ONTENTS
Section
Page
1. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. USB Function Controller and Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2. Data Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3. Serial Clock Phase and Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1. GPIO.3—Ready-to-Read (RTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2. GPIO.4—Event Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3. GPIO.5—Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4. GPIO.8—SPI Activity Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5. GPIO.9-10—SUSPEND and SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6. USB Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.7. GPIO State During USB Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. One-Time Programmable ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
8. CP2130 Interface Specification and Windows Interface DLL . . . . . . . . . . . . . . . . . . . . .20
9. Relevant Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
11. QFN-24 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Rev. 0.7
3
CP2130
1. System Overview
The CP2130 is a highly-integrated USB-to-SPI bridge controller providing a simple solution for bridging a Universal
Serial Bus (USB) host to a Serial Peripheral Interface (SPI) bus using a minimum of components and PCB space.
The CP2130 includes a USB 2.0 full-speed controller, USB transceiver, oscillator, one-time programmable (OTP)
ROM, and a SPI controller in a compact 4 x 4 mm QFN24 package (sometimes called “MLF” or “MLP”).
The on-chip, OTP ROM provides the option to customize the USB Vendor ID, Product ID, Manufacturer String,
Product Description String, Power Descriptor, Device Release Number, Device Serial Number, and GPIO
configuration as desired for OEM applications.
The CP2130 uses a Silicon Labs vendor-specific USB protocol using control and bulk transfers which is supported
by most operating systems through the use of generic USB drivers and interface libraries. A custom driver typically
does not need to be developed for this device. Windows applications communicate with the CP2130 through a
Windows DLL which is provided by Silicon Labs that communicates with the Microsoft WinUSB driver via a
WinUSB DLL. The interface specification for the CP2130 is also available to enable development of an API for any
operating system that supports control and bulk transfers over USB.
The CP2130 SPI implements the standard signals, including SCK, MISO, MOSI, CS, as well as a ready-to-read
(RTR) hardware handshaking input, so existing system firmware does not need to be modified. The SPI
capabilities of the CP2130 include fixed SPI clock rates ranging from 93.75 kHz to 12 MHz, configurable clock
phase, configurable clock polarity, adjustable SPI delays, and up to 11 configurable chip select signals.
Any of the multi-purpose pins not used as chip select signals may instead be used as GPIO signals that are userdefined. The GPIO signals may also be configured to initiate a USB remote wakeup event on GPIO state change,
which allows the CP2130 to wake a USB host from sleep mode. Eight of the GPIO signals support alternate
features including ready-to-read (RTR) handshaking, a configurable event counter, a configurable clock output
(93.75 kHz to 24 MHz), SPI activity LED toggle, and USB suspend indicators. Support for I/O interface voltages
down to 1.8 V is provided via a VIO pin.
An evaluation kit for the CP2130 (Part Number: CP2130EK) is available. It includes a CP2130-based USB-to-SPI
evaluation board with SPI slave devices such as an EEPROM and ADC as well as connections for an external
CP2400 LCD controller EVB and SPI monitor. The kit also includes a Windows DLL and test application, USB
cables, and full documentation. See www.silabs.com for the latest application notes and product support
information for the CP2130. Contact a Silicon Labs sales representatives or go to www.silabs.com to order the
CP2130 Evaluation Kit.
4
Rev. 0.7
CP2130
2. Electrical Characteristics
Table 1. Global DC Electrical Characteristics
VDD = 3.0 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Symbol
Digital Supply Voltage
Test Condition
Min
Typ
Max
Unit
VDD
3.0
—
3.6
V
Digital Port I/O Supply
Voltage
VIO
1.8
—
VDD
V
Specified Operating
Temperature Range
TA
–40
—
+85
°C
Thermal Resistance1
θJA
—
28
—
°C/W
Bus Powered; Regulator enabled
—
170
360
µA
Self Powered; Regulator disabled; VDD = 3.0 V
—
170
290
µA
Self Powered; Regulator disabled; VDD = 3.3 V
—
210
330
µA
Bus Powered; Regulator enabled
—
14.4
18.8
mA
Self Powered; Regulator disabled; VDD = 3.0 V
—
13.8
18.1
mA
Self Powered; Regulator disabled; VDD = 3.3 V
—
14.1
18.4
mA
Bus Powered; Regulator enabled
—
17.8
23.2
mA
Self Powered; Regulator disabled; VDD = 3.0 V
—
16.6
21.7
mA
Self Powered; Regulator disabled; VDD = 3.3 V
—
17.1
22.2
mA
—
200
230
µA
Supply Current
USB Suspended2
USB Normal; SPI Idle2
IREGIN
USB Normal; SPI
Active2
USB Pull-up3
IPU
Notes:
1. Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad.
2. USB Pull-up current should be added for total supply current. USB normal and suspended supply current is current
flowing into VREGIN. USB normal and suspended supply current is guaranteed by characterization.
3. The USB Pull-up supply current values are calculated values based on USB specifications. USB Pull-up supply current
is current flowing from VDD to GND through USB pull-down/pull-up resistors on D+ and D-.
Rev. 0.7
5
CP2130
Table 2. SPI, Port I/O, and Suspend I/O DC Electrical Characteristics
VIO = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters
Symbol
Test Condition
Min
Typ
Max
Unit
VOH
IOH = –10 µA, Port I/O push-pull
IOH = –3 mA, Port I/O push-pull
IOH = –10 mA, Port I/O push-pull
VIO – 0.1
VIO – 0.2
—
—
—
VIO – 0.4
—
—
—
V
VOL
IOL = 10 µA
IOL = 8.5 mA
IOL = 25 mA
—
—
—
—
—
0.6
0.1
0.4
—
V
Output High Voltage
Output Low Voltage
Input High Voltage
VIH
0.7 x VIO
—
—
V
Input Low Voltage
VIL
—
—
0.6
V
Weak Pull-Up On, VIN = 0 V
—
25
50
µA
Open drain, logic high (1)
—
—
5.8
V
Input Leakage Current
IL
Maximum Input Voltage
Table 3. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
VDD Ramp Time
Symbol
Test Condition
Min
Typ
Max
Unit
tRMP
Time to VDD ≥ 2.7 V
—
—
1
ms
RST Input High Voltage
VIHRESET
0.75 x VIO
—
—
V
RST Input Low Voltage
VILRESET
—
—
0.6
V
tRSTL
15
—
—
µs
RST Low Time to
Generate a System Reset
Table 4. Voltage Regulator Electrical Specifications
–40 to +85 °C unless otherwise specified.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input Voltage Range1
VREGIN
Regulator Enabled
VDD + VDO
—
5.25
V
Output Voltage2
VDDOUT
Output Current = 1 to 100 mA
3.3
3.45
3.6
V
VBUS Detection Input
Threshold
VBUSTH
2.5
—
—
V
—
1
—
mV / mA
—
—
120
µA
Dropout Voltage
VDO
1 mA ≤ IDD ≤ 100 mA
Bias Current
Notes:
1. Input range specified for regulation. When the internal regulator is not used, should be tied to VDD.
2. The maximum regulator supply current is 100 mA. This includes the supply current of the CP2130.
6
Rev. 0.7
CP2130
Table 5. GPIO Output Specifications
–40 to +85 °C unless otherwise specified.
Parameter
Symbol
Test Condition
GPIO.5 Clock Output*
FCLKOUT
SPI Activity Toggle Rate
FSPIACT
Min
FCLKOUT = configured FCLKOUT x
frequency
0.985
Typ
Max
Unit
FCLKOUT
FCLKOUT x
1.015
Hz
10
—
Hz
—
*Note: The clock output frequency is configurable from 93.75 kHz to 24 MHz.
Table 6. USB Transceiver Electrical Characteristics*
VDD = 3.0 V to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Transmitter
Output High Voltage
VOH
2.8
—
—
V
Output Low Voltage
VOL
—
—
0.8
V
Output Crossover Point
VCRS
1.3
—
2.0
V
Output Impedance
ZDRV
Driving High
Driving Low
—
—
36
36
—
—
Pull-up Resistance
RPU
Full Speed (D+ Pull-up)
1.425
1.5
1.575
k
Output Rise Time
TR
Full Speed
4
—
20
ns
Output Fall Time
TF
Full Speed
4
—
20
ns
Differential Input Sensitivity
VDI
| (D+) - (D-) |
0.2
—
—
V
Differential Input Common
Mode Range
VCM
0.8
—
2.5
V
—
<1.0
—
µA
Receiver
Input Leakage Current
IL
Pullups Disabled
*Note: Refer to the USB Specification for timing diagrams and symbol definitions.
Table 7. OTP ROM Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Symbol
Digital Port I/O Supply Voltage
During Programming
VIO
Voltage on VPP with respect to GND during a
programming operation
VPP
Capacitor on VPP for In-system Programming
Rev. 0.7
Test Condition
VIO > 3.3 V
Min
Typ
Max
Unit
3.3
—
VDD
V
5.75
—
VIO +
3.6
V
—
4.7
—
µF
7
CP2130
Table 8. Thermal Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
*
θJA
—
28
—
°C/W
Thermal Resistance
*Note: Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad.
Table 9. Absolute Maximum Ratings*
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Ambient Temperature under Bias
TBIAS
–55
—
125
°C
Storage Temperature
TSTG
–65
—
150
°C
VIO > 2.2 V
VIO < 2.2 V
–0.3
–0.3
—
—
5.8
VIO + 3.6
V
VDD > 3.0 V
VDD not powered
–0.3
–0.3
—
—
5.8
VDD + 3.6
V
–0.3
—
4.2
V
Maximum Total Current through VDD,
VIO, REGIN, and GND
—
—
500
mA
Maximum Output Current Sunk by RST or
any I/O pin
—
—
100
mA
Voltage on RST, GPIO, or SPI Pins with
respect to GND
Voltage on VBUS with respect to GND
VBUS
Voltage on VDD or VIO with respect to GND
VDD
*Note: Stresses above those listed may cause permanent damage to the device. This is a stress rating only, and functional
operation of the devices at or exceeding the conditions in the operation listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.
8
Rev. 0.7
CP2130
3. USB Function Controller and Transceiver
The Universal Serial Bus (USB) function controller in the CP2130 is a USB 2.0-compliant, full-speed device with
integrated transceiver and on-chip matching and pullup resistors. The USB function controller manages all data
transfers between the USB and the SPI bus as well as command requests generated by the USB host and
commands for controlling the function of the SPI and GPIO pins.
The USB Suspend and Resume modes are supported for power management of both the CP2130 device as well
as external circuitry. The CP2130 enters Suspend mode when Suspend signaling is detected on the bus. Upon
entering Suspend mode, the Suspend signals are asserted. The Suspend signals are also asserted after a CP2130
reset until device configuration and USB Enumeration is complete. SUSPEND is logic high when the device is in
the Suspend state, and logic low when the device is in normal mode. The SUSPEND pin has the opposite logic
value of the SUSPEND pin.
The CP2130 exits Suspend mode when any of the following occur: Resume signaling is detected or generated, a
USB Reset signal is detected, the configured GPIO wakeup sources do not match the configured latch value, or a
device reset occurs. SUSPEND and SUSPEND are weakly pulled to VIO in a high impedance state during a
CP2130 reset. If this behavior is undesirable, a strong pulldown (10 k) can be used to ensure SUSPEND remains
low during reset.
The CP2130 can be configured to use any of the GPIO pins as a remote wakeup source. While suspended, if any
of the pins configured as a wakeup source does not match the configured wakeup match value, then the CP2130
will send remote wakeup signaling to the USB host. If the host has configured the CP2130 to enable remote
wakeup, then the host will send resume signaling to the CP2130 and the device will exit Suspend mode.
The logic level and output mode (push-pull or open-drain) of various pins during USB Suspend is configurable in
the OTP ROM. See Section 6 for more information.
Rev. 0.7
9
CP2130
4. Serial Peripheral Interface (SPI)
The CP2130 Serial Peripheral Interface (SPI) provides access to a flexible, full-duplex synchronous serial bus. The
CP2130 can operate as a master device in both 3-wire or 4-wire modes, and supports multiple slaves. Any of the
11 GPIO pins may be configured as chip select master outputs to select multiple SPI slave devices.
4.1. Signal Descriptions
The four signals used by SPI (MOSI, MISO, SCK, CS) are described below.
4.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used
to serially transfer data from the master to the slave. Data is transferred most-significant bit first.
4.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is
used to serially transfer data from the slave to the master. Data is transferred most-significant bit first.
4.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to
synchronize the transfer of data between the master and slave on the MOSI and MISO lines. Since the CP2130
always acts as a SPI master, it always drives SCK.
4.1.4. Chip Select (CS0 - CS10)
The CP2130 may be used to control up to 11 different SPI slave devices using GPIO pins configured in chip select
output mode. Chip select signals are active low.
See Figure 2 and Figure 3 for typical connection diagrams of the various operational modes.
Master Device
Slave Device
SCK
SCK
MISO
MISO
MOSI
MOSI
Figure 2. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
Master Device
Slave Device
SCK
SCK
MISO
MISO
MOSI
MOSI
CS0
CS
CS1
Slave Device
SCK
MISO
MOSI
CS
Figure 3. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
10
Rev. 0.7
CP2130
4.2. Data Throughput
SPI read and write data transfer throughput can be affected by many factors including USB host performance, host
driver and PC application performance, SPI clock rate, and data transfer size. Also USB bulk transfers are limited
by available bandwidth on the bus; increased traffic on the bus may decrease SPI throughput. Additionally, the
CP2130 can be configured to operate in high-priority write or high-priority read mode. The priority mode is
configured in the OTP ROM. The CP2130 has two independent USB endpoints used for bulk data transfers. The
first endpoint is double buffered whereas the second endpoint is single buffered. Each endpoint is used for only a
single direction. A USB IN transfer is data transferred from the device to the host. A USB OUT transfer is data
transferred from the host to the device. More information about the USB interface can be found in application note,
“AN792: CP2130 Interface Specification”. By default, the CP2130 is configured in high-priority write mode, in which
the double-buffered endpoint is used for OUT transfers and the single-buffered endpoint is used for IN transfers.
Conversely, when the CP2130 is configured in high-priority read mode, the double-buffered endpoint is used for IN
transfers and the single-buffered endpoint is used for OUT transfers.
Table 10 below shows the CP2130 typical SPI throughput in high-priority write and high-priority read modes using
a 64-bit PC.
Table 10. Typical SPI Throughput
Device Configuration
High-Priority Write Mode
High-Priority Read Mode
Conditions
Write
Throughput
Read
Throughput
WriteRead
Throughput
Units
FSCK = 12 MHz;
Block Size = 64 KB
4.9
4.6
3.5
Mbps
4.2
6.6
2.9
Mbps
4.3. Serial Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using SPI control commands over the USB
interface. The clock phase (CPHA) specifies which clock edge is used to latch the data. The clock polarity (CPOL)
selects between an active-high or active-low clock. Both master and slave devices must be configured to use the
same clock phase and polarity. The clock and data line relationships are shown in Figure 4.
The SPI clock field of the SPI control command controls the master mode serial clock frequency. The clock
frequency is restricted to discrete values between 93.8 kHz and 12 MHz.
SCK
(CPHA=Leading Edge, CPOL=Active High)
SCK
(CPHA=Trailing Edge, CPOL=Active High)
SCK
(CPHA=Leading Edge, CPOL=Active Low)
SCK
(CPHA=Trailing Edge, CPOL=Active Low)
MISO/MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Figure 4. Data/Clock Timing
Rev. 0.7
11
CP2130
SCK Shift Edge
SCK*
1 / FSCK
TMIS
TMIH
MISO
MOSI
* SCK is shown for CPOL = Active High. SCK is the opposite polarity for CPOL = Active Low.
Figure 5. SPI Master Timing (CPHA=Leading Edge)
SCK Shift Edge
SCK*
TMIS
TMIH
MISO
MOSI
* SCK is shown for CPOL = Active High. SCK is the opposite polarity for CPOL = Active Low.
Figure 6. SPI Master Timing (CPHA=Trailing Edge)
12
Rev. 0.7
CP2130
CS
TPOST‐ASSERT
TPRE‐DEASSERT
SCK*
TINTER‐BYTE DELAY
MISO/MOSI
MSB
LSB
MSB
LSB
* SCK is shown for CPOL = Active High. SCK is the opposite polarity for CPOL = Active Low.
Figure 7. SPI Delays (CPHA = Leading Edge)
CS
TPOST‐ASSERT
TPRE‐DEASSERT
SCK*
TINTER‐BYTE DELAY
MISO/MOSI
MSB
LSB
MSB
LSB
* SCK is shown for CPOL = Active High. SCK is the opposite polarity for CPOL = Active Low.
Figure 8. SPI Delays (CPHA = Trailing Edge)
Table 11. SPI Timing Parameters1
Parameter
Symbol
Min
Typ
Max
Units
12 MHz
6 MHz
3 MHz
1.5 MHz
750 kHz
375 kHz
187.5 kHz
93.75 kHz
SCK Frequency
FSCK
MISO Valid to SCK Shift Edge
TMIS
41.15
—
—
ns
SCK Shift Edge to MISO Change
TMIH
0
—
—
ns
Post-Assert SPI Delay2
Inter-Byte SPI Delay2
Pre-Deassert SPI Delay2
TPOST-ASSERT
N x 10
µs
TINTER-BYTE
N x 10
µs
TPRE-DEASSERT
N x 10
µs
Notes:
1. See Figures 5–8.
2. N = user-specified delay values, where {0 ≤ N ≤ 65535}.
Rev. 0.7
13
CP2130
5. GPIO Pins
The CP2130 supports 11 user-configurable GPIO pins. Each of these GPIO pins are usable as inputs, open-drain
outputs, or push-pull outputs. Each GPIO pin may also be configured for use as SPI chip select signals for up to 11
different SPI slaves. Six of these GPIO pins also have alternate functions which are listed in Table 12. More
information regarding the configuration and usage of these pins is available in application note, “AN721: CP21xx
Customization Guide” available on the Silicon Labs website.
Table 12. GPIO Pin Alternate Functions
GPIO Pin
Alternate Function
GPIO.3
Ready-to-Read (RTR)
GPIO.4
Event Counter
GPIO.5
Clock Output
GPIO.8
SPI Activity
GPIO.9
SUSPEND
GPIO.10
SUSPEND
The default configuration for all of the GPIO pins is provided in Table 13. The configuration of the pins is one-time
programmable for each device. See Section 6 for more information about programming the GPIO pin functionality.
Table 13. GPIO Pin Default Configuration
GPIO Pin
Default Function
GPIO Pin
Default Function
GPIO.0
CS0 (Push-Pull Output)
GPIO.6
GPIO (Input)
GPIO.1
CS1 (Push-Pull Output)
GPIO.7
GPIO (Push-Pull Output)
GPIO.2
CS2 (Push-Pull Output)
GPIO.8
SPI Activity (Push-Pull Output)
GPIO.3
RTR Active Low (Input)
GPIO.9
SUSPEND (Push-Pull Output)
GPIO.4
Event Counter Rising Edge (Input)
GPIO.10
SUSPEND (Push-Pull Output)
GPIO.5
Clock Output (Push-Pull Output)
The difference between an open-drain output and a push-pull output is evident when the GPIO output is driven to
logic high. A logic high, open-drain output pulls the pin to the VIO rail through an internal, pull-up resistor. A logic
high, push-pull output directly drives the pin to the VIO voltage. Open-drain outputs are typically used when
interfacing to logic at a higher voltage than the VIO pin. These pins can be safely pulled to the higher, external
voltage through an external pull-up resistor. The maximum external pull-up voltage is 5 V.
The speed of reading and writing the GPIO pins is subject to the timing of the USB interface and host computer.
GPIO pins configured as inputs or outputs are not recommended for real-time signaling.
The following paragraphs describe the alternate functions available on the corresponding GPIO pin.
14
Rev. 0.7
CP2130
5.1. GPIO.3—Ready-to-Read (RTR)
RTR, or Ready-to-Read, is a configurable active-low or active-high input to the CP2130 and is used by the SPI
slave device to indicate to the CP2130 when to read. When performing a Read with RTR command, the CP2130
will only read SPI data when the RTR pin is asserted.
By default, GPIO.3 is configured to operate as the RTR input pin. In addition to the GPIO OTP ROM configuration,
the device must be configured to use RTR flow control to use this pin.
Master Device
Slave Device
MISO
MISO
MOSI
MOSI
SCK
SCK
RTR
RTR
Figure 9. Hardware Flow Control Typical Connection Diagram
5.2. GPIO.4—Event Counter
GPIO.4 is configurable as an event counter digital input pin. The event counter can be configured to count edges or
pulses. The four configurable modes are: rising edge, falling edge, positive pulse, or negative pulse. Once
configured for event counter mode, the CP2130 maintains a 16-bit counter that increments by ‘1’ whenever the
specified edge or pulse is detected. The user may query the CP2130 to get the current event count. The event
counter can be used to detect slave interrupt events by connecting the slave interrupt output pin to the CP2130
event counter pin.
5.3. GPIO.5—Clock Output
GPIO.5 is configurable to output a configurable CMOS clock output. The clock output appears at the pin at the
same time the device completes enumeration and exits USB Suspend mode. The clock output is removed from the
pin when the device enters USB Suspend mode. The output frequency is configurable through the use of a divider
and the accuracy is specified in Table 5. When the divider is set to 0, the output frequency is 93.75 kHz. For divider
values between 1 and 255, the output frequency is determined by the formula:
24 MHz
GPIO.5 Clock Frequency = --------------------Divider
Equation 1. GPIO.0 Clock Output Frequency
Rev. 0.7
15
CP2130
5.4. GPIO.8—SPI Activity Indicator
GPIO.8 is configurable as a SPI activity indicator pin. This pin is logic high when a device is not transferring data
over the SPI, and toggles at a fixed rate as specified in Table 5 when a data transfer is in progress. Typically, this
pin is connected to an LED to indicate data transfer.
VIO
CP2130
GPIO.8 – SPI Activity
Figure 10. SPI Activity Toggle Typical Connection Diagram
5.5. GPIO.9-10—SUSPEND and SUSPEND
GPIO.9 and GPIO.10 are configurable as active-high SUSPEND and active-low SUSPEND pins. The SUSPEND
pin is logic high when the device is in the suspended state and logic low when the device is in the active mode. The
SUSPEND pin has the opposite logic value of the SUSPEND pin.
5.6. USB Remote Wakeup
Any of the GPIO pins may be used to trigger a USB remote wakeup event. Before the CP2130 enters the Suspend
state, the device may be configured to wakeup on a port mismatch event. When any of the pins specified in the
wakeup mask do not match the pin logic value specified in the wakeup value, the CP2130 will wakeup and signal
remote wakeup on the bus. The CP2130 will assert USB remote wakeup signaling for 10 to 15 ms before the host
may respond by resuming the CP2130.
Any GPIO pin used for remote wakeup must be configured as an input during the Suspend state. GPIO pins are
selected as wakeup pins using the Wakeup Match Mask. The Wakeup Match Value specifies the logic level of the
wakeup pin. When the pin level does not match the value specified, the device will wakeup. The default Wakeup
Match Mask and Wakeup Match Value are shown in Table 15.
5.7. GPIO State During USB Suspend
All GPIO pins support programmable suspend state mode and latch values. When the CP2130 enter USB
Suspend mode and the Use Suspend Mode and Values option is set, the CP2130 will reconfigure the GPIO pins
just prior to entering USB Suspend mode. When the CP2130 resumes from USB Suspend mode, the GPIO pins
revert to the previous function configurations and modes.
16
Rev. 0.7
CP2130
6. One-Time Programmable ROM
The CP2130 includes an internal, OTP ROM that may be used to customize the USB Vendor ID (VID), Product ID
(PID), Manufacturer String, Product Description String, Power Descriptor, Device Release Number, Device Serial
Number, GPIO configuration, Suspend Pins and Modes as desired for OEM applications. If the OTP ROM has not
been customized, the default configuration data shown in Table 14 and Table 15 is used.
Table 14. Default USB Configuration Data
Name
Value
Vendor ID
0x10C4
Product ID
0x87A0
Power Descriptor (Attributes)
0x80 (Bus-powered)
Power Descriptor (Max. Power)
0x32 (100 mA)
Release Number
0x0100 (Release Version 01.00)
Transfer Priority
High Priority Write
Manufacturer String
“Silicon Laboratories” (62 ASCII characters maximum)
Product Description String
“CP2130 USB-to-SPI Bridge” (62 ASCII characters maximum)
Serial String
Unique 8 character ASCII string (30 ASCII characters maximum)
Table 15. Default GPIO, UART, and Suspend Configuration Data
Name
Value
Name
Value
GPIO.0
CS0 push-pull output
Use Suspend Mode
and Values
False
GPIO.1
CS1 push-pull output
Suspend Mode
0x0000 (open-drain)
GPIO.2
CS2 push-pull output
Suspend Latch
0x0000 (logic low)
GPIO.3
RTR active low
Wakeup Match Mask
0x0000 (ignore all)
GPIO.4
Event counter rising edge
Wakeup Match Value
0x0000 (match value logic low)
GPIO.5
Clock output
Clock Divider
0 (93.75 kHz)
GPIO.6
GPIO input
GPIO.7
GPIO push-pull output
GPIO.8
SPI activity push-pull output
GPIO.9
SUSPEND push-pull output
GPIO.10
SUSPEND push-pull output
While customization of the USB configuration data is optional, customizing the VID/PID combination is strongly
recommended. A unique VID/PID will prevent the device from being recognized by any other manufacturer’s
software application. A vendor ID can be obtained from www.usb.org or Silicon Labs can provide a free PID for the
OEM product that can be used with the Silicon Labs VID at www.silabs.com/RequestPID. All CP2130 devices are
pre-programmed with a unique serial number. It is important to have a unique serial string if it is possible for
multiple CP2130 devices to be connected to the same PC.
Application note, “AN792: CP2130 Interface Specification”, includes more information about the programmable
values and their valid options. Note that certain items in the OTP ROM are programmed as a group and
programming one of the items in the group prevents further programming of any of the other items in the group.
The configuration data OTP ROM is programmable by Silicon Labs prior to shipment with the desired configuration
information. It can also be programmed in-system over the USB interface if a 4.7 µF capacitor is connected
between the VPP pin and ground. No other circuitry should be connected to VPP during a programming operation,
and VIO must remain at 3.3 V or higher to successfully write to the configuration OTP ROM.
Rev. 0.7
17
CP2130
7. Voltage Regulator
The CP2130 includes an on-chip 5 V to 3.45 V voltage regulator. This allows the CP2130 to be configured as either
a USB bus-powered device or a USB self-powered device. A typical connection diagram of the device in a buspowered application using the regulator is shown in Figure 11. When enabled, the voltage regulator output appears
on the VDD pin and can be used to power external devices. See Table 4 for the voltage regulator electrical
characteristics.
Note: By default, the CP2130 is configured for bus-powered operation. The CP2130 OTP configuration must be changed if the
device will be operated in either of the self-powered modes.
If the regulator is used to provide VDD in a self-powered application, use the same connections from Figure 11, but
connect REGIN to an on-board 5 V supply, and disconnect it from the VBUS pin. In addition, if REGIN may be
unpowered while VBUS is 5 V, a resistor divider (or functionally equivalent circuit) shown in Note 6 of Figure 12 is
required to meet the absolute maximum voltage on VBUS specification in Table 9.
VIO
Note 4
4.7 kohm
Note 1
3.45 V Power
4.7 F
VIO
VDD
0.1 F
CP2130
RST
SUSPEND
SUSPEND
VPP
Suspend
Signals
Note 5
4.7 F
REGIN
1 F
0.1 F
SCK
MOSI
MISO
GPIO.0 / CS0
GND
GPIO.1 / CS1
GPIO.2 / CS2
USB
Connector
Shield
VBUS
VBUS
GPIO.3 / CS3 / RTR
D+
D+
GPIO.4 / CS4 / EVTCNTR
D-
D-
GPIO.5 / CS5 / CLKOUT
GND
SPI
and
GPIO
Signals
GPIO.6 / CS6
GPIO.7 / CS7
GPIO.8 / CS8 / SPIACT
0.1 F 1 Mohm 0.1 F
Note 2
GPIO.9 / CS9 / SUSPEND
GPIO.10 / CS10 / SUSPEND
Note 3
Notes:
1. VIO can be connected directly to VDD or to a supply as low as 1.8 V to set the I/O interface voltage.
2. USB connector shield decoupling capacitors and resistor are not required, but can be added for noise immunity.
3. Avalanche transient voltage suppression diodes compatible with Full-speed USB should be added at the
connector for ESD protection. Use Littelfuse p/n SP0503BAHT or equivalent.
4. An external pull-up is not required, but can be added for noise immunity.
5. If programming the configuration ROM via USB, add a 4.7 F capacitor between VPP and ground.
During a programming operation, do not connect the VPP pin to other circuitry, and ensure that VIO is at least 3.3 V.
Figure 11. Typical Bus-Powered Connection Diagram
18
Rev. 0.7
CP2130
Alternatively, if 3.0 to 3.6 V power is supplied to the VDD pin, the CP2130 can function as a USB self-powered
device with the voltage regulator bypassed. For this configuration, tie the REGIN input to VDD to bypass the voltage
regulator. A typical connection diagram showing the device in a self-powered application with the regulator
bypassed is shown in Figure 12.
The USB max power and power attributes descriptor must match the device power usage and configuration. See
application note, “AN721: CP21xx Customization Guide”, for information on how to customize USB descriptors for
the CP2130.
Note 1
3.3 V
Power
VIO
CP2130
VIO Note 4
VDD
4.7 F
4.7 kohm
0.1 F
RST
SUSPEND
SUSPEND
REGIN
1 F
0.1 F
VPP
Suspend
Signals
Note 5
4.7 F
GND
SCK
MOSI
Note 6
(Optional)
MISO
24 k
GPIO.0 / CS0
VBUS
47 k
USB
Connector
Shield
GPIO.1 / CS1
GPIO.2 / CS2
VBUS
GPIO.3 / CS3 / RTR
D+
D+
GPIO.4 / CS4 / EVTCNTR
D-
D-
GPIO.5 / CS5 / CLKOUT
GND
SPI
and
GPIO
Signals
GPIO.6 / CS6 / MMACK
GPIO.7 / CS7 / MMREQ
GPIO.8 / CS8 / SPIACT
0.1 F 1 Mohm 0.1 F
Note 2
GPIO.9 / CS9 / SUSPEND
GPIO.10 / CS10 / SUSPEND
Note 3
Notes:
1. VIO can be connected directly to VDD or to a supply as low as 1.8 V to set the I/O interface voltage.
2. USB connector shield decoupling capacitors and resistor are not required, but can be added for noise immunity.
3. Avalanche transient voltage suppression diodes compatible with Full-speed USB should be added at the
connector for ESD protection. Use Littelfuse p/n SP0503BAHT or equivalent.
4. An external pull-up is not required, but can be added for noise immunity.
5. If programming the configuration ROM via USB, add a 4.7 F capacitor between VPP and ground.
During a programming operation, do not connect the VPP pin to other circuitry, and ensure that VIO is at least 3.3 V.
6. For self-powered systems where VDD and VIO may be unpowered when VBUS is connected to 5 V, a resistor
divider (or functionally-equivalent circuit) on VBUS is required to meet the absolute maximum voltage on VBUS
specification in the Electrical Characteristics section.
Figure 12. Typical Self-Powered Connection Diagram (Regulator Bypass)
Rev. 0.7
19
CP2130
8. CP2130 Interface Specification and Windows Interface DLL
The CP2130 is a Bulk Mode USB device and requires a generic USB driver such as Microsoft’s WinUSB driver or
the open-source LibUSB driver. The CP2130 uses a vendor-specific interface protocol, and so the host application
or library must comply with the CP2130 Interface Specification to communicate with the device. The low-level USB
specification for the CP2130 is provided in application note, “AN792: CP2130 Interface Specification.” This
document describes all of the basic functions for opening, reading from, writing to, and closing the device as well
as the OTP ROM programming functions.
Silicon Labs also provides an interface library that encapsulates the CP2130 interface and also adds higher level
features such as read/write time-outs. This library is the recommended interface for the CP2130. The interface
library is provided as a Windows DLL. Documentation for the interface library API is included in the installation
package.
AN792: CP2130 Interface Specification and the library are available in the CP2130EK CD as well as online at:
www.silabs.com.
9. Relevant Application Notes
The following application notes are applicable to the CP2130. The latest versions of these application notes and
their accompanying software are available at
http://www.silabs.com/products/Interface/Pages/interface-application-notes.aspx.
AN721: CP21xx Device Customization Guide. This application note describes how to use the AN721
software, CP21xx Customization Utility, to configure the USB parameters on CP2130 devices.
AN792: CP2130 Interface Specification. This application note describes how to interface to the CP2130 using
the low-level, USB bulk and control mode Interface.
20
Rev. 0.7
CP2130
MISO
MOSI
GPIO.0 / CS0
GPIO.1 / CS1
GPIO.2 / CS2
GPIO.3 / CS3 / RTR
24
23
22
21
20
19
10. Pin Descriptions
SCK
1
18
GPIO.4 / CS4 / EVTCNTR
GND
2
17
GPIO.5 / CS5 / CLKOUT
D+
3
16
VPP
D-
4
15
GPIO.6 / CS6
VIO
5
14
GPIO.7 / CS7
VDD
6
13
GPIO.8 / CS8 / SPIACT
CP2130-GM
Top View
9
10
11
12
N/C
GPIO.10 / CS10 / SUSPEND
GPIO.9 / CS9 / SUSPEND
8
VBUS
RST
7
REGIN
GND (optional)
Figure 13. QFN-24 Pinout Diagram (Top View)
Rev. 0.7
21
CP2130
Table 16. CP2130 Pin Definitions
Pin #
Name
Type
Description
1
SCK
D Out
2
GND
3
D+
D I/O
USB D+
4
D–
D I/O
USB D–
5
VIO
Power In I/O Supply Voltage Input.
6
VDD
Power In Power Supply Voltage Input.
SPI clock output
Ground. Must be tied to ground.
Power Out Voltage Regulator Output. See Section 7.
7
REGIN
8
VBUS
D In
VBUS Sense Input. This pin should be connected to the VBUS signal of a USB
network.
9
RST
D I/O
Device Reset. Open-drain output of internal power-on reset or VDD monitor. An
external source can initiate a system reset by driving this pin low for the time
specified in Table 3.
10*
N/C
11*
GPIO.10
D I/O
In GPIO mode, this pin is a user-configurable input or output.
CS10
D Out
In chip select mode, this pin is a SPI chip select output.
SUSPEND
D Out
In USB suspend mode, this pin is Low when in USB suspend mode.
GPIO.9
D I/O
In GPIO mode, this pin is a user-configurable input or output.
CS9
D Out
In chip select mode, this pin is a SPI chip select output.
SUSPEND
D Out
In USB suspend mode, this pin is High when in USB suspend mode.
GPIO.8
D I/O
In GPIO mode, this pin is a user-configurable input or output.
CS8
D Out
In chip select mode, this pin is a SPI chip select output.
SPIACT
D Out
In SPI activity mode, this pin toggles to indicate SPI activity.
GPIO.7
D I/O
In GPIO mode, this pin is a user-configurable input or output.
CS7
D Out
In chip select mode, this pin is a SPI chip select output.
GPIO.6
D I/O
In GPIO mode, this pin is a user-configurable input or output.
CS6
D Out
In chip select mode, this pin is a SPI chip select output.
VPP
Special
12*
13*
14*
15*
16*
Power In 5 V Regulator Input. This pin is the input to the on-chip voltage regulator.
No connect. This pin should be left unconnected or tied to VIO.
Connect a 4.7 µF capacitor between this pin and ground to support OTP ROM
programming via the USB interface.
*Note: Pin can be left unconnected when not in use.
22
Rev. 0.7
CP2130
Table 16. CP2130 Pin Definitions (Continued)
Pin #
Name
Type
17*
GPIO.5
D I/O
In GPIO mode, this pin is a user-configurable input or output.
CS5
D Out
In chip select mode, this pin is a SPI chip select output.
CLKOUT
D Out
In clock output mode, this pin outputs a configurable frequency clock signal.
GPIO.4
D I/O
In GPIO mode, this pin is a user-configurable input or output.
CS4
D Out
In chip select mode, this pin is a SPI chip select output.
EVTCNTR
D In
In event counter mode, this pin is an event counter input.
GPIO.3
D I/O
In GPIO mode, this pin is a user-configurable input or output.
CS3
D Out
In chip select mode, this pin is a SPI chip select output.
RTR
D In
In Ready-to-Read mode, this pin is a SPI read flow control input.
GPIO.2
D I/O
In GPIO mode, this pin is a user-configurable input or output.
CS2
D Out
In chip select mode, this pin is a SPI chip select output.
GPIO.1
D I/O
In GPIO mode, this pin is a user-configurable input or output.
CS1
D Out
In chip select mode, this pin is a SPI chip select output.
GPIO.0
D I/O
In GPIO mode, this pin is a user-configurable input or output.
CS0
D Out
In chip select mode, this pin is a SPI chip select output.
23
MOSI
D Out
SPI master output/slave input
24
MISO
D In
SPI master input/slave output
18*
19*
20*
21*
22*
Description
*Note: Pin can be left unconnected when not in use.
Rev. 0.7
23
CP2130
11. QFN-24 Package Specifications
Figure 14. QFN-24 Package Drawing
Table 17. QFN-24 Package Dimensions
Dimension
Min
Typ
Max
Dimension
Min
Typ
Max
A
A1
b
D
D2
e
E
E2
0.70
0.00
0.18
0.75
0.02
0.25
4.00 BSC.
2.70
0.50 BSC.
4.00 BSC.
2.70
0.80
0.05
0.30
L
L1
aaa
bbb
ddd
eee
Z
Y
0.30
0.00
—
—
—
—
—
—
0.40
—
—
—
—
—
0.24
0.18
0.50
0.15
0.15
0.10
0.05
0.08
—
—
2.55
2.55
2.80
2.80
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
24
Rev. 0.7
CP2130
12. PCB Land Pattern
Figure 15. QFN-24 Recommended PCB Land Pattern
Table 18. QFN-24 PCB Land Pattern Dimensions
Dimension
Min
Max
Dimension
Min
Max
C1
C2
E
X1
3.90
3.90
4.00
4.00
X2
Y1
Y2
2.70
0.65
2.70
2.80
0.75
2.80
0.50 BSC
0.20
0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2 x 2 array of 1.10 x 1.10 mm openings on a 1.30 mm pitch should be used for the center
pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 0.7
25
CP2130
DOCUMENT CHANGE LIST
Revision 0.5 to Revision 0.6
Updated pin configuration functions for GPIO.6 and
GPIO.7.
Revision 0.6 to Revision 0.7
Moved VBUS to a separate row and updated the
specification in Table 9, “Absolute Maximum
Ratings*,” on page 8.
Added VPP Voltage specification to Table 7, “OTP
ROM Electrical Characteristics,” on page 7.
Updated "7. Voltage Regulator" on page 18 to add
absolute maximum voltage on VBUS requirements
in self-powered systems.
Updated measured throughput numbers in Table 10,
“Typical SPI Throughput,” on page 11.
26
Rev. 0.7
CP2130
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any
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consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where
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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
Rev. 0.7
27