CY7C65211 CY7C65211A (UART/I2C/SPI) ® USB-Serial Single-Channel Bridge with CapSense and BCD USB-Serial Single-Channel (UART/I2C/SPI) Bridge with CapSense® and BCD Features CapSense Charger detection ❐ GPIO ❐ USB 2.0-certified, Full-Speed (12 Mbps) ❐ Supports communication driver class (CDC), personal health care device class (PHDC), and vendor-device class ❐ Battery charger detection (BCD) compliant with USB Battery Charging Specification, Rev. 1.2 (Peripheral Detect only) ❐ Integrated USB termination resistors ■ Single-channel configurable UART interface ❐ Data rates up to 3 Mbps ❐ 190 bytes for each transmit and receive buffer ❐ Supports 2-pin,4-pin and 6-pin UART interface ❐ Data format: • 7 to 8 data bits • 1 to 2 stop bits • No parity, even, odd, mark, or space parity ❐ Supports parity, overrun, and framing errors ❐ Supports flow control using CTS, RTS, DTR, DSR ❐ Supports UART break signal ❐ CY7C65211 supports single channel RS232/RS422 interfaces whereas CY7C65211A supports RS232/RS422/RS485 interfaces ■ Single-channel configurable SPI interface ❐ Data rate up to 3 MHz for SPI master and 1 MHz for SPI slave ❐ Data width: 4 bits to 16 bits ❐ 256 bytes for each transmit and receive buffer ❐ Supports Motorola, TI, and National SPI modes 2 ■ Single-channel configurable I C interface ❐ Master/slave up to 400 kHz ❐ 256 bytes each transmit and receive buffer 2 ❐ Supports multi-master I C ® ■ CapSense ❐ SmartSense™ Auto-Tuning is supported through a Cypress-supplied configuration utility ❐ Max CapSense buttons: 5 ❐ GPIOs linked to CapSense buttons ❐ ■ ■ General-purpose input/output (GPIO) pins: 10 ■ Supports unique serial number feature for each device, which fixes the COM port number permanently when USB-serial Bridge controller as CDC device plugs in ■ Driver support for VCOM and DLL ❐ Windows 10: 32- and 64-bit versions ❐ Windows 8.1: 32- and 64-bit versions ❐ Windows 8: 32- and 64-bit versions ❐ Windows 7: 32- and 64-bit versions ❐ Windows Vista: 32- and 64-bit versions ❐ Windows XP: 32- and 64-bit versions ❐ Windows CE ❐ Mac OS-X: 10.6, 10.7 ❐ Linux: Kernel version 2.6.35 onwards. ❐ Android: Gingerbread and later versions ■ Clocking: Integrated 48-MHz clock oscillator ■ Supports bus-/self-powered configurations ■ USB Suspend mode for low power ■ Operating voltage: 1.71 to 5.5 V ■ Operating temperature: ❐ Commercial: 0 °C to 70 °C ❐ Industrial: –40 °C to 85 °C ■ ESD protection: 2.2-kV HBM ■ RoHS-compliant package ❐ 24-pin QFN (4.0 mm × 4.0 mm, 0.55 mm, 0.5 mm pitch) ■ Ordering part number ❐ CY7C65211-24LTXI ❐ CY7C65211A-24LTXI Applications ■ Medical/healthcare devices ■ Point-of-Sale (POS) terminals ■ Test and measurement system ■ Gaming systems ■ Set-top box PC-USB interface ■ Industrial ■ 512-byte flash for storing configuration parameters ■ Networking ■ Configuration utility (Windows) to configure the following: ❐ Vendor ID (VID), Product ID (PID), and Product and Manufacturer descriptors ❐ UART/I2C/SPI ■ Enabling USB connectivity in legacy peripherals Functional Description For a complete list of related resources, click here. USB-Compliant The USB-Serial Single-Channel Bridge with CapSense and BCD (CY7C65211/CY7C65211A) is fully compliant with the USB 2.0 specification and Battery Charging Specification v1.2, USB-IF Test-ID (TID) 40001521. Cypress Semiconductor Corporation Document Number: 001-82042 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 24, 2015 CY7C65211 CY7C65211A CY7C65211 and CY7C65211A Features Comparison Table 1. CY7C65211 and CY7C65211A Features Comparison Features CY7C65211 CY7C65211A USB Product ID 0x002 0x00FB UART Can be configured as Virtual COM port or USB vendor device Can be configured as Virtual COM port or USB vendor device I2C Can be configured as USB vendor device Can be configured as Virtual COM port or USB vendor device SPI Can be configured as USB vendor device Can be configured as Virtual COM port or USB vendor device RS485 Support No Yes More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the document USB-Serial Bridge Controller Product Overview. ■ Overview: USB Portfolio, USB Roadmap ■ Code Examples: USB Full-Speed ■ USB 2.0 Product Selectors: USB-Serial Bridge Controller, USB to UART Controller (Gen I) ■ Development Kits: ❐ CYUSBS232, Cypress USB-UART LP Reference Design Kit ❐ CYUSBS234, Cypress USB-Serial (Single Channel) Development Kit ❐ CYUSBS236, Cypress USB-Serial (Dual Channel) Development Kit Knowledge Base Articles: Cypress offers a large number of USB knowledge base articles covering a broad range of topics, from basic to advanced level. Recommended knowledge base articles for getting started with USB-Serial Bridge Controller are: ® ❐ KBA85909 – Key Features of the Cypress USB-Serial Bridge Controller ❐ KBA85920 – USB-UART and USB-Serial ❐ KBA85921 – Replacing FT232R with CY7C65213 USB-UART LP Bridge Controller ❐ KBA85913 – Voltage supply range for USB-Serial ❐ KBA89355 – USB Serial Cypress Default VID and PID ❐ KBA92641 – USB-Serial Bridge Controller Managing I/Os using API ❐ KBA92442 – Non-Standard Baud Rates in USB-Serial Bridge Controllers ❐ KBA91366 – Binding a USB-Serial Device to a Microsoft® CDC Driver ❐ KBA92551 – Testing a USB-Serial Bridge Controller Configured as USB-UART with Linux® ❐ KBA91299 – Interfacing an External I2C Device with the CYUSBS234/236 DVK For complete list of knowledge base articles, click here. ■ Document Number: 001-82042 Rev. *I ■ Models: IBIS Cypress USB-Serial (Single Channel) Development Kit The Cypress USB-Serial (Single Channel) Development Kit is a complete development resource. It provides a platform to develop and test custom projects. The development kit contains collateral materials for the firmware, hardware, and software aspects of a design. Page 2 of 34 CY7C65211 CY7C65211A Contents Block Diagram – CY7C65211/CY7C65211A .................... 4 Functional Overview ........................................................ 4 USB and Charger Detect ............................................. 4 Serial Communication ................................................. 4 CapSense .................................................................... 5 GPIO Interface ............................................................ 5 Memory ....................................................................... 5 System Resources ...................................................... 5 Suspend and Resume ................................................. 5 WAKEUP ..................................................................... 6 Software ...................................................................... 6 Internal Flash Configuration ........................................ 7 Electrical Specifications .................................................. 8 Absolute Maximum Ratings ......................................... 8 Operating Conditions ................................................... 8 Device-Level Specifications ........................................ 8 GPIO ........................................................................... 9 nXRES ....................................................................... 10 SPI Specifications ..................................................... 11 I2C Specifications ...................................................... 13 CapSense Specifications .......................................... 13 Flash Memory Specifications .................................... 13 Pin Description ............................................................... 14 USB Power Configurations ............................................ 16 USB Bus-Powered Configuration .............................. 16 Document Number: 001-82042 Rev. *I Self-Powered Configuration ...................................... 17 USB Bus-Powered with Variable I/O Voltage ............ 18 Application Examples .................................................... 19 USB to RS232 Bridge ................................................ 19 USB to RS485 Bridge ................................................ 20 Battery-Operated, Bus-Powered USB to MCU with Battery Charge Detection .......................................... 21 CapSense .................................................................. 23 USB to I2C Bridge ..................................................... 24 USB to SPI Bridge ..................................................... 25 Ordering Information ...................................................... 29 Ordering Code Definitions ......................................... 29 Package Information ...................................................... 30 Acronyms ........................................................................ 31 Document Conventions ................................................. 31 Units of Measure ....................................................... 31 Document History Page ................................................. 32 Sales, Solutions, and Legal Information ...................... 34 Worldwide Sales and Design Support ....................... 34 Products .................................................................... 34 PSoC® Solutions ...................................................... 34 Cypress Developer Community ................................. 34 Technical Support ..................................................... 34 Page 3 of 34 CY7C65211 CY7C65211A Block Diagram – CY7C65211/CY7C65211A nXRES VDDD VCCD Voltage Regulator Reset Internal 48 MHz OSC Internal 32 KHz OSC USB VBUS BCD USBDP USBDM 256 Bytes TX Buffer VBUS Regulator 256 Bytes RX Buffer Battery Charger Detection USB Transceiver with Integrated Resistor SIE Functional Overview The CY7C65211/CY7C65211A is a Full-Speed USB controller that enables seamless PC connectivity for peripherals with serial interfaces, such as UART, SPI, and I2C. CY7C65211/CY7C65211A also integrates CapSense and BCD compliant with the USB Battery Charging Specification, Rev. 1.2. It integrates a voltage regulator, an oscillator, and flash memory for storing configuration parameters, offering a cost-effective solution. CY7C65211 supports bus-powered and self-powered modes and enables efficient system power management with suspend and remote wake-up signals. It is available in a 24-pin QFN package. USB and Charger Detect USB CY7C65211/CY7C65211A has a built-in USB 2.0 Full-Speed transceiver. The transceiver incorporates the internal USB series termination resistors on the USB data lines and a 1.5-k pull-up resistor on USBDP. Charger Detection CY7C65211/CY7C65211A supports BCD for Peripheral Detect only and complies with the USB Battery Charging Specification, Rev. 1.2. It supports the following charging ports: ■ Standard Downstream Port (SDP): Allows the system to draw up to 500 mA current from the host ■ Charging Downstream Port (CDP): Allows the system to draw up to 1.5 A current from the host ■ Dedicated Charging Port (DCP): Allows the system to draw up to 1.5 A of current from the wall charger Serial Communication CY7C65211/CY7C65211A has a serial communication block (SCB). Each SCB can implement UART, SPI, or I2C interface. A 256-byte buffer is available in both the TX and RX lines. UART Interface The UART interface provides asynchronous serial communication with other UART devices operating at speeds of up to 3 Mbps. It supports 7 to 8 data bits, 1 to 2 stop bits, odd, Document Number: 001-82042 Rev. *I Serial Communication Block 512 Bytes Flash Memory UART/ SPI/I2C CapSense GPIO UART/SPI/I2C CapSense GPIO even, mark, space, and no parity. The UART interface supports full-duplex communication with a signaling format that is compatible with the standard UART protocol. In CY7C65211, UART pins may be interfaced to industry standard RS232/RS422 transceivers whereas in CY7C65211A these UART pins may be interfaced to RS232/RS422/RS485. Common UART functions, such as parity error and frame error, are supported. CY7C65211/CY7C65211A supports baud rates ranging from 300 baud to 3 Mbaud. The UART baud rates can be set using the configuration utility. Notes: Parity error gets detected when UART transmitter device is configured for odd parity and UART receiver device is configured for even parity. Frame error gets detected when UART transmitter device is configured for 7 bits data width and 1 stop bit, whereas UART receiver device is configured for 8 bit data width and 2 stop bits. UART Flow Control The CY7C65211 device supports UART hardware flow control using control signal pairs, such as RTS# (Request to Send) / CTS# (Clear to Send) and DTR# (Data Terminal Ready) / DSR# (Data Set Ready). Data flow control is enabled by default. Flow control can be disabled using the configuration utility. The following section describes the flow control signals: ■ CTS# (Input) / RTS# (Output) CTS# can pause or resume data transmission over the UART interface. Data transmission can be paused by de-asserting the CTS signal and resumed with CTS# assertion. The pause and resume operation does not affect data integrity. With flow control enabled, receive buffer has a watermark level of 93%. After the data in the receive buffer reaches that level, the RTS# signal is de-asserted, instructing the transmitting device to stop data transmission. The start of data consumption by application reduces the device data backlog; when it reaches the 75% watermark level, the RTS# signal is asserted to resume data reception. ■ DSR# (Input) /DTR# (Output) Page 4 of 34 CY7C65211 CY7C65211A The DSR#/DTR# signals are used to establish a communication link with the UART. These signals complement each other in their functionality, similar to CTS# and RTS#. SPI Interface The SPI interface supports an SPI Master and SPI Slave. This interface supports the Motorola, TI, and National Microwire protocols. The maximum frequency of operation is 3 MHz in SPI master mode and 1 MHz in SPI slave mode. It can support transaction sizes ranging from 4 bits to 16 bits in length, SPI slave supports 4 bits to 8 bits and 12 bits to 16 bits data width at 1 MHz operation. Whereas, it supports 9 bits,10 bits and 11 bits data width operation at 500 kHz operation. (refer to USB to SPI Bridge on page 25 for more details). I2C Interface The I2C interface implements full multi-master/slave modes and supports up to 400 kHz. The configuration utility tool is used to set the I2C address in the slave mode. The tool enables only even slave addresses. For further details on the protocol, refer to the NXP I2C specification, Rev. 5. Notes 2 ■ I C ports are not tolerant of higher voltages. Therefore, they cannot be hot-swapped or powered up independently when chip is not powered. ■ The minimum fall time of the SCL is met (as per NXP I2C specification Rev. 5) when VDDD is between 1.71 V and 3.0 V. When VDDD is within the range of 3.0 V to 3.6 V, it is recommended to add a 50 pF capacitor on the SCL signal. CapSense CapSense functionality is supported on all the GPIO pins. Any GPIO pin can be configured as a sense pin (CS0–CS7) using the configuration utility. When implementing CapSense functionality, the GPIO_0 pin (configured as a modulator capacitor - Cmod) should be connected to ground through a 2.2-nF capacitor (see Figure 13 on page 23). CY7C65211 supports SmartSense Auto-Tuning of the CapSense parameters and does not require manual tuning. SmartSense Auto-tuning compensates for printed circuit board (PCB) variations and device process variations. Optionally, any GPIO pin can be configured as a Cshield and connected to the shield of the CapSense button, as shown in Figure 13 on page 23. Shield prevents false triggering of buttons due to water droplets and guarantees CapSense operation (sensors respond to finger touch). GPIOs can be linked to the CapSense buttons to indicate the presence of a finger. CapSense functionality can be configured using the configuration utility. CY7C65211 supports up to five CapSense buttons. For more information on CapSense, refer to Getting Started with CapSense. GPIO Interface CY7C65211/CY7C65211A has 10 GPIOs. The maximum available GPIOs for configuration is 10 if one two-pin (I2C/2-pin UART) serial interface is implemented. The configuration utility allows configuration of the GPIO pins. The configurable options are as follows: Document Number: 001-82042 Rev. *I TRISTATE: GPIO tristated ■ DRIVE 1: Output static 1 ■ DRIVE 0: Output static 0 ■ POWER#: Power control for bus power designs ■ TXLED#: Drives LED during USB transmit ■ RXLED#: Drives LED during USB receive ■ TX or RX LED#: Drives LED during USB transmit or receive ■ GPIO can be configured to drive LED at 8-mA drive strength. ■ BCD0/BCD1: Two-pin output to indicate the type of USB charger ■ BUSDETECT: Connects the VBUS pin for USB host detection ■ CS0–CS4: CapSense button input (Sense pin) ■ CSout0–CSout2: Indicates which CapSense button is pressed ■ Cmod: External modulator capacitor; connects a 2.2-nF capacitor (±10%) to ground (GPIO_0 only) ■ Cshield: Shield for waterproofing Memory CY7C65211/CY7C65211A has a 512-byte flash. Flash is used to store USB parameters, such as VID/PID, serial number, product and manufacturer descriptors, which can be programmed by the configuration utility. System Resources Power System CY7C65211/CY7C65211A supports the USB Suspend mode to control power usage. CY7C65211 operates in bus-powered or self-powered modes over a range of 3.15 to 5.5 V. Clock System CY7C65211/CY7C65211A has a fully integrated clock with no external components required. The clock system is responsible for providing clocks to all subsystems. Internal 48-MHz Oscillator The internal 48-MHz oscillator is the primary source of internal clocking in CY7C65211. Internal 32-kHz Oscillator The internal 32-kHz oscillator is primarily used to generate clocks for peripheral operation in the USB Suspend mode. Reset The reset block ensures reliable power-on reset and brings the device back to the default known state. The nXRES (active low) pin can be used by the external devices to reset the CY7C65211/CY7C65211A. Suspend and Resume The CY7C65211/CY7C65211A device asserts the SUSPEND pin when the USB bus enters the suspend state. This helps in meeting the stringent suspend current requirement of the USB 2.0 specification, while using the device in bus-powered mode. The device resumes from the suspend state under either of the two following conditions: 1. Any activity is detected on the USB bus Page 5 of 34 CY7C65211 CY7C65211A 2. The WAKEUP pin is asserted to generate remote wakeup to the host WAKEUP The WAKEUP pin is used to generate the remote wakeup signal on the USB bus. The remote wakeup signal is sent only if the host enables this feature through the SET_FEATURE request. The device communicates support for the remote wakeup to the host through the configuration descriptor during the USB enumeration process. The CY7C65211/CY7C65211A device allows enabling/disabling and polarity of the remote wakeup feature through the configuration utility. Software Cypress delivers a complete set of software drivers and a configuration utility to enable configuration of the product during system development. Drivers for Linux Operating Systems Cypress provides a User Mode USB driver library (libcyusbserial.so) that abstracts vendor commands for the UART interface and provides a simplified API interface for user applications. This library uses the standard open-source libUSB library to enable USB communication. The Cypress serial library supports the USB plug-and-play feature using the Linux 'udev' mechanism. CY7C65211/CY7C65211A supports the standard USB CDC UART class driver, which is bundled with the Linux kernel. Android Support The CY7C65211/CY7C65211A solution includes an Android Java class–CyUsbSerial.java–which exposes a set of interface functions to communicate with the device. library–CyUSBSerial DLL–that abstracts a vendor-specific interface of the CY7C65211/CY7C65211A devices and provides convenient APIs to the user. It provides interface APIs for vendor-specific UART/SPI/I2C and class-specific APIs for PHDC. USB-Serial Bridge Controller works with the Windows-standard USB CDC class driver, when either CY7C65211 is configured as CDC USB to UART device or when CY7C65211A is configured as CDC USB to UART/SPI/I2C device. A virtual COM port driver–CyUSBSerial.sys–is also delivered, which implements the USB CDC class driver. The Cypress Windows drivers are Windows hardware certification kit-compliant. These drivers are bound to device through WU (Windows Update) services. Cypress drivers also support Windows plug-and-play and power management and USB Remote Wake-up. Windows-CE support The CY7C65211/CY7C65211A solution includes a CDC UART driver library for Windows-CE platforms. Device Configuration Utility (Windows only) A Windows-based configuration utility is available to configure device initialization parameters. This graphical user application provides an interactive interface to define the boot parameters stored in the device flash. This utility allows the user to save a user-selected configuration to text or xml formats. It also allows users to load a selected configuration from text or xml formats. The configuration utility allows the following operations: ■ View current device configuration ■ Select and configure UART/I2C/SPI, CapSense, battery charging, and GPIOs ■ Configure USB VID, PID, and string descriptors ■ Save or Load configuration Drivers for Mac OSx Cypress delivers a dynamically linked shared library (CyUSBSerial.dylib) based on libUSB, which enables communication to the CY7C65211 device. In addition, the CY7C65211 device also supports the native Mac OSx CDC UART driver, and CY7C65211A supports native Mac OSx CDC UART/SPI/I2C driver. You can download the free configuration utility and drivers at www.cypress.com. Drivers for Windows Operating Systems For Windows operating systems (XP, Vista, Win7, Win 8, and Win 8.1), Cypress delivers a user-mode dynamically linked Document Number: 001-82042 Rev. *I Page 6 of 34 CY7C65211 CY7C65211A Internal Flash Configuration The internal flash memory can be used to store the configuration parameters shown in the following table. A free configuration utility is provided to configure the parameters listed in the table to meet application-specific requirements over the USB interface. The configuration utility can be downloaded at www.cypress.com/go/usbserial. Table 2. Internal Flash Configuration for both CY7C65211 and CY7C65211A Parameter Default Value Description USB Vendor ID (VID) 0x04B4 Default Cypress VID. Can be configured to customer VID USB Product ID (PID) 0x0002 for CY7C65211 and 0x00FB for CY7C65211A Default Cypress PID. Can be configured to customer PID USB Configuration Manufacturer string Product string Cypress Can be configured with any string up-to 64 characters USB-Serial (Single Channel) Can be configured with any string up-to 64 characters Serial string Can be configured with any string up-to 64 characters Power mode Bus powered Max current draw 100 mA Remote wakeup Enabled USB interface protocol CDC BCD Disabled GPIO_0 TXLED# GPIO_1 RXLED# GPIO_2 DSR# Can be configured to bus-powered or self-powered mode Can be configured to any value from 0 to 500 mA. The configuration descriptor will be updated based on this,. Can be disabled. Remote wakeup is initiated by asserting the WAKEUP pin Can be configured to function in CDC, PHDC, or Cypress vendor class Charger detect is disabled by default. When BCD is enabled, three of the GPIOs must be configured for BCD GPIO Configuration GPIO_3 RTS# GPIO_4 CTS# GPIO_5 TxD GPIO_6 RxD GPIO_7 DTR# GPIO_8 TRISTATE GPIO_9 TRISTATE GPIO_10 TRISTATE GPIO_11 POWER# Document Number: 001-82042 Rev. *I GPIO can be configured as shown in Table 15 on page 15. Page 7 of 34 CY7C65211 CY7C65211A Electrical Specifications Absolute Maximum Ratings Static discharge voltage ESD protection levels: Exceeding maximum ratings[1] may shorten the useful life of the device. Storage temperature .................................... –55 °C to +100 °C Ambient temperature with power supplied (Industrial) ............................ –40 °C to +85 °C ■ 2.2-KV HBM per JESD22-A114 Latch-up current .......................................................... . 140 mA Current per GPIO ........................................................... 25 mA Operating Conditions Supply voltage to ground potential VDDD ................................................................................. 6.0 V TA (ambient temperature under bias) Industrial ........................................................ –40 °C to +85 °C VBUS ................................................................................. 6.0 V VBUS supply voltage ........................................ 3.15 V to 5.25 V VCCD ............................................................................... 1.95 V VDDD supply voltage ........................................ 1.71 V to 5.50 V VGPIO ................................................................... VDDD + 0.5 V VCCD supply voltage ........................................ 1.71 V to 1.89 V Device-Level Specifications All specifications are valid for –40 °C TA 85 °C, TJ 100 °C, and 1.71 V to 5.50 V, except where noted. Table 3. DC Specifications Parameter VBUS VDDD Description VBUS supply voltage VDDD supply voltage Min Typ Max Units Details/Conditions 3.15 3.30 3.45 V 4.35 5.00 5.25 V Set and configure the correct voltage range using a configuration utility for VBUS. Default 5 V. 1.71 1.80 1.89 V 2.0 3.3 5.5 V – 1.80 – V Do not use this supply to drive the external device. • 1.71 V VDDD 1.89 V: Short the VCCD pin with the VDDD pin • VDDD > 2 V – connect a 1-µF capacitor (Cefc) between the VCCD pin and ground 1.00 1.30 1.60 µF X5R ceramic or better Used to set I/O and core voltage. Set and configure the correct voltage range using a configuration utility for VDDD. Default 3.3 V. VCCD Output voltage (for core logic) Cefc External regulator voltage bypass IDD1 Operating supply current – 20 – mA USB 2.0 FS, UART at 1-Mbps single channel, no GPIO switching. IDD2 USB Suspend supply current – 5 – µA Does not include current through a pull-up resistor on USBDP. In USB suspend mode, the D+ voltage can go up to a maximum of 3.8 V. Min Typ Max Units Table 4. AC Specifications Parameter Description Zout USB driver output impedance 28 – 44 Twakeup Wakeup from USB Suspend mode – 25 – µs Details/Conditions Note 1. Usage above the Absolute Maximum conditions may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification. Document Number: 001-82042 Rev. *I Page 8 of 34 CY7C65211 CY7C65211A GPIO Table 5. GPIO DC Specification Parameter Description Min Typ Max Units Details/Conditions VIH[2] Input voltage high threshold 0.7 × VDDD – – V CMOS Input VIL Input voltage low threshold – – 0.3 × VDDD V CMOS Input VIH[2] LVTTL input, VDDD< 2.7 V 0.7 × VDDD – – V VIL LVTTL input, VDDD < 2.7V – – 0.3 × VDDD V VIH[2] LVTTL input, VDDD > 2.7V 2 – – V VIL LVTTL input, VDDD > 2.7V – – 0.8 V VOH CMOS output voltage high level VDDD – 0.4 – – V IOH = 4 mA, VDDD = 5 V +/- 10% VOH CMOS output voltage high level VDDD – 0.6 – – V IOH = 4 mA, VDDD = 3.3 V +/- 10% VOH CMOS output voltage high level VDDD – 0.5 – – V IOH = 1 mA, VDDD = 1.8 V +/- 5% VOL CMOS output voltage low level – – 0.4 V IOL = 8 mA, VDDD = 5 V +/- 10% VOL CMOS output voltage low level – – 0.6 V IOL = 8 mA, VDDD = 3.3 V +/- 10% VOL CMOS output voltage low level – – 0.6 V IOL = 4 mA, VDDD = 1.8 V +/- 5% Rpullup Pull-up resistor 3.5 5.6 8.5 kΩ Rpulldown Pull-down resistor 3.5 5.6 8.5 kΩ IIL Input leakage current (absolute value) – – 2 nA CIN Input capacitance – – 7 pF Vhysttl Input hysteresis LVTTL; VDDD > 2.7 V 25 40 C mV Vhyscmos Input hysteresis CMOS 0.05 × VDDD – – mV Min Typ Max Units 25 °C, VDDD = 3.0 V Table 6. GPIO AC Specification Parameter Description Details/Conditions TRiseFast1 Rise Time in Fast mode 2 – 12 ns VDDD = 3.3 V/ 5.5 V, Cload = 25 pF TFallFast1 Fall Time in Fast mode 2 – 12 ns VDDD = 3.3 V/ 5.5 V, Cload = 25 pF TRiseSlow1 Rise Time in Slow mode 10 – 60 ns VDDD = 3.3 V/ 5.5 V, Cload = 25 pF TFallSlow1 Fall Time in Slow mode 10 – 60 ns VDDD = 3.3 V/ 5.5 V, Cload = 25 pF TRiseFast2 Rise Time in Fast mode 2 – 20 ns VDDD = 1.8 V, Cload = 25 pF TFallFast2 Fall Time in Fast mode 20 – 100 ns VDDD = 1.8 V, Cload = 25 pF TRiseSlow2 Rise Time in Slow mode 2 – 20 ns VDDD = 1.8 V, Cload = 25 pF TFallSlow2 Fall Time in Slow mode 20 – 100 ns VDDD = 1.8 V, Cload = 25 pF Note 2. VIH must not exceed VDDD + 0.2 V. Document Number: 001-82042 Rev. *I Page 9 of 34 CY7C65211 CY7C65211A nXRES Table 7. nXRES DC Specifications Parameter Description Min Typ Max Units VIH Input voltage high threshold 0.7 × VDDD – – V VIL Input voltage low threshold – – 0.3 × VDDD V Rpullup Pull-up resistor 3.5 5.6 8.5 kΩ CIN Input capacitance – 5 – pF Vhysxres Input voltage hysteresis – 100 – mV Min Typ Max Units 1 – – µs Min Typ Max Units 0.3 – 3000 kbps Details/Conditions Table 8. nXRES AC Specifications Parameter Tresetwidth Description Reset pulse width Details/Conditions Table 9. UART AC Specifications Parameter FUART Description UART bit rate Document Number: 001-82042 Rev. *I Details/Conditions Page 10 of 34 CY7C65211 CY7C65211A SPI Specifications Figure 1. SPI Master Timing FSPI SCK (CPOL=0, Output) SCK (CPOL=1, Output) TDSI MISO (input) MSB LSB TDMO MOSI (output) THMO MSB LSB SPI Master Timing for CPHA = 0 (Refer to Table 15) FSPI SCK (CPOL=0, Output) SCK (CPOL=1, Output) TDSI MISO (input) LSB TDMO MOSI (output) MSB THMO LSB MSB SPI Master Timing for CPHA = 1 (Refer to Table 15) Document Number: 001-82042 Rev. *I Page 11 of 34 CY7C65211 CY7C65211A Figure 2. SPI Slave Timing SSN (Input) SCK (CPOL=0, Input) FSPI TSSELSCK SCK (CPOL=1, Input) TDSO MISO (Output) THSO LSB MSB LSB MSB TDMI MOSI (Input) SPI Slave Timing for CPHA = 0 (Refer to Table 15) SSN (Input) FSPI SCK (CPOL=0, Input) TSSELSCK SCK (CPOL=1, Input) TDSO MISO (Ouput) THSO LSB MSB LSB MSB TDMI MOSI (Input) SPI Slave Timing for CPHA = 1 (Refer to Table 15) Document Number: 001-82042 Rev. *I Page 12 of 34 CY7C65211 CY7C65211A Table 10. SPI AC Specifications Parameter Description Min Typ Max Units FSPI SPI operating frequency (Master/Slave) – – 3 MHz WLSPI SPI word length 4 – 16 bits Details/Conditions SPI Master Mode TDMO MOSI valid after SClock driving edge – – 15 ns TDSI MISO valid before SClock capturing edge 20 – – ns THMO Previous MOSI data hold time with respect to capturing edge at slave 0 – – ns TDMI MOSI valid before Sclock Capturing edge 40 – – ns TDSO MISO valid after Sclock driving edge – – 104.4 ns THSO Previous MISO data hold time 0 – – ns TSSELSCK SSEL valid to first SCK Valid edge 100 – – ns Min Typ Max Units 1 – 400 kHz Min Typ Max Units 1.71 – 5.50 V 5 – – Ratio Sensor capacitance range of 9 to 35 pF; finger capacitance > 0.1 pF sensitivity Details/Conditions SPI Slave Mode I2C Specifications Table 11. I2C AC Specifications Parameter FI2C Description I2C frequency Details/Conditions CapSense Specifications Table 12. CapSense AC Specifications Parameter Description VCSD Voltage range of operation SNR Ratio of counts of finger to noise Details/Conditions Flash Memory Specifications Table 13. Flash Memory Specifications Parameter Description Fend Flash endurance Fret Flash retention. TA 85 °C, 10 K program/erase cycles Document Number: 001-82042 Rev. *I Min Typ Max Units 100K – – cycles 10 – – years Page 13 of 34 CY7C65211 CY7C65211A – 10 USBIO USBDP – 11 USBIO USBDM – 12 Power VCCD – 13 14 Power nXRES VSSD nXRES – – 15 16 17 18 19 20 Power Power Power GPIO GPIO SCB/GPIO VBUS VSSD VSSA GPIO_0 GPIO_1 SCB_1 GPIO_2 – – – TXLED# RXLED# DSR# 21 SCB/GPIO SCB_2 GPIO_3 RTS# 22 SCB/GPIO SCB_3 GPIO_4 CTS# 23 SCB/GPIO SCB_4 GPIO_5 TxD 24 Power VDDD – VSSD 3 GPIO_8 4 GPIO_9 5 GPIO_10 6 SCB_2/GPIO_3 SCB_1/GPIO_2 GPIO_1 20 19 CY7C65211/ CY7C65211A -24QFN Top View 18 GPIO_0 17 VSSA 16 VSSD 15 VBUS 14 13 12 WAKEUP 2 VCCD Input 1 SCB_5/GPIO_7 11 9 SCB_0/GPIO_6 USBDM – TRISTATE TRISTATE TRISTATE POWER# – SCB_3/GPIO_4 VSSD GPIO_8 GPIO_9 GPIO_10 GPIO_11 SUSPEND 21 Power GPIO GPIO GPIO GPIO Output 10 3 4 5 6 7 8 USBDP DTR# SCB_4/GPIO_5 GPIO_7 22 SCB_5 9 SCB/GPIO WAKEUP 2 SCB/GPIO. See Table 14 and Table 15 on page 15. SCB/GPIO. See Table 14 and Table 15 on page 15. Digital Ground GPIO. See Table 15 GPIO. See Table 15 GPIO. See Table 15 GPIO. See Table 15 Indicates device in suspend mode. Can be configured as active low/high using the configuration utility Wakeup device from suspend mode. Can be configured as active low/high using the configuration utility USB Data Signal Plus, integrates termination resistor and a 1.5-k pull-up resistor USB Data Signal Minus, integrates termination resistor This pin should be decoupled to ground using a 1-µF capacitor or by connecting a 1.8-V supply Digital Ground Chip reset, active low. Can be left unconnected or have a pull-up resistor connected if not used VBUS Supply, 3.15 V to 5.25 V Digital Ground Analog Ground GPIO. See Table 15 GPIO. See Table 15 SCB/GPIO. See Table 14 and Table 15 on page 15. SCB/GPIO. See Table 14 and Table 15 on page 15. SCB/GPIO. See Table 14 and Table 15 on page 15. SCB/GPIO. See Table 14 and Table 15 on page 15. Supply to the device core and Interface, 1.71 to 5.5 V VDDD RxD 24 GPIO_6 Name 8 Description SCB_0 7 Defualt SCB/GPIO GPIO_11 Type 1 SUSPEND Pin[3] 23 Pin Description nXRES VSSD Note 3. Any pin acting as an Input pin should not be left unconnected. Document Number: 001-82042 Rev. *I Page 14 of 34 CY7C65211 CY7C65211A Table 14. Serial Communication Block Configuration Pin Serial Port Mode 0* Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 4-pin UART RxD 2-pin UART RxD SPI Master GPIO_6 SPI Slave GPIO_6 I2C Master GPIO_6 I2C Slave GPIO_6 1 SCB_0 6-pin UART RxD 20 SCB_1 DSR# GPIO_2 GPIO_2 SSEL_OUT SSEL_IN GPIO_2 GPIO_2 21 SCB_2 RTS# RTS# GPIO_3 MISO_IN MISO_OUT SCL_OUT SCL_IN 22 SCB_3 CTS# CTS# GPIO_4 MOSI_OUT MOSI_IN SDA SDA 23 SCB_4 TxD TxD TxD SCLK_OUT SCLK_IN GPIO_5 GPIO_5 2 SCB_5 DTR# GPIO_7 GPIO_7 GPIO_7 GPIO_7 GPIO_7 GPIO_7 *Note: The device is configured in Mode 0 as the default. Other modes can be configured using the configuration utility provided by Cypress. GPIO SCB Table 15. GPIO Configuration GPIO Configuration Option TRISTATE Description I/O tristated DRIVE 1 Output static 1 DRIVE 0 Output static 0 POWER# This output is used to control power to an external logic through a switch to cut power off during an unconfigured USB device and USB suspend. 0 - USB device in Configured state 1 - USB device in Unconfigured state or during USB suspend mode TXLED# Drives LED during USB transmit RXLED# Drives LED during USB receive TX or RX LED# BCD0 BCD1 BUSDETECT Drives LED during USB transmit or receive Configurable battery charger detect pins to indicate the type of USB charger (SDP, CDP, or DCP) Configuration example: 00 - Draw up to 100 mA (unconfigured state) 01 - SDP (up to 500 mA) 10 - CDP/DCP (up to 1.5 A) 11 - Suspend (up to 2.5 mA) This truth table can be configured using a configuration utility VBUS detection. Connect the VBUS to this pin through a resistor network for VBUS detection when using the BCD feature (refer to page 19). CS0, CS1, CS2, CS3, CS4 CapSense button input (max up to 5) CSout0, CSout1, CSout2 Indicates which CapSense button is pressed CMOD External modulator capacitor, connect a 2.2-nF capacitor (±10%) to ground (Available on GPIO_0 only) Cshield (optional) Shield for waterproofing Note: These signal options can be configured on any of the available GPIO pins using the configuration utility provided by Cypress. Document Number: 001-82042 Rev. *I Page 15 of 34 CY7C65211 CY7C65211A USB Power Configurations The following section describes possible USB power configurations for the CY7C65211/CY7C65211A. Refer to the Pin Description on page 14 for signal details. USB Bus-Powered Configuration Figure 3 shows an example of the CY7C65211/CY7C65211A in a bus-powered design. The VBUS is connected directly to the CY7C65211 because it has an internal regulator. The USB bus-powered system must comply with the following requirements: 1. The system should not draw more than 100 mA prior to USB enumeration (Unconfigured state). 2. The system should not draw more than 2.5 mA during the USB Suspend mode. 3. A high-power bus-powered system (can draw more than 100 mA when operational) must use POWER# (configured over GPIO) to keep the current consumption below 100 mA prior to USB enumeration, and 2.5 mA during USB Suspend state. 4. The system should not draw more than 500 mA from the USB host. The configuration descriptor in the CY7C65211/CY7C65211A flash should be updated to indicate bus power and the maximum current required by the system using the configuration utility. Figure 3. Bus-Powered Configuration CY7C65211/CY7C65211A GPIO_0 19 GPIO_1 20 GPIO_2 / SCB_1 21 GPIO_3 / SCB_2 22 GPIO_4 / SCB_3 23 GPIO_5 / SCB_4 1 GPIO_6 / SCB_0 2 GPIO_7 / SCB_5 4 GPIO_8 5 GPIO_9 6 GPIO_10 7 GPIO_11 USB CONNECTOR 15 10 USBDP 11 USBDM VBUS D+ DGND 4.7 uF XRES VSSD VSSD 24 VBUS VCCD VSSA 8 SUSPEND 9 WAKEUP VDDD VSSD 18 0.1 uF 14 12 1 uF 17 16 13 3 Document Number: 001-82042 Rev. *I Page 16 of 34 CY7C65211 CY7C65211A Self-Powered Configuration Figure 4 shows an example of CY7C65211/CY7C65211A in a self-powered design. A self-powered system does not use the VBUS from the host to power the system, but it has its own power supply. A self-powered system has no restriction on current consumption because it does not draw any current from the VBUS. When the VBUS is present, CY7C65211/CY7C65211A enables an internal, 1.5-k pull-up resistor on USBDP. When the VBUS is absent (USB host is powered down), CY7C65211/CY7C65211A removes the 1.5-k pull-up resistor on USBDP. This ensures that no current flows from the USBDP to the USB host through a 1.5-k pull-up resistor, to comply with the USB 2.0 specification. When reset is asserted to CY7C65211/CY7C65211A, all the I/O pins are tristated. The configuration descriptor in the CY7C65211/CY7C65211A flash should be updated to indicate self-power using the configuration utility. Figure 4. Self-Powered Configuration 3.3 V CY7C65211/CY7C65211A GPIO_0 19 GPIO_1 20 GPIO_2 / SCB_1 21 GPIO_3 / SCB_2 22 GPIO_4 / SCB_3 VBUS USBDP USBDM GPIO_5 / SCB_4 24 USB CONNECTOR 15 10 VBUS D+ DGND 11 GPIO_6 / SCB_0 GPIO_7 / SCB_5 GPIO_8 GPIO_9 GPIO_10 GPIO_11 4.7 uF XRES 14 0.1 uF 4.7 KO 10 KO VSSD VCCD VSSD 8 SUSPEND 9 WAKEUP VSSA 23 1 2 4 5 6 7 VDDD VSSD 18 3.3 V 12 1 uF 17 16 13 3 Document Number: 001-82042 Rev. *I Page 17 of 34 CY7C65211 CY7C65211A USB Bus-Powered with Variable I/O Voltage Figure 5 shows CY7C65211/CY7C65211A in a bus-powered system with variable I/O voltage. A low dropout (LDO) regulator is used to supply 1.8 V or 3.3 V, using a jumper switch the input of which is 5 V from the VBUS. Another jumper switch is used to select 1.8/3.3 V or 5 V from the VBUS for the VDDD pin of CY7C65211. This allows I/O voltage and supply to external logic to be selected among 1.8 V, 3.3 V, or 5 V. The USB bus-powered system must comply with the following conditions: ■ The system should not draw more than 100 mA prior to USB enumeration (unconfigured state) ■ The system should not draw more than 2.5 mA during USB Suspend mode ■ A high-power bus-powered system (can draw more than 100 mA when operational) must use POWER# (configured over GPIO) to keep the current consumption below 100 mA prior to USB enumeration and 2.5 mA during the USB Suspend state Figure 5. USB Bus-Powered with 1.8-V, 3.3-V, or 5-V Variable I/O Voltage [4] 1.8 V or 3.3 V or 5 V Supply to External Logic Power Switch 1.8/3.3 V CY7C65211/CY7C65211A 18 GPIO_0 19 GPIO_1 20 GPIO_2 / SCB_1 21 GPIO_3 / SCB_2 22 GPIO_4 / SCB_3 VBUS USBDP USBDM GPIO_5 / SCB_4 1 2 3 24 Jumper to select 1.8 V/3.3 V or 5 V 15 10 11 VBUS USB D+ CONNECTOR DGND GPIO_6 / SCB_0 GPIO_7 / SCB_5 GPIO_8 GPIO_9 GPIO_10 GPIO_11 4.7 uF XRES VSSD VSSD VCCD VSSD 8 SUSPEND 9 WAKEUP VSSA 23 1 2 4 5 6 7 VDDD 0.1uF 14 VBUS 12 1 uF TC 1070 1.8/3.3 V Vout 17 16 13 3 Vin SHDn 1uF Vadj 1M 0.1 uF GND 123 3.3 V 562K 1.8 V 2M Jumper to select 1.8 V or 3.3 V Note 4. 1.71 V VDDD 1.89 V - Short VCCD pin with VDDD pin; VDDD > 2 V - connect a 1-µF decoupling capacitor to the VCCD pin. Document Number: 001-82042 Rev. *I Page 18 of 34 CY7C65211 CY7C65211A Application Examples The following section provides CY7C65211/CY7C65211A application examples. USB to RS232 Bridge CY7C65211/CY7C65211A can connect any embedded system, with a serial port, to a host PC through USB. CY7C65211/CY7C65211A enumerates as a COM port on the host PC. The RS232 protocol follows bipolar signaling – that is, the output signal toggles between negative and positive polarity. The valid RS232 signal is either in the –3-V to –15-V range or in the +3-V to +15-V range, and the range between –3 V to +3 V is invalid. In the RS232, Logic 1 is called “Mark” and it corresponds to a negative voltage range. Logic 0 is called “Space” and it corresponds to a positive voltage range. The RS232 level converter facilitates this polarity inversion and the voltage-level translation between the CY7C65211/CY7C65211A’s UART interface and RS232 signaling. In this application, as shown in Figure 6, SUSPEND is connected to the SHDN# pin of the RS232-level converter to indicate USB suspend or USB not enumerated. GPIO8 and GPIO9 are configured as RXLED# and TXLED# to drive two LEDs, indicating data transmit and receive. Figure 6. USB to RS232 Bridge 1.8/3.3 V CY7C65211/CY7C65211A VCC VCC VCC RTSout RTSin CTSin 1K CTSout RS232 Level TXDin TXDout Convertor 1K RXDin RXDout RTS# 21 CTS# 22 TXD 23 RXD 1 VDDD GPIO_3 / SCB_2 VBUS USBDP GPIO_4 / SCB_3 GPIO_5 / SCB_4 USBDM 24 1 2 3 Jumper to select 1.8 V/3.3 V or 5 V 15 10 11 VBUS D+ DGND GPIO_6 / SCB_0 USB CONNECTOR 0.1 uF SHDN# 8 SUSPEND XRES Vout 1uF 1M GPIO_8 GPIO_9 VSSD VSSD VCCD VSSA 5 12 1 uF VBUS VDDD Vin SHDn Vadj TXLED# 14 17 16 13 3 TC 1070 1.8/3.3 V 4 VSSD VBUS RXLED# 0.1 uF 4.7 uF 0.1 uF 4.7 uF 0.1 uF GND 123 3.3 V 562K 1.8 V 2M Jumper to select 1.8 V or 3.3 V Document Number: 001-82042 Rev. *I Page 19 of 34 CY7C65211 CY7C65211A USB to RS485 Bridge CY7C65211A can be configured as USB to UART interface. This UART interface operates at TTL level and it can be converted to RS485 interface using a GPIO and any half duplex RS485 transceiver IC (to convert TTL level to RS485 level) as shown in Figure 7. This GPIO (TXDEN) enables or disables the transmission of data through RS485 transceiver IC based on availability of character in UART buffer of CY7C65211A. This GPIO can be configured using Cypress USB-Serial Configuration utility. Figure 8 shows timing diagram of this GPIO. RS485 is a multi-drop network – i.e. many devices can communicate with each other over a single two wire cable connection. The RS485 cable requires to be terminated at each end of the cable. Figure 7. USB to RS485 Bridge 1.8/3.3 V CY7C65211A VCC 1K VCC VCC 21 RS485 Level TXDout Convertor 1K RXDin 22 TXDin RXDout TXD 23 RXD 1 VDDD GPIO_3 / SCB_2 VBUS USBDP GPIO_4 / SCB_3 GPIO_5 / SCB_4 USBDM 24 1 2 3 Jumper to select 1.8 V/3.3 V or 5 V 15 10 11 VBUS D+ DGND GPIO_6 / SCB_0 USB CONNECTOR 0.1 uF GND TXDEN 6 GPIO_10 XRES Vout 1uF GPIO_8 GPIO_9 VSSD 12 VSSD VCCD VSSA 5 VBUS 1 uF 4.7 uF Vin SHDn Vadj 1M TXLED# 14 VDDD 17 16 13 3 TC 1070 1.8/3.3 V 4 VSSD VBUS RXLED# 0.1 uF 4.7 uF 0.1 uF 0.1 uF GND 123 3.3 V 562K 1.8 V 2M Jumper to select 1.8 V or 3.3 V Figure 8. RS485 GPIO (TXDEN) Timing diagram Document Number: 001-82042 Rev. *I Page 20 of 34 CY7C65211 CY7C65211A Battery-Operated, Bus-Powered USB to MCU with Battery Charge Detection Figure 9 illustrates CY7C65211/CY7C65211A as a USB-to-microcontroller interface. The TXD and RXD lines are used for data transfer, and the RTS# and CTS# lines are used for handshaking. The SUSPEND pin indicates to the MCU if the device is in USB Suspend, and the WAKEUP pin is used to wake up CY7C65211/CY7C65211A, which in turn issues a remote wakeup to the USB host. This application illustrates a battery-operated system, which is bus-powered. CY7C65211/CY7C65211A implements the battery charger detection functionality based on the USB Battery Charging Specification, Rev. 1.2. Battery-operated bus power systems must comply with the following conditions: ■ The system can be powered from the battery (if not discharged) and can be operational if the VBUS is not connected or powered down. ■ The system should not draw more than 100 mA from the VBUS prior to USB enumeration and USB Suspend. The system should not draw more than 500 mA for SDP and 1.5 A for CDP/DCP To comply with the first requirement, the VBUS from the USB host is connected to the battery charger as well as to CY7C65211, as shown in Figure 9. When the VBUS is connected, CY7C65211 initiates battery charger detection and indicates the type of USB charger over BCD0 and BCD1. If the USB charger is SDP or CDP, CY7C65211 enables a 1.5-K pull-up resistor on the USBDP for Full-Speed enumeration. When the VBUS is disconnected, CY7C65211 indicates an absence of the USB charger over BCD0 and BCD1, and removes the 1.5-K pull-up resistor on USBDP. Removing this resistor ensures that no current flows from the supply to the USB host through the USBDP, to comply with the USB 2.0 specification. To comply with the second and third requirements, two signals (BCD0 and BCD1) are configured over GPIO to communicate the type of USB host charger and the amount of current it can draw from the battery charger. BCD0 and BCD1 signals can be configured using the configuration utility. ■ Figure 9. USB to MCU Interface with Battery Charge Detection [5] VCC CY7C65211/CY7C65211A VDDD CTS# RTS# 21 GPIO_3 / SCB_2 RTS# CTS# 22 GPIO_4 / SCB_3 I/O 1 GPIO_9 GPIO_10 GPIO_5 / SCB_4 8 SUSPEND 9 WAKEUP GND 10K 5 BCD0 EN1 6 BCD1 EN2 Battery Charger (MAX8856) SYS BAT IN 14 GPIO_6 / SCB_0 XRES VBUS USBDP USBDM VSSD I/O RXD 10K VSSD TXD 23 VSSD MCU TXD VSSA RXD 24 VCCD 15 10 11 OVP 12 VBUS USB D+ CONNECTOR DGND 0.1 uF 1 uF 17 16 13 3 VBUS 4.7 uF 0.1 uF Note 5. Add a 100-k pull-down resistor on the VBUS pin for quick discharge. Document Number: 001-82042 Rev. *I Page 21 of 34 CY7C65211 CY7C65211A In a battery charger system, a 9-V spike on the VBUS is possible. The CY7C65211 VBUS pin is intolerant to voltage above 6 V. In the absence of over-voltage protection (OVP) on the VBUS line, the VBUS should be connected to BUSDETECT (GPIO configured) using the resistive network and the output of the battery charger to the VBUS pin of CY7C65211, as shown in Figure 10. Figure 10. 9 V Tolerant A B Rs Rs = 10 K VBUS VBUS = VDDD SYS CY7C65211/ CY7C65211A GPIO Battery Charger BUSDETECT A BAT A CY7C65211/ CY7C65211A R1 R2/(R1+R2) = VDDD/VBUS VBUS > VDDD VDDD CY7C65211/ CY7C65211A BUSDETECT R1 = 10 k? R2 B VBUS VDDD B R1 BUSDETECT Rs VBUS VBUS R2 When the VBUS and VDDD are at the same voltage potential, the VBUS can be connected to the GPIO using a series resistor (Rs). This is shown in the following figure. If there is a charger failure and the VBUS becomes 9 V, then the 10-k resistor plays two roles. It reduces the amount of current flowing into the forward-biased diodes in the GPIO, and it reduces the voltage seen on the pad. Figure 11. GPIO VBUS Detection, VBUS = VDDD VDDD CY7C65211 BUSDETECT Rs When the VBUS > VDDD, a resistor voltage divider is required to reduce the voltage from the VBUS down to VDDD for the GPIO sensing the VBUS voltage. This is shown in the following figure. The resistors should be sized as follows: R1 >= 10 k R2 / (R1 + R2) = VDDD / VBUS The first condition limits the voltage and current for the charger failure situation, as described in the previous paragraph, while the second condition allows for normal-operation VBUS detection. Figure 12. GPIO VBUS detection, VBUS > VDDD VBUS VDDD CY7C65211 BUSDETECT R1 VBUS R2 Document Number: 001-82042 Rev. *I Page 22 of 34 CY7C65211 CY7C65211A CapSense In Figure 13, CY7C65211 is configured to support four CapSense buttons. Three GPIOs are configured to indicate which CapSense button is pressed by the finger (as shown in the table next to the schematic). If two CapSense buttons are implemented, then two GPIOs (CSout0 and CSout1) are configured to indicate which CapSense button is pressed. A 2.2-nF (10%) capacitor (Cmod) must be connected on the GPIO_0 pin for proper CapSense operation. Optionally, the GPIO_7 pin is configured as Cshield and connected to the shield of the CapSense button, as shown in Figure 13. Shield prevents false triggering of buttons due to water droplets, and guarantees CapSense operation (the sensors respond to finger touch). For further information on CapSense, refer to Getting Started with CapSense. Figure 13. CapSense Schematic VDDD CY7C65211/CY7C65211A VCC VDDD RxD TxD I/O I/O I/O 23 GPIO_5 / SCB_4 1 GPIO_6 / SCB_0 UART_TxD UART_RxD CSout0 GPIO_7 / SCB_5 GPIO_8 19 GPIO_1 20 GPIO_2 / SCB_1 CSout1 CSout_int 21 GPIO_9 GPIO_10 GPIO_3 / SCB_2 MCU CSout2 CSout0 0 0 0 0 0 1 0 1 1 0 GPIO_11 22 Capsense CSout1 button No button 0 pressed 1 CS0 0 CS1 1 CS2 0 CS3 GPIO_4 / SCB_3 VBUS USBDP USBDM 8 SUSPEND 9 WAKEUP I/O I/O XRES 24 2 Jumper to select Shield or No shield Cshield 4 5 6 7 560R 1 2 3 CS0 CS1 560R 560R 560R 15 10 CS2 CS3 VBUS D+ DGND 11 14 VBUS VDDD 1.8/3.3 V VSSD 12 1 uF 17 16 13 3 TC 1070 Vout Vin SHDn 1uF VSSD 2.2 nF GND VCCD VSSA 18 GPIO_0 VSSD Cmod Vadj 1M 0.1 uF GND VBUS 123 3.3 V 562K VDDD 1.8 V 2M 4.7 uF 0.1 uF 4.7 uF 0.1 uF Jumper to select 1.8 V or 3.3 V Document Number: 001-82042 Rev. *I Page 23 of 34 CY7C65211 CY7C65211A USB to I2C Bridge In Figure 14, CY7C65211 is configured as a USB to I2C Bridge. The CY7C65211 I2C can be configured as a master or a slave using the configuration utility. CY7C65211 supports I2C data rates up to 100 kbps in the standard mode (SM) and 400 kbps in the fast mode (FM). In the master mode, SCL is output from CY7C65211. In the slave mode, SCL is input to CY7C65211. The I2C slave address for CY7C65211 can be configured using the configuration utility. The SDA data line is bi-directional in the master/slave modes. The drive modes of the SCL and SDA port pins are always open drain. GPIO8 and GPIO9 are configured as RXLED# and TXLED# to drive two LEDs to indicate USB receive and transmit. Refer to the NXP I2C specification for further details on the protocol. Figure 14. USB to I2C Bridge 1.8/3.3 V VDDD 2.2K CY7C65211/CY7C65211A 2.2K VDDD VCC SCL 21 I2C Master/Slave SDA 22 GPIO_3 / SCB_2 VBUS USBDP GPIO_4 / SCB_3 GND USBDM 1 2 3 24 Jumper to select 1.8 V/3.3 V or 5 V 15 10 VBUS D+ DGND 11 USB CONNECTOR 0.1 uF XRES VSSD 12 1 uF 17 16 13 3 TC 1070 1.8/3.3 V Vout Vin SHDn 1uF VSSD VSSA VBUS VSSD VCCD 14 Vadj 1M 0.1 uF GND VBUS VDDD 123 3.3 V 562K 1.8 V 2M 4.7 uF 0.1 uF 4.7 uF 0.1 uF Jumper to select 1.8 V or 3.3 V Document Number: 001-82042 Rev. *I Page 24 of 34 CY7C65211 CY7C65211A USB to SPI Bridge In Figure 15, CY7C65211 is configured as a USB to SPI Bridge. The CY7C65211 SPI can be configured as a master or a slave using the configuration utility. CY7C65211 supports SPI master frequency up to 3 MHz and SPI slave frequency up to 1 MHz. It can support transaction sizes ranging from 4 bits to 16 bits, which can be configured using the configuration utility. In the master mode, the SCLK, MOSI, and SSEL lines act as outputs and MISO acts as an input. In the slave mode, the SCL SCLK, MOSI, and SSEL lines act as inputs and MISO acts as an output. GPIO8 and GPIO9 are configured as RXLED# and TXLED# to drive two LEDs to indicate USB receive and transmit. Figure 15. USB to SPI Bridge 1.8/3.3 V VDDD CY7C65211/CY7C65211A 10K VCC SSEL 20 MISO 21 SPI Master/Slave MOSI 22 SCLK 23 GND VDDD 1 2 3 24 GPIO_2 / SCB_1 GPIO_3 / SCB_2 GPIO_4 / SCB_3 VBUS USBDP GPIO_5 / SCB_4 USBDM Jumper to select 1.8 V/3.3 V or 5 V 15 10 11 VBUS D+ DGND USB CONNECTOR 0.1 uF XRES VSSD VSSD 12 1 uF 17 16 13 3 TC 1070 1.8/3.3 V Vout Vadj 1M VBUS VDDD Vin SHDn 1uF VSSD VBUS VSSA VCCD 14 0.1 uF 4.7 uF GND 0.1 uF 4.7 uF 0.1 uF 123 3.3 V 562K 1.8 V 2M Jumper to select 1.8 V or 3.3 V CY7C65211 supports three versions of the SPI protocol: ■ Motorola - This is the original SPI protocol. ■ Texas Instruments - A variation of the original SPI protocol in which the data frames are identified by a pulse on the SSEL line. National Semiconductors - A half-duplex variation of the original SPI protocol. Motorola The original SPI protocol is defined by Motorola. It is a full-duplex protocol: transmission and reception occur at the same time. A single (full-duplex) data transfer follows these steps: The master selects a slave by driving its SSEL line to '0'. Next, it drives the data on its MOSI line and it drives a clock on its SCLK line. The slave uses the edges of the transmitted clock to capture the data on the MOSI line. The slave drives data on its MISO line. The master captures the data on the MISO line. Repeat the process for all bits in the data transfer. ■ Document Number: 001-82042 Rev. *I Multiple data transfers may happen without the SSEL line changing from '0' to '1' and back from '1' to '0' in between the individual transfers. As a result, slaves must keep track of the progress of data transfers to separate individual transfers. When not transmitting data, the SSEL line is '1' and the SCLK is typically off. The Motorola SPI protocol has four modes that determine how data is driven and captured on the MOSI and MISO lines. These modes are determined by clock polarity (CPOL) and clock phase (CPHA). Clock polarity determines the value of the SCLK line when not transmitting data: ■ CPOL is '0': SCLK is '0' when not transmitting data. CPOL is '1': SCLK is '1' when not transmitting data. The clock phase determines when data is driven and captured. It is dependent on the value of CPOL: ■ Page 25 of 34 CY7C65211 CY7C65211A Table 16. SPI Protocol Modes Mode CPOL CPHA Description 0 0 0 Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK 1 0 1 Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK 2 1 0 Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK 3 1 1 Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK Figure 16. Driving and Capturing MOSI/MISO Data As A Function of CPOL and CPHA CPOL: ‘0’, CPHA: ‘0’ SCLK MOSI/MISO MSB LSB CPOL: ‘0’, CPHA: ‘1’ SCLK MOSI/MISO MSB LSB CPOL: ‘1’, CPHA: ‘0’ SCLK MOSI/MISO MSB LSB CPOL: ‘1’, CPHA: ‘0’ SCLK MOSI/MISO MSB LEGEND: CPOL: CPHA: SCLK: MOSI: MISO: LSB Clock Polarity Clock Phase SPI interface clock SPI Master Out / Slave In SPI Master In / Slave Out Figure 17. Single 8-bit Data Transfer and Two Successive 8-bit Data Transfers in Mode 0 (CPOL is ‘0’, CPHA is ‘0’) CPOL: ‘0’, CPHA: ‘0’, single data transfer SCLK SSEL MOSI MSB MISO MSB LSB LSB CPOL: ‘0’, CPHA: ‘0’, two successive data transfers SCLK SSEL MOSI MSB MISO MSB LEGEND: CPOL: CPHA: SCLK: SSEL: MOSI: MISO: Document Number: 001-82042 Rev. *I LSB MSB LSB LSB MSB LSB Clock Polarity Clock Phase SPI interface clock SPI slave select SPI Master Out / Slave In SPI Master In / Slave Out Page 26 of 34 CY7C65211 CY7C65211A Texas Instruments Texas Instruments' SPI protocol redefines the use of the SSEL signal. It uses the signal to indicate the start of a data transfer, rather than a low, active slave-select signal. The start of a transfer is indicated by a high, active pulse of a single-bit transfer period. This pulse may occur one cycle before the transmission of the first data bit, or it may coincide with the transmission of the first data bit. The transmitted clock SCLK is a free-running clock. The TI SPI protocol only supports mode 1 (CPOL is '0' and CPHA is '1'): Data is driven on a rising edge of SCLK and data is captured on a falling edge of SCLK. The following figure illustrates a single 8-bit data transfer and two successive 8-bit data transfers. The SSEL pulse precedes the first data bit. Note how the SSEL pulse of the second data transfer coincides with the last data bit of the first data transfer. Single data transfer SCLK SSEL MOSI MSB LSB MISO MSB LSB Two successive data transfers SCLK SSEL MOSI MSB LSB MSB LSB MISO MSB LSB MSB LSB LEGEND: SCLK: SSEL: MOSI: MISO: SPI interface clock SPI slave select pulse SPI Master Out / Slave In SPI Master In / Slave Out The following figure illustrates a single 8-bit data transfer and two successive 8-bit data transfers. The SSEL pulse coincides with the first data bit. Single data transfer SCLK SSEL MOSI MSB LSB MISO MSB LSB Two successive data transfers SCLK SSEL MOSI MSB LSB MSB LSB MISO MSB LSB MSB LSB LEGEND: SCLK: SSEL: MOSI: MISO: Document Number: 001-82042 Rev. *I SPI interface clock SPI slave select pulse SPI Master Out / Slave In SPI Master In / Slave Out Page 27 of 34 CY7C65211 CY7C65211A National Semiconductor National Semiconductor’s SPI protocol is a half-duplex protocol. Rather than transmission and reception occurring at the same time, they take turns (transmission happens before reception). A single "idle" bit transfer period separates transmission from reception. Note Successive data transfers are NOT separated by an "idle" bit transfer period. The transmission data transfer size and reception data transfer size may differ. National Semiconductor’s SPI protocol supports only mode 0: Data is driven on a falling edge of SCLK, and data is captured on a rising edge of SCLK. The following figure illustrates a single data transfer and two successive data transfers. In both cases, the transmission data transfer size is 8 bits and the reception transfer size is 4 bits. Single data transfer SCLK SSEL MOSI MSB LSB MISO MSB LSB “idle” ‘0’ cycle Two successive data transfers SCLK SSEL MOSI MSB LSB MISO MSB MSB “idle” ‘0’ cycle LEGEND: SCLK: SSEL: MOSI: MISO: LSB no “idle” cycle SPI interface clock SPI slave select SPI Master Out / Slave In SPI Master In / Slave Out Note The above figure defines MISO and MOSI as undefined when the lines are considered idle (not carrying valid information). It will drive the outgoing line values to '0' during idle time (to satisfy the requirements of specific master devices (NXP LPC17xx) and specific slave devices (MicroChip EEPROM). Document Number: 001-82042 Rev. *I Page 28 of 34 CY7C65211 CY7C65211A Ordering Information Table 17 lists the key package features and ordering codes of the CY7C65211. For more information, contact your local sales representative. Table 17. Key Features and Ordering Information Package Ordering Code 24-pin QFN (4.00 × 4.00 × 0.55 mm, 0.5 mm pitch) (Pb-free) CY7C65211-24LTXI Operating Range Industrial 24-pin QFN (4.00 × 4.00 × 0.55 mm, 0.5 mm pitch) (Pb-free) – Tape and CY7C65211-24LTXIT Reel Industrial 24-pin QFN (4.00 × 4.00 × 0.55 mm, 0.5 mm pitch) (Pb-free) Industrial CY7C65211A-24LTXI 24-pin QFN (4.00 × 4.00 × 0.55 mm, 0.5 mm pitch) (Pb-free) – Tape and CY7C65211A-24LTXIT Reel Industrial Ordering Code Definitions CY 7 C 65 XXXX - 24 XX X I X X = blank or T blank = Tube; T = Tape and Reel Temperature Range: I = Industrial Pb-free Package Type: LT = QFN Number of pins: 24 pins Part Number: XXXX = 211 or 211A Family Code: 65 = USB Hubs Technology Code: C = CMOS Marketing Code: 7 = Cypress products Company ID: CY = Cypress Document Number: 001-82042 Rev. *I Page 29 of 34 CY7C65211 CY7C65211A Package Information Support currently is planned for the 24-pin QFN package. Figure 18. 24-pin QFN (4 mm × 4 mm × 0.55 mm) LQ24A 2.65 × 2.65 EPAD (Sawn) Package Outline, 001-13937 001-13937 *F Table 18. Package Characteristics Description Min Typ Max Units TA Parameter Operating ambient temperature –40 25 85 °C THJ Package JA – 18.4 – °C/W Table 19. Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature 24-pin QFN 260 °C 30 seconds Table 20. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 24-pin QFN MSL 3 Document Number: 001-82042 Rev. *I Page 30 of 34 CY7C65211 CY7C65211A Acronyms Document Conventions Table 21. Acronyms Used in this Document Units of Measure Acronym Description Table 22. Units of Measure BCD battery charger detection CDC communication driver class C degree Celsius CDP charging downstream port DMIPS Dhrystone million instructions per second DCP dedicated charging port k kilo-ohm DLL dynamic link library KB kilobyte ESD electrostatic discharge kHz kilohertz GPIO general purpose input/output kV kilovolt HBM human-body model Mbps megabits per second I2C inter-integrated circuit MHz megahertz MCU microcontroller unit mm millimeter OSC oscillator V volt PHDC personal health care device class PID product identification SCB serial communication block SCL I2C serial clock SDA I2C serial data SDP standard downstream port SIE serial interface engine SPI serial peripheral interface VCOM virtual communication port USB Universal Serial Bus UART universal asynchronous receiver transmitter VID vendor identification Document Number: 001-82042 Rev. *I Symbol Unit of Measure Page 31 of 34 CY7C65211 CY7C65211A Document History Page Document Title: CY7C65211/CY7C65211A, USB-Serial Single-Channel (UART/I2C/SPI) Bridge with CapSense® and BCD Document Number: 001-82042 Revision ECN Orig. of Change Submission Date *F 4287738 SAMT 02/21/2014 Updated Ordering Information (Updated part numbers). *G 4455825 MVTA 01/19/2015 Added More Information. Updated to new template. *H 4807404 RRSH 06/23/2015 Updated Features. Updated Functional Overview: Updated Serial Communication: Updated UART Interface: Updated description. Updated I2C Interface: Updated description. Updated System Resources: Updated Power System: Updated description. Updated Internal 32-kHz Oscillator: Updated description. Updated Reset: Updated description. Updated Software: Updated Drivers for Windows Operating Systems: Updated description. Updated Windows-CE support: Updated description. Updated Electrical Specifications: Updated Operating Conditions: Updated details corresponding to VBUS supply voltage. Updated Device-Level Specifications: Updated Table 3: Changed maximum value of VBUS parameter from 5.25 V to 5.5 V. Updated Table 4: Removed F1 parameter and its details. Removed F2 parameter and its details. Updated Pin Description: Updated details in “Description” column of pin 15. Updated USB Power Configurations: Updated Self-Powered Configuration: Updated Figure 4. Updated Application Examples: Updated USB to SPI Bridge: Updated description. Updated Package Information: spec 001-13937 – Changed revision from *E to *F. Updated to new template. Completing Sunset Review. Document Number: 001-82042 Rev. *I Description of Change Page 32 of 34 CY7C65211 CY7C65211A Document History Page (continued) Document Title: CY7C65211/CY7C65211A, USB-Serial Single-Channel (UART/I2C/SPI) Bridge with CapSense® and BCD Document Number: 001-82042 Revision ECN Orig. of Change Submission Date *I 5063358 MVTA 12/24/2015 Document Number: 001-82042 Rev. *I Description of Change Updated Document Title to read as “CY7C65211/CY7C65211A, USB-Serial Single-Channel (UART/I2C/SPI) Bridge with CapSense® and BCD”. Included details of CY7C65211A part number in all instances across the document. Updated Features: Updated description. Added CY7C65211 and CY7C65211A Features Comparison. Updated More Information: Updated description. Updated Functional Overview: Updated Serial Communication: Updated UART Interface: Updated description. Updated UART Flow Control: Updated description. Updated SPI Interface: Updated description. Updated Internal Flash Configuration: Updated Table 2: Updated details in “Default Value” column corresponding to USB Product ID (PID) parameter. Updated Electrical Specifications: Updated Operating Conditions: Updated details corresponding to “VBUS supply voltage”. Updated Device-Level Specifications: Updated Table 3: Changed maximum value of VBUS parameter from 5.5 V to 5.25 V. Updated details in “Details/Conditions” column corresponding to IDD2 parameter. Updated Pin Description: Updated details in “Description” column corresponding to VBUS pin. Updated USB Power Configurations: Updated USB Bus-Powered Configuration: Updated Figure 3. Updated Self-Powered Configuration: Updated Figure 4. Updated USB Bus-Powered with Variable I/O Voltage: Updated Figure 5. Updated Application Examples: Updated USB to RS232 Bridge: Updated Figure 6. Added USB to RS485 Bridge. Updated Battery-Operated, Bus-Powered USB to MCU with Battery Charge Detection: Updated Figure 9. Updated Figure 10. Updated CapSense: Updated Figure 13. Updated USB to I2C Bridge: Updated Figure 14. Updated USB to SPI Bridge: Updated Figure 15. Updated Ordering Information: Updated part numbers. Updated Ordering Code Definitions. Page 33 of 34 CY7C65211 CY7C65211A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2012-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-82042 Rev. *I Revised December 24, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 34 of 34