Si844x/5x QSOP F O UR A N D F IVE - C HANNEL D IGITAL I SOLA TORS Features High-speed operation DC Up to 1000 VRMS isolation Precise timing (typical) to 150 Mbps No start-up initialization required Wide Operating Supply Voltage: 2.70–5.5 V Ultra low power (typical) 5 V Operation: <10 ns worst case ns pulse width distortion 0.5 ns channel-channel skew 2 ns propagation delay skew 6 ns minimum pulse width N ot fo R r N ec e w om m D e e s nd ig e ns d 1.5 1.6 mA per channel at 1 Mbps Transient Immunity 25 kV/µs 6 mA per channel at 100 Mbps Wide temperature range 2.70 V Operation: –40 to 125 °C at 150 Mbps < 1.4 mA per channel at 1 Mbps RoHS-compliant packages < 4 mA per channel at 100 Mbps QSOP-16 < < High electromagnetic immunity Applications Industrial automation systems Isolated switch mode supplies Isolated ADC, DAC Motor control Power inverters Communications systems Safety Regulatory Approvals UL 1577 recognized Up to 1000 VRMS for 1 minute CSA component notice 5A approval VDE certification conformity IEC 60747-5-2 (VDE0884 Part 2) Ordering Information: See page 25. Description Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages when compared to legacy isolation technologies. The operating parameters of these products remain stable across wide temperature ranges throughout their service life. For ease of design, only VDD bypass capacitors are required. Data rates up to 150 Mbps are supported, and all devices achieve worst-case propagation delays of less than 10 ns. These devices are available in a 16-pin QSOP package. Rev. 1.2 9/13 Copyright © 2013 by Silicon Laboratories Si844x/5x QSOP N ot fo R r N ec e w om m D e e s nd ig e ns d Si8 44x/5x Q S O P 2 Rev. 1.2 Si844x/5x QSOP TABLE O F C ONTENTS Section Page N ot fo R r N ec e w om m D e e s nd ig e ns d 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1. Power Supply Bypass Capacitors (Revision C and Revision D) . . . . . . . . . . . . . . . . 23 4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. Package Outline: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. Land Pattern: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8. Top Marking: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1. 16-Pin QSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Rev. 1.2 3 Si8 44x/5x Q S O P 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit TA 150 Mbps, 15 pF, 5 V –40 25 125 °C VDD1 2.70 — 5.5 V VDD2 2.70 — 5.5 V Ambient Operating Temperature* Supply Voltage N ot fo R r N ec e w om m D e e s nd ig e ns d *Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage. Table 2. Absolute Maximum Ratings1 Parameter Symbol Min Typ Max Unit TSTG –65 — 150 °C TA –40 — 125 °C VDD1, VDD2 –0.5 — 6.0 V Input Voltage VI –0.5 — VDD + 0.5 V Output Voltage VO –0.5 — VDD + 0.5 V Output Current Drive Channel IO — — 10 mA Lead Solder Temperature (10 s) — — 260 °C Maximum Isolation (Input to Output) (1 sec) QSOP-16 — — 1000 VRMS Storage Temperature 2 Ambient Temperature Under Bias Supply Voltage Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. VDE certifies storage temperature from –40 to 150 °C. 4 Rev. 1.2 Si844x/5x QSOP Table 3. Electrical Characteristics (VDD1 =5 V±10%, VDD2 =5 V±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 4.8 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V IL — — ±10 µA ZO — 85 — Input Leakage Current 1 N ot fo R r N ec e w om m D e e s nd ig e ns d Output Impedance Enable Input High Current IENH VENx = VIH — 2.0 — µA Enable Input Low Current IENL VENx = VIL — 2.0 — µA DC Supply Current (All inputs 0 V or at Supply) Si8455Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 1.6 2.9 7.0 3.1 2.4 4.4 10.5 4.7 Si8442Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 2.3 2.3 4.5 4.5 3.5 3.5 6.8 6.8 mA mA 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8455Bx VDD1 VDD2 — — 4.3 3.5 6.5 5.3 mA Si8442Bx VDD1 VDD2 — — 3.6 3.6 5.4 5.4 mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8455Bx VDD1 VDD2 — — 4.3 4.8 6.5 6.7 mA Si8442Bx VDD1 VDD2 — — 4.2 4.2 5.9 5.9 mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.2 5 Si8 44x/5x Q S O P Table 3. Electrical Characteristics (Continued) (VDD1 =5 V±10%, VDD2 =5 V±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8455Bx VDD1 VDD2 — — 4.6 24 6.9 30 mA Si8442Bx VDD1 VDD2 — — 11.8 11.8 14.8 14.8 mA N ot fo R r N ec e w om m D e e s nd ig e ns d Timing Characteristics Si845xAx, Si8442Bx Maximum Data Rate 0 — 1.0 Mbps Minimum Pulse Width — — 250 ns Propagation Delay tPHL, tPLH See Figure 2 — — 35 ns PWD See Figure 2 — — 25 ns tPSK(P-P) — — 40 ns tPSK — — 35 ns Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 6.0 ns Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew Si845xBx, Si8442Bx Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL, tPLH See Figure 2 3.0 6.0 9.5 ns PWD See Figure 2 — 1.5 2.5 ns tPSK(P-P) — 2.0 3.0 ns tPSK — 0.5 1.8 ns All Models Output Rise Time tr CL = 15 pF See Figure 2 — 3.8 5.0 ns Output Fall Time tf CL = 15 pF See Figure 2 — 2.8 3.7 ns CMTI VI = VDD or 0 V — 25 — kV/µs ten1 See Figure 1 — 5.0 8.0 ns ten2 See Figure 1 — 7.0 9.2 ns — 15 40 µs Common Mode Transient Immunity Enable to Data Valid Enable to Data Tri-State 3 Start-up Time tSU Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 6 Rev. 1.2 Si844x/5x QSOP ENABLE OUTPUTS ten1 N ot fo R r N ec e w om m D e e s nd ig e ns d ten2 Figure 1. ENABLE Timing Diagram 1.4 V Typical Input tPLH 1.4 V Typical Output tPHL 90% 90% 10% 10% tr tf Figure 2. Propagation Delay Timing Rev. 1.2 7 Si8 44x/5x Q S O P Table 4. Electrical Characteristics (VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 3.1 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V IL — — ±10 µA ZO — 85 — Input Leakage Current N ot fo R r N ec e w om m D e e s nd ig e ns d Output Impedance 1 Enable Input High Current IENH VENx = VIH — 2.0 — µA Enable Input Low Current IENL VENx = VIL — 2.0 — µA DC Supply Current (All inputs 0 V or at supply) Si8455Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 dc All inputs 0 dc All inputs 1 dc All inputs 1 dc — — — — 1.6 2.9 7.0 3.1 2.4 4.4 10.5 4.7 Si8442Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 dc All inputs 0 dc All inputs 1 dc All inputs 1 dc — — — — 2.3 2.3 4.5 4.5 3.5 3.5 6.8 6.8 mA mA 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8455Bx VDD1 VDD2 — — 4.3 3.5 6.5 5.3 mA Si8442Bx VDD1 VDD2 — — 3.6 3.6 5.4 5.4 mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8455Bx VDD1 VDD2 — — 4.3 4.8 6.5 6.7 mA Si8442Bx VDD1 VDD2 — — 4.2 4.2 5.9 5.9 mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. 8 Rev. 1.2 Si844x/5x QSOP Table 4. Electrical Characteristics (Continued) (VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8455Bx VDD1 VDD2 — — 4.4 16.8 6.6 21 mA Si8442Bx VDD1 VDD2 — — 8.6 8.6 10.8 10.8 mA N ot fo R r N ec e w om m D e e s nd ig e ns d Timing Characteristics Si845xBx, Si8442Bx Maximum Data Rate 0 — 1.0 Mbps Minimum Pulse Width — — 250 ns Propagation Delay tPHL,tPLH See Figure 2 — — 35 ns PWD See Figure 2 — — 25 ns tPSK(P-P) — — 40 ns tPSK — — 35 ns Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 6.0 ns Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew Si845xBx, Si8442Bx Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL, tPLH See Figure 2 3.0 6.0 9.5 ns PWD See Figure 2 — 1.5 2.5 ns tPSK(P-P) — 2.0 3.0 ns tPSK — 0.5 1.8 ns All Models Output Rise Time tr CL = 15 pF See Figure 2 — 4.3 6.1 ns Output Fall Time tf CL = 15 pF See Figure 2 — 3.0 4.3 ns CMTI VI = VDD or 0 V — 25 — kV/µs ten1 See Figure 1 — 5.0 8.0 ns ten2 See Figure 1 — 7.0 9.2 ns — 15 40 µs Common Mode Transient Immunity Enable to Data Valid Enable to Data Tri-State Start-up Time 3 tSU Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.2 9 Si8 44x/5x Q S O P Table 5. Electrical Characteristics1 (VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 2.3 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V Input Leakage Current IL — — ±10 µA Impedance2 ZO — 85 — Enable Input High Current IENH VENx = VIH — 2.0 — µA Enable Input Low Current IENL VENx = VIL — 2.0 — µA N ot fo R r N ec e w om m D e e s nd ig e ns d Output DC Supply Current (All inputs 0 V or at supply) Si8455Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 1.6 2.9 7.0 3.1 2.4 4.4 10.5 4.7 Si8442Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 2.3 2.3 4.5 4.5 3.5 3.5 6.8 6.8 mA mA 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8455Bx VDD1 VDD2 — — 4.3 3.5 6.5 5.3 mA Si8442Bx VDD1 VDD2 — — 3.6 3.6 5.4 5.4 mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8455Bx VDD1 VDD2 — — 4.3 4.8 6.5 6.7 mA Si8442Bx VDD1 VDD2 — — 4.2 4.2 5.9 5.9 mA Notes: 1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is constrained to TA = 0 to 85 °C. 2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. Start-up time is the time period from the application of power to valid data at the output. 10 Rev. 1.2 Si844x/5x QSOP Table 5. Electrical Characteristics1 (Continued) (VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8455Bx VDD1 VDD2 — — 4.3 13.3 6.5 16.6 mA Si8442Bx VDD1 VDD2 — — 7.2 7.2 9.0 9.0 mA N ot fo R r N ec e w om m D e e s nd ig e ns d Timing Characteristics Si845xBx, Si8442Bx Maximum Data Rate 0 — 1.0 Mbps Minimum Pulse Width — — 250 ns Propagation Delay tPHL,tPLH See Figure 2 — — 35 ns PWD See Figure 2 — — 25 ns tPSK(P-P) — — 40 ns tPSK — — 35 ns Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 6.0 ns Pulse Width Distortion |tPLH – tPHL| Propagation Delay Skew3 Channel-Channel Skew Si845xBx, Si8442Bx Propagation Delay Pulse Width Distortion |tPLH – tPHL| Propagation Delay Skew3 Channel-Channel Skew tPHL, tPLH See Figure 2 3.0 6.0 9.5 ns PWD See Figure 2 — 1.5 2.5 ns tPSK(P-P) — 2.0 3.0 ns tPSK — 0.5 1.8 ns Notes: 1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is constrained to TA = 0 to 85 °C. 2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. Start-up time is the time period from the application of power to valid data at the output. Rev. 1.2 11 Si8 44x/5x Q S O P Table 5. Electrical Characteristics1 (Continued) (VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C) Parameter Symbol Test Condition Min Typ Max Unit Output Rise Time tr CL = 15 pF See Figure 2 — 4.8 6.5 ns Output Fall Time tf CL = 15 pF See Figure 2 — 3.2 4.6 ns CMTI VI = VDD or 0 V — 25 — kV/µs ten1 See Figure 1 — 5.0 8.0 ns ten2 See Figure 1 — 7.0 9.2 ns — 15 40 µs All Models N ot fo R r N ec e w om m D e e s nd ig e ns d Common Mode Transient Immunity Enable to Data Valid Enable to Data Tri-State Start-up Time 4 tSU Notes: 1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is constrained to TA = 0 to 85 °C. 2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. Start-up time is the time period from the application of power to valid data at the output. Table 6. Regulatory Information* CSA The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. VDE The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. 60747-5-2: Up to 560 Vpeak for basic insulation working voltage. UL The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455. *Note: Regulatory Certifications apply to 1.0 kVRMS rated devices which are production tested to 1.2 kVRMS for 1 sec. For more information, see "5. Ordering Guide" on page 25. 12 Rev. 1.2 Si844x/5x QSOP Table 7. Insulation and Safety-Related Specifications Parameter Symbol Test Condition Value Unit QSOP-16 Nominal Air Gap (Clearance) L(IO1) 3.6 mm Nominal External Tracking (Creepage) L(IO2) 3.6 mm 0.008 mm 600 VRMS Minimum Internal Gap (Internal Clearance) PTI IEC 60112 Erosion Depth ED 0.031 mm Resistance (Input-Output)1 RIO 1012 2.0 pF 4.0 pF N ot fo R r N ec e w om m D e e s nd ig e ns d Tracking Resistance (Proof Tracking Index) Capacitance (Input-Output)1 CIO Input Capacitance2 f = 1 MHz CI Notes: 1. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–8 are shorted together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are then measured between these two terminals. 2. Measured from input pin to ground. Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings Parameter Basic Isolation Group Installation Classification Test Condition Material Group Specification I Rated Mains Voltages < 150 VRMS I-IV Rated Mains Voltages < 300 VRMS I-III Rated Mains Voltages < 400 VRMS I-II Rated Mains Voltages < 600 VRMS I-II Rev. 1.2 13 Si8 44x/5x Q S O P Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB* Parameter Symbol Maximum Working Insulation Voltage Characteristic Unit 560 V peak VIORM Input to Output Test Voltage Transient Overvoltage Test Condition V peak VPR Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm =1 sec, Partial Discharge < 5 pC) 1050 VIOTM t = 60 sec 4000 2 N ot fo R r N ec e w om m D e e s nd ig e ns d Pollution Degree (DIN VDE 0110, Table 1) Insulation Resistance at TS, VIO = 500 V V peak >109 RS *Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of 40/125/21. Table 10. Safety Limiting Values1 Max Parameter Symbol Case Temperature TS Safety input, output, or supply current IS Device Power Dissipation2 PD Test Condition JA = 105 °C/W (QSOP-16), VI =5.5 V, TJ =150 °C, TA = 25 °C Min Typ Unit Si844x Si845x QSOP-16 QSOP-16 — — 150 150 °C — — 210 215 mA — — 275 415 mW Notes: 1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 3 and 4. 2. The Si84xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square wave. 14 Rev. 1.2 Si844x/5x QSOP Table 11. Thermal Characteristics Parameter Symbol Si84xx QSOP-16 Unit JA 105 °C/W IC Junction-to-Air Thermal Resistance 430 400 VDD1, VDD2 = 2.70 V 360 VDD1, VDD2 = 3.6 V 300 N ot fo R r N ec e w om m D e e s nd ig e ns d Safety-Limiting Current (mA) 500 210 200 VDD1, VDD2 = 5.5 V 100 0 0 50 100 Temperature (ºC) 150 200 Figure 3. (Si844x, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Safety-Limiting Current (mA) 500 430 400 VDD1, VDD2 = 2.70 V 360 VDD1, VDD2 = 3.6 V 300 215 200 VDD1, VDD2 = 5.5 V 100 0 0 50 100 Temperature (ºC) 150 200 Figure 4. (Si845x, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Rev. 1.2 15 Si8 44x/5x Q S O P 2. Functional Description 2.1. Theory of Operation The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si84xx channel is shown in Figure 5. Transmitter Receiver A N ot fo R r N ec e w om m D e e s nd ig e ns d RF OSCILLATOR MODULATOR SemiconductorBased Isolation Barrier DEMODULATOR B Figure 5. Simplified Channel Diagram A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See Figure 6 for more details. Input Signal Modulation Signal Output Signal Figure 6. Modulation Scheme 16 Rev. 1.2 Si844x/5x QSOP 2.2. Eye Diagram N ot fo R r N ec e w om m D e e s nd ig e ns d Figure 7 illustrates an eye-diagram taken on an Si8455. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8455 were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited. Figure 7. Eye Diagram Rev. 1.2 17 Si8 44x/5x Q S O P 2.3. Device Operation Device behavior during start-up, normal operation, and shutdown is shown in Table 12. Table 13 provides an overview of the output states when the Enable pins are active. Table 12. Si84xx Logic Operation Table Input1,2 EN Input1,2,3 VDDI State1,4,5 VDDO State1,4,5 VO Output1,2 H H or NC P P H L H or NC P P L X6 L P P Hi-Z7 H or NC UP P L L UP P Hi-Z7 P UP X6 X6 X 6 Comments Enabled, normal operation. Disabled. N ot fo R r N ec e w om m D e e s nd ig e ns d VI X 6 Upon transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 µs. Disabled. Undetermined Upon transition of VDDO from unpowered to powered, VO returns to the same state as VI within 1 µs, if EN is in either the H or NC state. Upon transition of VDDO from unpowered to powered, VO returns to Hi-Z within 1 µs if EN is L. Notes: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the enable control input located on the same output side. 2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance. 3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si84xx is operating in noisy environments. 4. "Powered" state (P) is defined as 2.70 V < VDD < 5.5 V. 5. "Unpowered" state (UP) is defined as VDD = 0 V. 6. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current. 7. When using the enable pin (EN) function, the output pin state goes into a high-impedance state when the EN pin is disabled (EN = 0). 18 Rev. 1.2 Si844x/5x QSOP Table 13. Enable Input Truth Table1 P/N Operation EN11,2 EN21,2 Si8442 X Outputs A3 and A4 are enabled and follow input state. L X Outputs A3 and A4 are disabled and Logic Low or in high impedance state.3 X H Outputs B1 and B2 are enabled and follow input state. X L Outputs B1 and B2 are disabled and Logic Low or in high impedance state.3 — — Outputs B1, B2, B3, B4, B5 are enabled and follow input state. N ot fo R r N ec e w om m D e e s nd ig e ns d Si8455 H Notes: 1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are internally pulled-up to local VDD by a 3 µA current source allowing them to be connected to an external logic level (high or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si845x is operating in a noisy environment. 2. X = not applicable; H = Logic High; L = Logic Low. 3. When using the enable pin (EN) function, the output pin state goes into a high-impedance state when the EN pin is disabled (EN = 0). Rev. 1.2 19 Si8 44x/5x Q S O P 2.4. Layout Recommendations To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). Refer to the end-system specification (61010-1, 60950-1, etc.) requirements before starting any design that uses a digital isolator. The following sections detail the recommended bypass and decoupling components necessary to ensure robust overall performance and reliability for systems using the Si84xx digital isolators. 2.4.1. Supply Bypass N ot fo R r N ec e w om m D e e s nd ig e ns d Digital integrated circuit components typically require 0.1 µF (100 nF) bypass capacitors when used in electrically quiet environments. However, digital isolators are commonly used in hazardous environments with excessively noisy power supplies. To counteract these harsh conditions, it is recommended that an additional 1 µF bypass capacitor be added between VDD and GND on both sides of the package. The capacitors should be placed as close as possible to the package to minimize stray inductance. If the system is excessively noisy, it is recommended that the designer add 50 to 100 resistors in series with the VDD supply voltage source and 50 to 300 resistors in series with the digital inputs/outputs (see Figure 8). For more details, see "3. Errata and Design Migration Guidelines" on page 23. All components upstream or downstream of the isolator should be properly decoupled as well. If these components are not properly decoupled, their supply noise can couple to the isolator inputs and outputs, potentially causing damage if spikes exceed the maximum ratings of the isolator (6 V). In this case, the 50 to 300 resistors protect the isolator's inputs/outputs (note that permanent device damage may occur if the absolute maximum ratings are exceeded). Functional operation should be restricted to the conditions specified in Table 1, “Recommended Operating Conditions,” on page 4. 2.4.2. Pin Connections No connect pins are not internally connected. They can be left floating, tied to VDD, or tied to GND. 2.4.3. Output Pin Termination The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. The series termination resistor values should be scaled appropriately while keeping in mind the recommendations described in “2.4.1. Supply Bypass” above. V Source 1 R1 (50 – 100 ) VDD1 C1 VDD2 50 – 300 0.1 F 0.1 F B1 C2 1 F R2 (50 – 100 ) C4 50 – 300 A1 V Source 2 C3 Input/Output Input/Output 1 F Bx Ax 50 – 300 50 – 300 GND1 GND2 Figure 8. Recommended Bypass Components for the Si84xx Digital Isolator Family 20 Rev. 1.2 Si844x/5x QSOP 2.5. Typical Performance Characteristics The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to Tables 3, 4, and 5 for actual specification limits. 35 35 30 5V 25 20 Current (mA) Current (mA) 30 3.3V 15 2.70V 10 5V 25 3.3V 20 15 2.70V 10 5 5 0 N ot fo R r N ec e w om m D e e s nd ig e ns d 0 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps) Data Rate (Mbps) Figure 9. Si8455 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation 30 10 25 20 15 3.3V 10 2.70V 5 Falling Edge 9 5V Delay (ns) Current (mA) Figure 11. Si8455 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load) 8 7 6 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Data Rate (Mbps) Figure 10. Si8442 Typical VDD1 or VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load) Rev. 1.2 Rising Edge 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Figure 12. Propagation Delay vs. Temperature 21 Si8 44x/5x Q S O P High Voltage Lifetime for 1kVrms Rated Isolation Products 1000 Data taken at worst case conditions of 150o C 10 1 N ot fo R r N ec e w om m D e e s nd ig e ns d Expected Lifetime, years (at 10 ppm) 100 0.1 0.01 0.001 0.0001 0.00001 0 400 800 1200 1600 2000 2400 2800 3200 Working Voltage, Vrms Figure 13. Si84xx Time-Dependent Dielectric Breakdown 22 Rev. 1.2 3600 4000 Si844x/5x QSOP 3. Errata and Design Migration Guidelines No errata exist for Revision D. However, the following recommendations apply to Revision D devices. See "5. Ordering Guide" on page 25 for more details. 3.1. Power Supply Bypass Capacitors (Revision C and Revision D) When using the Si844x isolators with power supplies > 4.5 V, sufficient VDD bypass capacitors must be present on both the VDD1 and VDD2 pins to ensure the VDD rise time is less than 0.5 V/µs (which is > 9 µs for a > 4.5 V supply). Although rise time is power supply dependent, > 1 µF capacitors are required on both power supply pins (VDD1, VDD2) of the isolator device. 3.1.1. Resolution N ot fo R r N ec e w om m D e e s nd ig e ns d For recommendations on resolving this issue, see "2.4.1. Supply Bypass" on page 20. Additionally, refer to "5. Ordering Guide" on page 25 for current ordering information. Rev. 1.2 23 Si8 44x/5x Q S O P 4. Pin Descriptions VDD1 GND1 RF XMITR A2 RF XMITR A3 RF RCVR A4 RF RCVR GND2 VDD2 GND1 RF RCVR B1 A1 RF XMITR RF RCVR B2 A2 RF XMITR RF RF XMITR RCVR B3 A3 RF XMITR RF XMITR B4 A4 RF XMITR I s o l a t i o n GND2 RF RCVR B1 RF RCVR B2 RF RCVR B3 RF RCVR B4 N ot fo R r N ec e w om m D e e s nd ig e ns d A1 I s o l a t i o n EN1 GND1 Si8442 EN2 A5 GND2 RF XMITR GND1 RF RCVR Si8455 B5 GND2 Name SOIC-16 Pin# Type Description (Si8442) Description (Si8455) VDD1 1 Supply Side 1 power supply Side 1 power supply GND1 2 Ground Side 1 ground Side 1 ground A1 3 Digital Input Side 1 digital input Side 1 digital input 4 Digital Input Side 1 digital input Side 1 digital input 5 Digital I/O Side 1 digital output Side 1 digital input 6 Digital I/O Side 1 digital output Side 1 digital input A5/EN1 7 Digital Input Side 1 active high enable Side 1 digital input GND1 8 Ground Side 1 ground Side 1 ground GND2 9 Ground Side 2 ground Side 2 ground B5/EN2 10 Digital Input or Enable Side 2 active high enable Side 2 digital output B4 11 Digital I/O Side 2 digital input Side 2 digital output 12 Digital I/O Side 2 digital input Side 2 digital output B2 13 Digital Output Side 2 digital output Side 2 digital output B1 14 Digital Output Side 2 digital output Side 2 digital output GND2 15 Ground Side 2 ground Side 2 ground VDD2 16 Supply Side 2 power supply Side 2 power supply A2 A3 A4 B3 24 VDD1 VDD2 Rev. 1.2 Si844x/5x QSOP 5. Ordering Guide These devices are not recommended for new designs. Please see the Si864x or Si865x datasheet for replacement options. Table 14. Ordering Guide for Valid OPNs* Alternative Part Number of Number of Number Inputs VDD1 Inputs VDD2 (APN) Side Side Maximum Data Rate (Mbps) Isolation Rating Si8442BA-D-IU Si8642BA-C-IU 2 2 150 1 kVrms Si8455BA-B-IU Si8655BA-C-IU 5 0 150 1 kVrms Package Type QSOP-16 N ot fo R r N ec e w om m D e e s nd ig e ns d Ordering Part Number (OPN) *Note: All packages are RoHS-compliant. Moisture sensitivity level is MSL2A with peak reflow temperature of 260 °C according to the JEDEC industry standard classifications and peak solder temperature. Rev. 1.2 25 Si8 44x/5x Q S O P 6. Package Outline: 16-Pin QSOP Figure 14 illustrates the package details for the Si84xx in a 16-pin QSOP package. Table 15 lists the values for the dimensions shown in the illustration. N ot fo R r N ec e w om m D e e s nd ig e ns d Figure 14. 16-pin QSOP Package Table 15. Package Diagram Dimensions Dimension Min Max A — 1.75 A1 0.10 0.25 A2 1.25 — b 0.20 0.30 c 0.17 0.25 D 4.89 BSC E 6.00 BSC E1 3.90 BSC e 0.635 BSC L 0.40 L2 h 26 1.27 0.25 BSC 0.25 Rev. 1.2 0.50 Si844x/5x QSOP Table 15. Package Diagram Dimensions (Continued) Dimension Min Max θ 0° 8° aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 N ot fo R r N ec e w om m D e e s nd ig e ns d Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AB. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.2 27 Si8 44x/5x Q S O P 7. Land Pattern: 16-Pin QSOP Figure 15 illustrates the recommended land pattern details for the Si84xx in a 16-pin QSOP. Table 16 lists the values for the dimensions shown in the illustration. N ot fo R r N ec e w om m D e e s nd ig e ns d Figure 15. 16-Pin QSOP PCB Land Pattern Table 16. 16-Pin QSOP Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 5.40 E Pad Row Pitch 0.635 X1 Pad Width 0.40 Y1 Pad Length 1.55 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOP63P602X173-16N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. 28 Rev. 1.2 Si844x/5x QSOP 8. Top Marking: 16-Pin QSOP 8.1. 16-Pin QSOP Top Marking e3 Si84XYSV YYWWTTTTTT N ot fo R r N ec e w om m D e e s nd ig e ns d 8.2. Top Marking Explanation Line 1 Marking: Line 2 Marking: Base Part Number Ordering Options (See Ordering Guide for more information). Si84 = Isolator product series XY = Channel Configuration X = # of data channels (5, 4) Y = # of reverse channels (2, 0)* S = Speed Grade A = 1 Mbps; B = 150 Mbps V = Insulation rating A = 1 kV Circle = 1.2 mm Diameter “e3” Pb-Free Symbol YY = Year WW = Work Week Assigned by the assembly subcontractor. Corresponds to the year and work week of the mold date. TTTTTT = Mfg code Manufacturing code from assembly purchase order form. Circle = 1.2 mm diameter “e3” Pb-Free Symbol. *Note: Si8455 has 0 reverse channels. Rev. 1.2 29 Si8 44x/5x Q S O P DOCUMENT CHANGE LIST Revision 0.1 to Revision 1.0 Changed document name from Si84x/5x QSOP to Si844x/5x QSOP. Updated " Features" on page 1. Moved Tables 1 and 2 to page 4. Updated Tables 6, 7, 8, and 9. Updated Table 12 footnotes. Added Figure 13, “Si84xx Time-Dependent Dielectric Breakdown,” on page 22. N ot fo R r N ec e w om m D e e s nd ig e ns d Revision 1.0 to Revision 1.1 Deleted all references to 2.5 kVRMS Updated Table 6, “Regulatory Information*,” on page 12. Updated Figure 13, “Si84xx Time-Dependent Dielectric Breakdown,” on page 22. Updated "2.4.1. Supply Bypass" on page 20. Added Figure 8, “Recommended Bypass Components for the Si84xx Digital Isolator Family,” on page 20. Updated "3.1. Power Supply Bypass Capacitors (Revision C and Revision D)" on page 23. Revision 1.1 to Revision 1.2 30 Updated "5. Ordering Guide" on page 25 to include new title note and “ Alternative Part Number (APN)” column. Rev. 1.2 N ot fo R r N ec e w om m D e e s nd ig e ns d Si844x/5x QSOP NOTES: Rev. 1.2 31 Smart. Connected. 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