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Digital Sound Processors for FPD TVs
32bit Audio DSP with Built-in 4ch
DAC and ASRC
No.12083EAT02
BU9408KS2
●General Description
This LSI is the digital sound processor which made
the use digital signal processing for FPD TVs.
DSP of ROHM original is used for the TV sound processor unit, and it excels in cost performance. A selection input of two
lines is possible from four digital inputs. An asynchronous sampling rate converter(ASRC) is built in one line. Three digital
outputs are built in.
Two audio DA converters are built in.
●Features
■Digital Signal Processor unit
Word length:
32bit (Data RAM)
The fastest machine cycle: 40.7ns (512fs, fs = 48kHz)
Multiplier:
32 x 24 → 56bit
Adder:
32 + 32 → 32bit
Data RAM:
256 x 32bit
Coefficient RAM:
128 x 24bit
Sampling frequency:
fs = 48kHz
Master clock :
512fs（24.576MHz,fs=48kHz）
■Digital signal input (Stereo4lines):
16/20/24bit (I2S, Left-Justified, Right-Justified)
Digital signal output (Stereo 3 lines):
16/20/24bit (I2S, Left-Justified, Right-Justified, S/PDIF)
■.Asynchronous sampling rate converter
（one line at stereo）：32kHz/44.1kHz/48kHz/88.2kHz/96kHz/176.4kHz/192kHz → 48kHz
■Audio DAC：One stereo output
24bit 8 x Over-sampling digital filter + 1 bit delta sigma DAC
S/N：
96dB
THD+N： 0.005%（Sine-wave 1kHz,0dB）
■Audio 16bit DAC：One stereo output
24bit 8 x Over-sampling digital filter + Audio 16bit DAC
S/N：
90dB
THD+N： 0.03%（Sine-wave 1kHz,0dB）
■The sound signal processing function for FPD TVs
Pre-Scaler, DC cut HPF, Channel Mixer, P2Volume(Perfect Pure Volume), BASS, MIDDLE,
TREBLE, Simulated-Stereo, Surround, P2Bass, P2Treble, 7Band Parametric EQ,
Master Volume, L/R balance, Post-Scaler, Output signal clipper
(P2Volume, P2Bass, and P2Treble are the sound effect functions of ROHM original.)
●Applications
Flat Panel TVs (LCD, Plasma)
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© 2012 ROHM Co., Ltd. All rights reserved.
1/53
2012.03 - Rev.A
Technical Note
BU9408KS2
●Absolute Maximum Ratings
Items
Power supply voltage
Symbol
Ratings
Unit
VDD
4.5
V
Power dissipation
Pd
850(*1)
mW
Operating temp. range
Topr
-25～+85
Storage temp. range
Tstg
-55～+125
°C
°C
Symbol
Ratings
Unit
VDD
3.0～3.6
V
*1Use of this processor at Ta = 25°C and over is subject to reduction of 8.5mW per 1°C.
Operation is not guaranteed.
●Recommended Operating Rating(s)
Items
Power supply voltage
*1 This product is not designed for protection against radioactive rays.
●Electrical Characteristics(Digital system)
VDD=3.3V (Unless otherwise specified Ta = 25°C)
Items
Input voltage
VIH
VIL
VIH
VIL
II
IIL
MIN
2.3
2.5
-1
-150
Limit
TYP
-100
MAX
1.0
0.8
+1
-50
IIH
VOH
VOL
35
2.75
-
70
-
VOL
-
-
Symbol
H-level voltage
L-level voltage
H-level voltage
L-level voltage
Hysteresis
input
voltage
Input current
Input L current to Pull-up resistor
Input H current to Pull-down resistor
H-level voltage
Output voltage
L-level voltage
SDA Output voltage L-level voltage
Unit
Adaptive
terminal
Conditions
V
V
V
V
μA
μA
VIN=0~3.3V
VIN=0V
*1
*1
*2,3,4
*2,3,4
*1,2
*3
105
0.55
μA
V
V
VIN=3.3V
IO=-0.6mA
IO=0.6mA
*4
*5
*5
0.4
V
IO=3mA
*6
Adaptive terminal
*1
CMOS input terminal
XI(33pin)
*2
CMOS hysteresis input terminal
SCANTEST(5pin), SCL(7pin), SDA(8pin)
*3
CMOS hysteresis input terminal with a built-in pull-up resistor
LRCKI1(41pin), BCKI1(42pin), DATAI1(43pin), LRCKI2(44pin), BCKI2(45pin), DATAI2(46pin),
LRCKI3(47pin), BCKI3(48pin), DATAI3(49pin), LRCKI4(50pin), BCKI4(51pin), DATAI4(52pin)
*4
CMOS input terminal with a built-in pull down resistor
I2CADR(6pin), RESETB(10pin), MUTE1B(12pin), MUTE2B(13pin), MUTE3B(14pin)
*5
CMOS output terminal
ERR1_LRC(24pin), ERR2_BCK(25pin), DATASO(26pin), DATAMO(27pin), BCKO(28pin), LRCKO(29pin),
AMCLKO(30pin), SPDIFO(31pin), XO(34pin),
*6
Open drain output terminal
SDA(8pin)
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© 2012 ROHM Co., Ltd. All rights reserved.
2/53
2012.03 - Rev.A
Technical Note
BU9408KS2
●Electrical Characteristics (Analog system)
VDD=3.3V (Unless otherwise specified Ta = 25°C, RL=10kΩ, standard VC)
Limit
Item
Symbol
Unit
Applicable pins, conditions
MIN
TYP
MAX
IQ
-
40
70
mA
VREG
1.3
1.5
1.7
V
fPA8
-
24.576
-
MHz
Max-output amplitude
VOMAX
0.63
0.75
0.86
Vrms
THD+N
THDDA
-
0.005
0.03
%
0dB,1kHz
S/N
S/NDA
-
96
-
dB
0dB,1kHz,A-weighted
Max-output amplitude
VOMAX
0.65
0.77
0.88
Vrms
THD+N
THDDA
-
0.03
-
%
0dB,1kHz
S/N
S/NDA
-
90
-
dB
0dB,1kHz,A-weighted
Total
Circuit current
DVDDIO,DVDDPLL,AVDDDA1,
AVDDDA2
Regulator
Output voltage
IO=100mA
PLLA
Lock frequency
BCK=3.072MHz (fs=48kHz)
Audio DAC
16bitDAC
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© 2012 ROHM Co., Ltd. All rights reserved.
3/53
2012.03 - Rev.A
Technical Note
BU9408KS2
LDOPOFF
DVDDREG
DVDDCOR2
ANATEST
DVDDIO
XO
XI
DGNDIO2
SPDIFO
AMCLKO
LRCKO
BCKO
DATAMO
●Block diagram
39
38
37
36
35
34
33
32
31
30
29
28
27
26 DATASO
DGNDREG 40
LDO15
LRCKI1 41
BCKI1 42
Clock Gen.
I/F Logic
24 ERR1_LRC
DSP
Program
Logic
Coef. ROM
Data RAM
DATAI1 43
25 ERR2_BCK
Coef. RAM
ΔΣ
Stereo
DAC
LRCKI2 44
BCKI2 45
DATAI2 46
DSP
LRCKI3 47
BCKI3 48
21 VREFDA
x8 Over
Sampling
Digital Filter
19 AVDDDA2
20 AOUTR2
18 AVDDDA1
PLL_ASRC
PLL_ASRC
17 AOUTL1
PLL8
BCKI4 51
22 AOUTL2
x8 Over
Sampling
Digital Filter
DATAI3 49
LRCKI4 50
23 AGNDDA2
16bit
Stereo
DAC
ASRC
Monitor
&
Command
I/F
I/F
Logic
16 AOUTR1
15 AGNDDA1
FILT2
SCANTEST
I2CADR
8
9
10
11
12
13
MUTE2B
DGNDPLL
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© 2012 ROHM Co., Ltd. All rights reserved.
7
MUTE1B
6
DVDDCOR1
5
RESETB
4
DGNDIO1
3
SDA
2
SCL
1
FILT1
14 MUTE3B
DVDDPLL
DATAI4 52
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Technical Note
BU9408KS2
●Pin Description(s)
No.
1
2
Name
DVDDPLL
Description of terminals
Power supply for PLL
FILT1
PLLA filter connect terminal 1
Type
－
No.
27
Name
DATAMO
Description of terminals
I2S audio Main data output
G
28
BCKO
I2S audio bit transfer clock output
2
Type
D
D
3
DGNDPLL
GND for PLL
-
29
LRCKO
I S audio LR sampling clock output
D
4
FILT2
PLLA filter connect terminal 2
G
30
AMCLKO
I2S audio Synchronous clock output
D
D
5
SCANTEST
Test mode select pin
A
31
SPDIFO
S/PDIF output
6
I2CADR
I2C slave address select pin
B
32
DGNDIO2
Digital I/O GND 2
-
7
SCL
I2C transfer clock input pin
I
33
XI
X’tal 24.576MHz input
F
8
SDA
I2C data I/O pin
H
34
XO
X’tal 24.576MHz output
F
9
DGNDIO1
Digital I/O GND
-
35
DVDDIO
Digital I/O power supply
-
10
RESETB
“L” → reset condition
B
36
ANATEST
Analog test mode select pin
G
11
DVDDCOR1
Power supply for Digital core 1
-
37
DVDDCOR2
Power supply for Digital core 2
-
12
MUTE1B
“L” → Digital-out mute
B
38
DVDDREG
power supply for Regulator
-
13
MUTE2B
“L” → Audio DAC mute
B
39
LDOPOFF
Regulator POFF signal
G
14
MUTE3B
“L” → 16bit DAC mute
B
40
DGNDREG
GND for Regulator
-
15
AGNDDA1
GND for DAC 1
-
41
LRCKI1
I2S audio LR sampling clock input 1 C
16
AOUTR1
Audio DAC Rch output 1
G
42
BCKI1
I2S audio bit transfer clock input 1
C
17
AOUTL1
Audio DAC Lch output 1
G
43
DATAI1
I2S audio data input 1
C
2
18
AVDDDA1
Power supply for DAC 1
-
44
LRCKI2
I S audio LR sampling clock input 2 C
19
AVDDDA2
Power supply for DAC 2
-
45
BCKI2
I2S audio bit transfer clock input 2
C
20
AOUTR2
Audio DAC Rch output 2
G
46
DATAI2
I2S audio data input 2
C
2
21
VREFDA
Reference voltage only for DAC
G
47
LRCKI3
I S audio LR sampling clock input 3 C
22
AOUTL2
Audio DAC Lch output 2
G
48
BCKI3
I2S audio bit transfer clock input 3
23
AGNDDA2
GND for DAC 2
-
49
DATAI3
2
I S audio data input 3
C
C
2
24
ERR1_LRC
PLL1 Error / LRCK output
D
50
LRCKI4
I S audio LR sampling clock input 4 C
25
ERR2_BCK
PLL2 Error / BCK output
D
51
BCKI4
I2S audio bit transfer clock input 4
26
DATASO
2
I S audio SUB data output
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© 2012 ROHM Co., Ltd. All rights reserved.
D
5/53
52
DATAI4
2
I S audio data input 4
C
C
2012.03 - Rev.A
Technical Note
BU9408KS2
●Terminal equal circuit figure
A
B
C
DVDDIO
DVDDIO
DVDDIO
DGNDIO
D
DGNDIO
DGNDIO
E
F
DVDDIO
DVDDIO
DVDDIO
DVDDIO
Test Input
XI
DGNDIO
G
DGNDIO
XO
DGNDIO
H
DGNDIO
I
AVDD,DVDDIO
DGNDIO
AGND,DGNDIO
DGNDIO
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© 2012 ROHM Co., Ltd. All rights reserved.
6/53
2012.03 - Rev.A
Technical Note
BU9408KS2
1.
Command Interface
BU9408KS2 uses I2C-bus system for the command interface with a host CPU.
The register of BU9408KS2 has Write-mode and Read-mode.
BU9408KS2 specifies a slave address and 1 byte of selection address, and it performs writing and read-out.
2
The slave mode format of I C bus is shown below.
MSB
LSB
MSB
LSB
MSB
S Slave Address
A Select Address
A Data
LSB
A
P
S : Start condition
Slave Address : After the slave address (7 bits) set up by I2CADR, bit of a read-mode (H") and a write-mode (L") is attached,
and a total of 8-bit data is sent. (MSB first)
A: Acknowledge An acknowledge bit is added on to each bit of data transmitted.
When data transmission is being done correctly, “L” is transmitted.
“H” transmission means there was no acknowledge.
Select Address: BU9408KS2 uses a 1-byte select address. (MSB first)
Data:
P:
Data byte, transmitted data (MSB first)
Stop condition
MSB
SDA
6
5
LSB
SCL
Start Condition
When SDA↓ , SCL=”H”
1-1.
Stop Condition
When SDA↑ , SCL=”H”
Data Write-In
S
Slave Address
A
Select Address
A
Data
A
: Master to Slave
ADDR=0
MSB
A6
A5
1
0
A4
0
A3
0
A2
0
A1
0
A0
0
LSB
R/W
0
ADDR=1
MSB
A6
A5
1
0
A4
0
A3
0
A2
0
A1
0
A0
1
LSB
R/W
0
Select Address
20h
A
S Slave Address
（例）
80h
A
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© 2012 ROHM Co., Ltd. All rights reserved.
Data
: Slave to Master
Setting of BU9408KS2 slave address
Terminal setting
Write-mode
Slave-address
ADDR
0
80h
1
82h
A Data
00h
00h
: Master to Slave
7/53
P
A
Data
A
P
00h
: Slave to Master
2012.03 - Rev.A
Technical Note
BU9408KS2
Write-in Procedure
Step
Clock
1
Master
Slave(BU9408KS2)
Note
Start Condition
2
7
Slave Address
3
1
R/W (0)
4
1
5
8
6
1
7
8
8
1
9
&h80 (&h82)
Acknowledge
Select Address
Write-in target register: 8bit
Acknowledge
Data
8bit write-in data
Acknowledge
Stop Condition
When transmitting continuous data, the auto-increment function moves the select address up by one.
Repeat steps 7 and 8.
1-2. Data Read-out
During read-out, the corresponding read-out address is first written into the &hD0 address register (&h20h in the example).
In the following stream, the data is read out after the slave address. Do not return an acknowledge after completing the
reception.
S Slave Address
（ex.）
S
A
Req_Addr
80h
Select Address
D0h
Slave Address
(ex.)
A
A
Data 1
81h
P
20h
A
**h
: Master to Slave,
A
Data 2
A
A
Ā
Data N
**h
P
**h
: Slave to Master, A: With acknowledge,
Ā: Without acknowledge
Read-out Procedure
Step
Clock
1
Master
Slave(BU9408KS2)
Start Condition
2
7
Slave Address
3
1
R/W (0)
4
1
5
8
6
1
7
8
8
1
9
1
Stop Condition
10
1
Start Condition
11
7
Slave Address
12
1
R/W (1)
13
1
Acknowledge
14
8
Data
15
1
16
Note
&h80 (&h82)
Acknowledge
I2C read-out address
Req_Addr
&hD0
Acknowledge
Select Address
Read-out target register: 8bit
Acknowledge
&h81 (&h83)
8bit read-out data
Acknowledge
Stop Condition
When transmitting continuous data, the auto-increment function moves up the select address by one.
Repeat steps 14 and 15.
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© 2012 ROHM Co., Ltd. All rights reserved.
8/53
2012.03 - Rev.A
Technical Note
BU9408KS2
1-3. Control Signal Specifications
○ Electrical Characteristics and Timing for Bus Line and I/O Stage
SDA
t
BUF
tF
tLOW
tHD;STA
tR
SCL
t
HD;STA
P
tHIGH
t
HD;DAT
tSU;DAT
tSU;STA
S
tSU;STO
Sr
P
Fig.1-1: Timing Chart
Table 1-1: SDA and SCL Bus Line Characteristics (Ta=25℃ and VDD=3.3V)
Parameters
1
2
3
4
5
6
7
8
Symbol
Unit
Min.
Max.
0
400
kHz
BUF
1.3
－
μS
HD;STA
0.6
－
μS
LOW
1.3
－
μS
HIGH
0.6
－
μS
SU;STA
0.6
－
μS
HD;DAT
1)
0
－
μS
100
－
ns
SCL clock frequency
fSCL
Bus free time between “stop” condition and
t
“start” condition
Hold time (re-transmit) “start” condition.
High-Speed Mode
t
After this period, the first clock pulse is generated.
SCL clock LOW state hold time
t
SCL clock HIGH state hold time
t
Re-transmit set-up time of “start” condition
t
Data hold time
t
Data setup time
t
SU;DAT
9
SDA and SCL signal stand-up time
t
R
20+Cb
300
ns
10
SDA and SCL signal stand-down time
t
F
20+Cb
300
ns
11
Set-up time for “stop” condition
SU;STO
0.6
－
μS
12
Each bus line’s capacitive load
Cb
－
400
pF
t
The values above correspond with VIH min and VIL max levels.
1)
Because the transmission device exceeds the undefined domain of the SCL fall edge, it is necessary to
internally provide a minimum 300ns
hold time for the SDA signal (of VIH min of SCL signal).
The above-mentioned characteristic is a theory value in IC design and it doesn't be guaranteed by shipment inspection.
When problem occurs by any chance, we talk in good faith and correspond.
Neither terminal SCLI nor terminal SDAI correspond to 5V tolerant. Please use it within absolute maximum rating 4.5V.
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© 2012 ROHM Co., Ltd. All rights reserved.
9/53
2012.03 - Rev.A
Technical Note
BU9408KS2
2.
Data and System-clock setting
The input-and-output distribution diagram of the audio data of BU9408KS2 is shown below.
P-S
②
①
PLL1
P-EQ
EVR
S-P
S
E
L
2
⑤
P-S
S
E
L
5
I2S_OUT_Main
I2S_OUT_Sub
CONV2
SPDIF
Dec
CONV2
S S/PDIF
E
L
7
DATAMO,BCKO,LRCKO
DATASO
(ERR2_BCK, ERR1_LRC)
SPDIFO
PLL2
ERROR2
AMCLK
_OUT
Control I/F
S
E
L
3
DF1
③ ΔΣ LINE OUT
DAC
AOUTL2,AOUTR2
S
E
L
4
DF2
④ 16bit HP OUT
DAC
AOUTL1,AOUTR1
・・・
AMCLKO
Audio DSP
(BU9408KS2)
CG
SYS CLK
SEL6
ERROR1
I2S_IN4
MUTE3
I2S_IN3
S
E
L
1
Func.
Main
MUTE2
I2S_IN2
Tone
RESET
DATAI4,BCKI4,LRCKI4
ASRC
MUTE1
DATAI3,BCKI3,LRCKI3
S-P
CONV1
I2C
DATAI2,BCKI2,LRCKI2
I2S_IN1
CONV1
DSP CLK
DATAI1,BCKI1,LRCKI1
DSP operation part
BU9408KS2 has a 4-line digital stereo input, 3-line digital stereo output and 2-line analog stereo output.
The digital data input to the DSP operation part is first changed to fs=48kHz data at the ASRC (asynchronous sampling
rate converter).
DSP operation part output is changed to either I2S format digital output, S/PDIF format digital serial output or analog
output.
2-1. Input data selection to S-P Conversion 1 (SEL1)
Default = 0
Select Address
Value
Operation Description
&h03 [ 1:0 ]
0
Input data from I2S_IN1
1
Input data from I2S_IN2
2
Input data from I2S_IN3
3
Input data from I2S_IN4
2-2. Input data selection to S-P Conversion 2 (SEL1)
Default = 0
Select Address
Value
Operation Description
&h03 [ 5:4 ]
0
Input data from I2S_IN1
1
Input data from I2S_IN2
2
Input data from I2S_IN3
3
Input data from I2S_IN4
2-3. Output data selection P-S Conversion 1 for DATAMO terminal (SEL2)
Default = 0
Select Address
Value
&h04 [ 1:0 ]
0
Main data output after DSP operation
1
Sub data output after DSP operation
2
Data output before DSP operation
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© 2012 ROHM Co., Ltd. All rights reserved.
Operation Description
10/53
2012.03 - Rev.A
Technical Note
BU9408KS2
2-4. Output data selection P-S Conversion 2 for DATASO terminal (SEL2, SEL5)
Default = 0
Select Address
Value
Operation Description
&h04 [ 5:4 ]
0
Sub data output after DSP operation
1
Main data output after DSP operation
2
Data output before DSP operation
3
Data output from DF1
2-5. P-S Conversion 2 output data option (DATASO，ERR1_LRC，ERR2_BCK)
Usually, from a DATASO terminal, the result of the Sub output process of DSP is outputted to the timing (LRCKO, BCKO)
which synchronized with DATAMO.
Moreover, if this output option is set up, it will enable DATAMO to output the data of DF1 as independent data from a
DATASO terminal as a 3 line serial output with ERR1_LRC (LRCK) and ERR2_BCK (BCK).
This function is used when doing a line out output using external DAC.
Default = 0
Select Address
Value
&h0E [ 7 ]
0
Synchronous output with DATAMO (LRCKO, BCKO)
Operation Description
1
Asynchronous output with DATAMO (ERR1_LRC, ERR2_BCK)
If this function is used, the monitor of the error flag from ERROR1 and ERROR2 terminal will not be made.
2-6. Output data selecting of SPDIFO terminal (SEL1, SEL7)
Default = 0
Select Address
Value
Operation Description
&h05 [ 3:0 ]
0
Data output before DSP operation
1
Main data output after DSP operation
2
Sub data output after DSP operation
3
Output data from I2S_IN1 (Only data of S/PDIF form)
4
Output data from I2S_IN2 (Only data of S/PDIF form)
5
Output data from I2S_IN3 (Only data of S/PDIF form)
6
Output data from I2S_IN4 (Only data of S/PDIF form)
2-7. Output data selecting DF1＋ΔΣDAC (SEL3)
Default = 0
Select Address
Value
&h06 [ 2:0 ]
0
Output data from S-P conversion 1 (Refer to &h03 [5:4])
1
Output data from S-P conversion 2 (Refer to &h03 [1:0])
2
Data output before DSP operation
3
Main data output after DSP operation
4
Sub data output after DSP operation
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© 2012 ROHM Co., Ltd. All rights reserved.
Operation Description
11/53
2012.03 - Rev.A
Technical Note
BU9408KS2
2-8. Output data selecting DF2＋16bitDAC (SEL4)
Default = 0
Select Address
Value
Operation Description
&h06 [ 6:4 ]
0
Output data from S-P conversion 1 (Refer to &h03 [5:4])
1
Output data from S-P conversion 2 (Refer to &h03 [1:0])
2
Data output before DSP operation
3
Main data output after DSP operation
4
Sub data output after DSP operation
2-9. Output clock selecting AMCLKO terminal (SEL8)
Default = 0
Select Address
Value
&h07 [ 3:0 ]
0
Output the 256fs (12.288MHz) clock of an input from the XI terminal.
Operation Description
1
Output the 256fs clock made from PLL1
2
Output the 256fs clock made from PLL2
3
Output the 512fs (24.576MHz) clock of an input from the XI terminal.
4
Output the 512fs clock made from PLL1
5
Output the 512fs clock made from PLL2
6
Output the 128fs (6.144MHz) clock of an input from the XI terminal.
7
Output the 128fs clock made from PLL1
8
Output the 128fs clock made from PLL2
There are three system clocks used by ASRC of BU9408KS2, DSP, the P-S conversion 1, the P-S conversion 2, a SPDIF
output part, DF1+sigma-delta DAC, and DF2+16bit DAC.
One is a 24.576MHz (512fs) system clock from XI terminal, and other two are a clock of 512fs made from PLL1 or PLL2.
2-10. System Clock Selecting of Input Part of ASRC (it is Used for up sampling) (Dotted line ①)
Default = 0
Select Address
Value
Operation Description
&h08 [ 0 ]
0
The 24.576MHz (512fs) system clock from the XI terminal
1
The clock of 512fs made from PLL1 of the S-P conversion 1
2-11. The output part of ASRC (it is used for down sampling), DSP, P-S conversion 1, system clock selecting of a SPDIF output
part (Dotted line ②)
Default = 0
Select Address
Value
&h08 [ 4 ]
0
The 24.576MHz (512fs) system clock from the XI terminal
1
The clock of 512fs made from PLL1 of the S-P conversion 1
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© 2012 ROHM Co., Ltd. All rights reserved.
Operation Description
12/53
2012.03 - Rev.A
Technical Note
BU9408KS2
2-12. System Clock Selecting of DF1＋ΔΣDAC (Dotted line ③)
Default = 0
Select Address
Value
Operation Description
&h0A [ 1:0 ]
0
The 24.576MHz (512fs) system clock from the XI terminal
1
The clock of 512fs made from PLL1 of the S-P conversion 1
2
The clock of 512fs made from PLL2 of the S-P conversion 2
2-13. System Clock Selecting DF2＋16bit DAC (Dotted line ④)
Default = 0
Select Address
Value
Operation Description
&h0A [ 5:4 ]
0
The 24.576MHz (512fs) system clock from the XI terminal
1
The clock of 512fs made from PLL1 of the S-P conversion 1
2
The clock of 512fs made from PLL2 of the S-P conversion 2
When using DATASO as an asynchronous output to DATAMO, it sets up system clock selecting of the P-S conversion
2 by this command. (Dotted line ⑤)
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© 2012 ROHM Co., Ltd. All rights reserved.
13/53
2012.03 - Rev.A
Technical Note
BU9408KS2
3.
S-P Conversion 1 and S-P Conversion 2
BU9408KS2 has two built-in serial-parallel conversion circuits. (S-P Conversion 1 and S-P Conversion 2)
S-P conversions 1 and 2 are blocks which receive 3-line serial input audio data from pins and convert it to parallel data.
Input from DATAI1, BCKI1 and LRCKI1 (pins 43, 42 and 41), DATAI2, BCKI2 and LRCKI2 (pins 46, 45, and 44), DATAI3,
BCKI3 and LRCKI3 (pins 49, 48 and 47), and DATAI4, BCKI4 and LRCKI4 (pins 52, 51 and 50) are selected.
The three input formats are IIS, left-justified and right-justified.
The bit clock frequency may be selected from either 64fs or
48fs, but when 48fs is selected, the input format is always right-justified.
16bit, 20bit and 24bit output may be selected for
each format.
Below are the timing charts for each transfer format.
IIS Format
LRCKI
BCKI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
DATAI
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
LSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
S
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LSB
S
16bit
16bit
20bit
20bit
24bit
24bit
Left-Justified Format
LRCKI
BCKI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
DATAI
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MSB
S
15
16
LSB
S
16bit
16bit
20bit
20bit
24bit
24bit
Right-Justified Format
LRCKI
BCKI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MSB
DATAI
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LSB
MSB
S
LSB
S
16bit
16bit
20bit
20bit
24bit
24bit
48fs
LRCKO
BCKO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
MSB
DATAO
18
19
20
21
22
23
24
1
2
3
4
5
6
7
LSB
8
9
10
11
12
13
14
15
16
17
MSB
S
18
19
20
21
22
23
24
LSB
S
16bit
16bit
20bit
20bit
24bit
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© 2012 ROHM Co., Ltd. All rights reserved.
24bit
14/53
2012.03 - Rev.A
Technical Note
BU9408KS2
3-1. Bit Clock Frequency Configuration for 3-line Serial Input
Default = 0
Select Address
Value
Operation Description
S-P Conversion 1 &h0B [4]
0
64fs format
S-P Conversion 2 &h0C [4]
1
48fs format
3-2. Format Configuration for 3-line Serial Input
Default = 0
Select Address
Value
S-P Conversion 1 &h0B [3:2]
0
IIS format
Operation Description
S-P Conversion 2 &h0C [3:2]
1
Left-justified format
2
Right-justified format
3-3. Data Bit Width Configuration for 3-line Serial Input
Default = 0
Select Address
Value
S-P Conversion 1 &h0B [1:0]
0
16 bit
S-P Conversion 2 &h0C [1:0]
1
20 bit
2
24 bit
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© 2012 ROHM Co., Ltd. All rights reserved.
Operation Description
15/53
2012.03 - Rev.A
Technical Note
BU9408KS2
4.
Digital Sound Processing (DSP)
BU9408KS2’s Digital Sound Processing (DSP) consists of special hardware most suitable to Thin TV.
BU9408KS2 uses this special DSP to perform the following processing.
2
Prescaler, DC cut HPF, Channel Mixer, P Volume (Perfect Pure Volume), BASS, MIDDLE, TREBLE,
2
2
Pseudo Stereo, Surround, P Bass, P Treble, 7 Band Parametric Equalizer, Master Volume, L/R
Balance,
PostScaler,
Output Clipper, Sub-woofer output Processing.
DSP Outline and Signal Flow
Data width:
32 bit
Machine cycle:
40.7ns (512fs, fs=48kHz）
Data
RAM
(DATA RAM)
0
32＋32 → 32 bit
Adder:
Coefficient
operation
Circuit
MUX
32×24 → 56 bit
Multiplier:
Input
Data RAM:
256×32 bit
Coefficient RAM:
128×24 bit
M
U
X
MUX
Coefficient
RAM
Decoder
circuit
Sampling frequency: fs=48kHz
Master clock:
512fs (24.576MHz, fs=48kHz)
ADD
Acc
Output
Digital signal from 16bit to 24bit is inputted to DSP,
and it is extended by +8bit (+42dB) as overflow margin on the upper side.
The clip process is performed in DSP when the process exceeding this range is performed.
Input1
Pre
scaler
HPF
Channel
mixer
P2Volume
BASS
MIDDLE
TREBLE
Scaler
1
Pseude
stereo
＆
surround
P2Bass
P2Treble
Channel
Channel
mixer
LPF
mixer
Scaler
2
7Band
P-EQ
EVR
＆
Blance
Post
scaler
＆
Clipper
Main output
3band
P-EQ
EVR
＆
Balance
Post
scaler
＆
Clipper
Sub output
Digital Audio Processing Signal Flow
4-1. Prescaler
When digital signal is inputted to audio DSP, if the level is full scale input and the process of surround or equalizer is
performed, then it overflows, therefore the input gain is adjusted by prescaler.
Adjustable range is +24dB to -103dB and can be set by the step of 0.5dB.
Prescaler does not incorporate the smooth transition function.
Default = 30h
Select Address
Operational explanation
command
00
01
&h20 [ 7:0 ]
…
30
31
32
0dB
-0.5dB
-1dB
…
…
16/53
…
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© 2012 ROHM Co., Ltd. All rights reserved.
gain
+24dB
+23.5dB
FE
FF
-103dB
-∞
2012.03 - Rev.A
Technical Note
BU9408KS2
4-2. DC cut HPF
The DC offset component of digital signal inputted to the audio DSP is cut by this HPF.
The cut off frequency (fc) of HPF is 1Hz, and first-order filter is used.
Default = 0
Select Address
Value
Operational explanation
&h21 [ 0 ]
0
Not using the DC cut HPF
1
Using the DC cut HPF
4-3. Channel mixer
It performs the setting of mixing the sounds of left channel & right channel of digital signal inputted to the audio DSP.
Here the stereo signal is made to be monaural.
The data inputted to Lch of DSP is mixed.
Default = 0
Select Address
Value
Operational explanation
&h22 [ 7:6 ]
0
Inputting the Lch data
1
Inputting the data of (Lch + Rch) / 2
2
Inputting the data of (Lch + Rch) / 2
3
Inputting the Rch data
The data inputted to Rch of DSP is mixed.
Default = 0
Select Address
Value
&h22 [ 5:4 ]
0
Inputting the Rch data
1
Inputting the data of (Lch + Rch) / 2
2
Inputting the data of (Lch + Rch) / 2
3
Inputting the Lch data
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Operational explanation
17/53
2012.03 - Rev.A
Technical Note
BU9408KS2
4-4. P2Volume （Perfect Pure Volume）
There are some scenes in which sound suddenly becomes large like plosive sound in TV Commercial or Movie.
2
P Volume function automatically controls the volume and adjusts the output level.
In addition, it also adjusts in such a way that a whispery sound can be heard easily.
2
P Volume function operates in the fields of (1), (2) & (3) divided according to input level.
P2V off
VO
(1) at the time of VＩinf(-∞)～VＩmin
2
Noise is prevented from being lifted by P Volume function.
K
(2) When input level is over VＩmin and output is below VOmax
(3)
VO = VI + α
α： Lifting the Whole output level by the offset value α
VOmax
(3) When output level ＶＯ exceeds VOmax
P2V_MAX
(2)
VO = K・VI + α
K：
Slope for suppressing of D range （P2V_K）
It is also possible to set an output level constant.
VOmin
α
(1)
VOinf
2
Selection of using the P Volume function.
VIinf
Default = 0
VImin
0dB
P2V_MIN
Select Address
Value
&h33 [ 7 ]
VI
Operational explanation
2
0
Not using the P Volume function
1
Using the P2Volume function
Setting of VＩmin
2
In order to cancel that noise etc. is lifted by P Volume, the P2V_MIN sets the minimum level at which (to the minimum) the
2
P Volume functions.
command
Default = 00h
Select Address
&h34 [ 4:0 ]
Operational explanation
command
00
01
02
03
04
05
06
07
gain
-∞
-30dB
-32dB
-34dB
-36dB
-38dB
-40dB
-42dB
command
08
09
0A
0B
0C
0D
0E
0F
gain
-44dB
-46dB
-48dB
-50dB
-52dB
-54dB
-56dB
-58dB
command
10
11
12
13
14
15
16
17
gain
-60dB
-62dB
-64dB
-66dB
-68dB
-70dB
-72dB
-74dB
コマンド値
18
19
1A
1B
1C
1D
1E
1F
ゲイン
-76dB
-78dB
-80dB
-82dB
-84dB
-86dB
-88dB
-90dB
Setting of VＯmax
P2V_MAX sets the output suppression level. It represents the output level VＯmax at the time of input level VI = 0dB in the
case of setting of P2V_K = “0h” (slope is 0).
Default = 00h
Select Address
&h35 [ 4:0 ]
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© 2012 ROHM Co., Ltd. All rights reserved.
Operational explanation
command
00
01
02
03
04
05
06
07
gain
0dB
-1dB
-2dB
-3dB
-4dB
-5dB
-6dB
-7dB
command
08
09
0A
0B
0C
0D
0E
0F
18/53
gain
-8dB
-9dB
-10dB
-11dB
-12dB
-13dB
-14dB
-15dB
command
10
11
12
13
14
15
16
17
gain
-16dB
-17dB
-18dB
-19dB
-20dB
-21dB
-22dB
-23dB
command
18
19
1A
1B
1C
1D
1E
1F
gain
-24dB
-25dB
-26dB
-27dB
-28dB
-29dB
-30dB
-
2012.03 - Rev.A
Technical Note
BU9408KS2
Setting of K
P2V_K sets the slop of D range. It sets the P2V_MAX = “1Eh” (-30dB) and represents the output level VＯmax at the time of
input level VI = 0dB.
Default = 00h
Select Address
Operational explanation
&h36 [ 3:0 ]
command
0
1
2
3
4
5
6
7
gain
-30dB
-28dB
-26dB
-24dB
-22dB
-20dB
-18dB
-16dB
comman
8
9
A
B
C
D
E
F
gain
-14dB
-12dB
-10dB
-8dB
-6dB
-4dB
-2dB
0dB
Setting of α
P2V_OFS makes small voice easy to be heard because the whole output level is lifted.
Default = 00h
Select Address
&h37 [ 4:0 ]
Operational explanation
command
00
01
02
03
04
05
06
07
gain
0dB
+1dB
+2dB
+3dB
+4dB
+5dB
+6dB
+7dB
command
08
09
0A
0B
0C
0D
0E
0F
gain
+8dB
+9dB
+10dB
+11dB
+12dB
+13dB
+14dB
+15dB
command
10
11
12
13
14
15
16
17
gain
+16dB
+17dB
+18dB
+19dB
+20dB
+21dB
+22dB
+23dB
command
18
19
1A
1B
1C
1D
1E
1F
gain
+24dB
-
Setting 1 of transition time at the time of attack
2
A_RATE is the setting of transition time when the state of P Volume function is transited to (2)→(3).
Default = 0
Select Address
&h38 [ 6:4 ]
Operational explanation
command A_RATE time command A_RATE time
5ms
4
0
1ms
1
2ms
5
10ms
2
6
20ms
3ms
3
4ms
7
40ms
Setting 1 of transition time at the time of recovery
2
R_RATE is the setting of transition time when the state of P Volume function is transited to (3)→(2).
Default = 0h
Select Address
Operational explanation
command R_RATE time command R_RATE time
0
0.25s
8
3s
1
0.5s
9
4s
0.75s
5s
2
A
3
1s
B
6s
4
1.25s
C
7s
5
1.5s
D
8s
6
2s
E
9s
7
2.5s
F
10s
&h38 [ 3:0 ]
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19/53
2012.03 - Rev.A
Technical Note
BU9408KS2
Explanation of A_RATE,R_RATE(field transition of (2)<->(3))
Time
T
VI
Input
Field (2)
Field (3)
Field (2)
VOmax
Output
Time
T
VO
Attack operation
A_RATE
The time from exceeding the
attack operation detection level
VＯmax till the attack operation's
transition to Field ( 3 ) is
completed
Recovery operation
R_RATE
The time from falling below the
recovery operation detection
level VＯmax till the recovery
operation's transition to Field
(2) is completed
Setting 1 of attack detection time
2
A_TIME is the setting of the initiation of P Volume function’s transition operation. If output level at the time of transiting to
2
(2)→(3) continues for more then A_TIME time in succession, then the state transition of P Volume is started.
Default = 0
Select Address
&h39 [ 6:4 ]
Operational explanation
command
0
1
2
3
A_TIME
0.5ms
1ms
1.5ms
2ms
command
4
5
6
7
A_TIME
3ms
4ms
5ms
6ms
Setting 1 of recovery detection time
2
R_TIME is the setting of the initiation of P Volume function’s transition operation. If output level at the time of transiting to
2
(3)→(2) continues for more then R_TIME time in succession, then the state transition of P Volume is started.
Default = 0
Select Address
&h39 [ 2:0 ]
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Operational explanation
command
0
1
2
3
20/53
R_TIME
50ms
100ms
150ms
200ms
command
4
5
6
7
R_TIME
300ms
400ms
500ms
600ms
2012.03 - Rev.A
Technical Note
BU9408KS2
Explanation of A_RATE_Low,R_RATE_Low(field transition of (1)<->(2))
VImin
VI
Input
Tme T
Field(1)
Field(2)
Field(1)
VOmin
Output
VO
Time T
Recovery operation
R_RATE_Low
Attack operation
A_RATE_Low
The time from falling
below
the
recovery
operation detection level
V I m i n till the recovery
operation's transition to
Field (2) is completed
The time from exceeding
the
attack
operation
detection level V I min till the
attack operation's transition
to Field (1) is completed
Setting 2 of the transition time at the time of attack
2
A_RATE_LOW is the setting of transition time when the state of P Volume function is transited to (2)→(1).
Default = 0
Select Address
&h3A [ 6:4 ]
Operational explanation
Command
0
1
2
3
A_RATE_LOW Time
1ms
2ms
3ms
4ms
Command
4
5
6
7
A_RATE_LOW Time
5ms
10ms
20ms
40ms
Setting 2 of the transition time at the time of recovery
R_RATE_LOW is the setting of transition time when the state of P2Volume function is transited to (1)→(2).
Default = 0 (Caution) This setting value is not reflected in BU9408KS2. The value of &h38 [3:0] is set up.
Select Address
&h3A [ 2:0 ]
Operational explanation
Command
0
1
2
3
R_RATE_LOW Time
1ms
2ms
3ms
4ms
Command
4
5
6
7
R_RATE_LOW Time
5ms
10ms
20ms
40ms
Setting 2 of attack recovery detection time
AR_TIME_LOW is the setting of the initiation of P2Volume function’s transition operation. If output level at the time of
transiting to (1)<->(2) continues for more then AR_TIME time in succession, then the state transition of P2Volume is started.
Default = 0
Select Address
&h3B [ 6:4 ]
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© 2012 ROHM Co., Ltd. All rights reserved.
Operational explanation
Command
0
1
2
3
21/53
AR_TIME_LOW
0.5ms
1ms
1.5ms
2ms
Command
4
5
6
7
AR_TIME_LOW
3ms
4ms
5ms
6ms
2012.03 - Rev.A
Technical Note
BU9408KS2
○Pulse sound detection and High-speed recovery function（functioning only at the time of transition of (2)<->(3)）
2
2
P Volume function makes the P Volume also compatible with large pulse sounds (clapping of hands, fireworks & shooting
2
etc.) in addition to normal P Volume operation. When large pulse sound is inputted, attack operation (A_RATE) or recovery
operation (R_RATE) is performed at 4 or 8 times the speed of normal attack operation or recovery operation.
Selection of using the pulse sound detection function.
Default = 0
Select Address
Value
Operational explanation
&h3BC [ 7 ]
0
Not using of pulse sound detection function
1
Using of pulse sound detection function
Selection of operating times of Recovery Time (R_RATE) in the case of using the pulse sound detection function
Default = 0
Select Address
Value
&h3C [ 3 ]
0
1
Operational explanation
Operating at 4 times the speed corresponding to the setting time of
R_RATE
Operating at 8 times the speed corresponding to the setting time of
R_RATE
Selection of pulse sound detection time
Default = 0
Select Address
&h3C [ 6:4 ]
Operational explanation
Command
0
1
2
3
Detection time
100us
200us
400us
1ms
Command
4
5
6
7
Detection time
2ms
5ms
10ms
20ms
Setting of operating level of pulse sound detection function
Operation is started by the difference between the presently detected value and the last value as a standard.
Default = 0
Select Address
&h3C [ 2:0 ]
Operational explanation
Command
0
1
2
3
Detection level
Over
Over
Over
Over
1.002
0.709
0.502
0.355
Command
4
5
6
7
Detection level
Over
Over
Over
Over
0.251
0.178
0.126
0.089
Example） Present detection level A ： -10dB → 10^(-10/20) = 0.32
The last detection level B
： -30dB → 10^(-30/20) = 0.032
A – B : 0.32 – 0.032 = 0.288 → Operating by the setting of command ”4” to ”7”.
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22/53
2012.03 - Rev.A
Technical Note
BU9408KS2
4-5. BASS
BASS of TONE Control can use Peaking filter or Low-shelf filter.
The setting is converted, in the IC, into digital filter’s coefficients (b0, b1, b2, a1, a2)by selecting the F0，Q and Gain, and
transmitted to coefficient RAM. The switching shock noise at the time of alteration of setting can be prevented by the smooth
transition function.
○BASS Control
Selection of filter types
Default = 0
Select Address
Value
&h40 [ 7 ]
0
Peaking filter
Operational explanation
1
Low-shelf filter
Selection of smooth transition function
Default = 0
Select Address
Value
Operational explanation
&h40 [ 6 ]
0
Using BASS smooth transition function
1
Not BASS using smooth transition function
Selection of smooth transition time
Default = 0
Select Address
Value
Operational explanation
&h40 [ 5:4 ]
0
21.4ms
1
10.7ms
2
5.4ms
3
2.7ms
Setting of smooth transition start
In the case of using the smooth transition function, after being transmitted, by the &h40[0] command, to the coefficient RAM
for smooth transition, the alteration of BASS’s coefficients is completed by using this command.
Default = 0
Select Address
Value
Operational explanation
&h4C [ 0 ]
0
BASS smooth transition stop
1
BASS smooth transition start
What is necessary is the time of waiting, which is more than the time selected by the setting of Bass smooth transition
time, from the time the BASS smooth transition start (&h4C[0] = “1”) is executed until the following command is sent. Please
make sure to perform the Bass smooth transition stop (&h4C[0] = “0”) after the smooth transition is completed.
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23/53
2012.03 - Rev.A
Technical Note
BU9408KS2
Setting of the Start of transmitting to coefficient RAM
In the case of using the smooth transition, it is transmitted to the coefficient RAM for smooth transition. In the case of not
using of the smooth transition, it is transmitted directly to the coefficient RAM.
Default = 0
Select Address
Value
Operational explanation
&h40 [ 0 ]
0
BASS coefficient transmission stop
1
BASS coefficient transmission start
Selection of frequency (F0)
Default = 0Eh
Select Address
&h41 [ 5:0 ]
Operational explanation
Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency
20Hz
50Hz
125Hz
315Hz
800Hz
2kHz
5kHz
12.5kHz
00
08
10
18
20
28
30
38
01
22Hz
09
56Hz
11
140Hz
19
350Hz
21
900Hz
29
2.2kHz
31
5.6kHz
39
14kHz
63Hz
400Hz
2.5kHz
16kHz
25Hz
160Hz
1kHz
6.3kHz
02
0A
12
1A
22
2A
32
3A
03
28Hz
0B
70Hz
13
180Hz
1B
450Hz
23
1.1kHz
2B
2.8kHz
33
7kHz
3B
18kHz
32Hz
80Hz
200Hz
500Hz
1.25kHz
3.15kHz
8kHz
20kHz
04
0C
14
1C
24
2C
34
3C
05
35Hz
0D
90Hz
15
220Hz
1D
560Hz
25
1.4kHz
2D
3.5kHz
35
9kHz
3D
0E
100Hz
40Hz
250Hz
630Hz
1.6kHz
4kHz
10kHz
06
16
1E
26
2E
36
3E
07
45Hz
0F
110Hz
17
280Hz
1F
700Hz
27
1.8kHz
2F
4.5kHz
37
11kHz
3F
-
Selection of quality factor (Q)
Default = 4h
Select Address
Operational explanation
Command
0
1
2
3
4
5
6
7
&h42 [ 3:0 ]
Command
8
9
A
B
C
D
E
F
Quality factor
0.33
0.43
0.56
0.75
1.0
1.2
1.5
1.8
Quality factor
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
Selection of Gain
Default = 40h
Select Address
Operational explanation
Command
1C
&h43 [ 6:0 ]
Gain
-18dB
…
…
3E
3F
40
41
42
-1dB
-0.5dB
0dB
+0.5dB
+1dB
…
…
64
+18dB
If the coefficient of b0, b1, b2, a1, and a2 exceeds ±4, it may not operate normally.
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24/53
2012.03 - Rev.A
Technical Note
BU9408KS2
4-6. MIDDLE
MIDDLE of TONE Control uses Peaking filter.
The setting is converted, in the IC, into digital filter’s coefficients (b0, b1, b2, a1, a2)by selecting the F，Q and Gain, and
transmitted to coefficient RAM. The switching shock noise at the time of alteration of setting can be prevented by the smooth
transition function.
○MIDDLE Control
Selection of smooth transition function
Default = 0
Select Address
Value
&h44 [ 6 ]
0
Using MIDDLE smooth transition function
Operational explanation
1
Not MIDDLE using smooth transition function
Selection of smooth transition time
Default = 0
Select Address
Value
Operational explanation
&h44 [ 5:4 ]
0
21.4ms
1
10.7ms
2
5.4ms
3
2.7ms
Setting of smooth transition start
In the case of using the smooth transition function, after being transmitted, by the &h44[0] command, to the coefficient RAM
for smooth transition, the alteration of MIDDLE’s coefficients is completed by using this command.
Default = 0
Select Address
Value
Operational explanation
&h4C [ 1 ]
0
MIDDLE smooth transition stop
1
MIDDLE smooth transition start
What is necessary is the time of waiting, which is more than the time selected by the setting of MIDDLE smooth transition
time, from the time the MIDDLE smooth transition start (&h4C[1] = “1”) is executed until the following command is sent.
Please make sure to perform the MIDDLE smooth transition stop (&h4C[1] = “0”) after the smooth transition is completed.
Setting of the Start of transmitting to coefficient RAM
In the case of using the smooth transition, it is transmitted to the coefficient RAM for smooth transition. In the case of not
using of the smooth transition, it is transmitted to the direct coefficient RAM.
Default = 0
Select Address
Value
&h44 [ 0 ]
0
MIDDLE coefficient transmission stop
1
MIDDLE coefficient transmission start
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© 2012 ROHM Co., Ltd. All rights reserved.
Operational explanation
25/53
2012.03 - Rev.A
Technical Note
BU9408KS2
Selection of frequency (F0)
Default = 0Eh
Select Address
&h45 [ 5:0 ]
Operational explanation
Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency
20Hz
50Hz
125Hz
315Hz
800Hz
2kHz
5kHz
12.5kHz
00
08
10
18
20
28
30
38
01
22Hz
09
56Hz
11
140Hz
19
350Hz
21
900Hz
29
2.2kHz
31
5.6kHz
39
14kHz
63Hz
400Hz
2.5kHz
16kHz
25Hz
160Hz
1kHz
6.3kHz
02
0A
12
1A
22
2A
32
3A
03
28Hz
0B
70Hz
13
180Hz
1B
450Hz
23
1.1kHz
2B
2.8kHz
33
7kHz
3B
18kHz
32Hz
80Hz
200Hz
500Hz
1.25kHz
3.15kHz
8kHz
20kHz
04
0C
14
1C
24
2C
34
3C
05
35Hz
0D
90Hz
15
220Hz
1D
560Hz
25
1.4kHz
2D
3.5kHz
35
9kHz
3D
0E
100Hz
40Hz
250Hz
630Hz
1.6kHz
4kHz
10kHz
06
16
1E
26
2E
36
3E
07
45Hz
0F
110Hz
17
280Hz
1F
700Hz
27
1.8kHz
2F
4.5kHz
37
11kHz
3F
-
Selection of quality factor (Q)
Default = 4h
Select Address
&h46 [ 3:0 ]
Operational explanation
Command
0
1
2
3
4
5
6
7
Quality factor
0.33
0.43
0.56
0.75
1.0
1.2
1.5
1.8
Command
8
9
A
B
C
D
E
F
Quality factor
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
Selection of Gain
Default = 40h
Select Address
Operational explanation
&h47 [ 6:0 ]
Command
1C
Gain
-18dB
…
…
3E
3F
40
41
42
-1dB
-0.5dB
0dB
+0.5dB
+1dB
…
…
64
+18dB
If the coefficient of b0, b1, b2, a1, and a2 exceeds ±4, it may not operate normally.
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26/53
2012.03 - Rev.A
Technical Note
BU9408KS2
4-7. TREBLE
TREBLE of TONE Control can use Peaking filter or High-shelf filter.
The setting is converted, in the IC, into digital filter’s coefficients (b0, b1, b2, a1, a2) by selecting the F0，Q and Gain, and
transmitted to coefficient RAM. The switching shock noise at the time of alteration of setting can be prevented by the smooth
transition function.
○TREBLE Control
Selection of filter types
Default = 0
Select Address
Value
&h48 [ 7 ]
0
Peaking filter
Operational explanation
1
High-shelf filter
Selection of smooth transition function
Default = 0
Select Address
Value
Operational explanation
&h48 [ 6 ]
0
Using smooth transition function
1
Not using smooth transition function
Selection of smooth transition time
Default = 0
Select Address
Value
Operational explanation
&h48 [ 5:4 ]
0
21.4ms
1
10.7ms
2
5.4ms
3
2.7ms
Setting of smooth transition start
In the case of using the smooth transition function, after being transmitted, by the &h48[0] command, to the coefficient RAM
for smooth transition, the alteration of TREBLE’s coefficients is completed by using this command.
Default = 0
Select Address
Value
Operational explanation
&h4C [ 2 ]
0
TREBLE smooth transition stop
1
TREBLE smooth transition start
What is necessary is the time of waiting, which is more than the time selected by the setting of TREBLE smooth
transition time, from the time the TREBLE smooth transition start (&h4C[2] = “1”) is executed until the following command is
sent. Please make sure to perform the TREBLE smooth transition stop (&h4C[2] = “0”) after the smooth transition is
completed.
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27/53
2012.03 - Rev.A
Technical Note
BU9408KS2
Setting of the Start of transmitting to coefficient RAM
In the case of using the smooth transition, it is transmitted to the coefficient RAM for smooth transition. In the case of not
using of the smooth transition, it is transmitted to the direct coefficient RAM.
Default = 0
Select Address
Value
&h48 [ 0 ]
0
TREBLE coefficient transmission stop
Operational explanation
1
TREBLE coefficient transmission start
Selection of frequency (F0)
Default = 0Eh
Select
Operational explanation
Address
&h49 [ 5:0 ]
Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency
20Hz
50Hz
125Hz
315Hz
800Hz
2kHz
5kHz
12.5kHz
00
08
10
18
20
28
30
38
01
22Hz
09
56Hz
11
140Hz
19
350Hz
21
900Hz
29
2.2kHz
31
5.6kHz
39
14kHz
63Hz
400Hz
2.5kHz
16kHz
25Hz
160Hz
1kHz
6.3kHz
02
0A
12
1A
22
2A
32
3A
03
28Hz
0B
70Hz
13
180Hz
1B
450Hz
23
1.1kHz
2B
2.8kHz
33
7kHz
3B
18kHz
32Hz
80Hz
200Hz
500Hz
1.25kHz
3.15kHz
8kHz
20kHz
04
0C
14
1C
24
2C
34
3C
05
35Hz
0D
90Hz
15
220Hz
1D
560Hz
25
1.4kHz
2D
3.5kHz
35
9kHz
3D
0E
100Hz
40Hz
250Hz
630Hz
1.6kHz
4kHz
10kHz
06
16
1E
26
2E
36
3E
07
45Hz
0F
110Hz
17
280Hz
1F
700Hz
27
1.8kHz
2F
4.5kHz
37
11kHz
3F
-
Selection of quality factor (Q)
Default = 4h
Select Address
Operational explanation
Command
0
1
2
3
4
5
6
7
&h4A [ 3:0 ]
Quality factor
0.33
0.43
0.56
0.75
1.0
1.2
1.5
1.8
Command
8
9
A
B
C
D
E
F
Quality factor
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
Selection of Gain
Default = 40h
Select Address
Operational explanation
&h4B [ 6:0 ]
Command
1C
Gain
-18dB
…
…
3E
3F
40
41
42
-1dB
-0.5dB
0dB
+0.5dB
+1dB
…
…
64
+18dB
If the coefficient of b0, b1, b2, a1, and a2 exceeds ±4, it may not operate normally.
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28/53
2012.03 - Rev.A
Technical Note
BU9408KS2
4-8. Scaler 1
Scaler adjusts the gain in order to prevent the overflow in DSP.
Adjustable range is +24dB to -103dB and can be set by the step of 0.5dB.
Scaler 1 does not incorporate the smooth transition function.
Default = 30h
Select Address
Operational explanation
Command
00
01
&h24 [ 7:0 ]
Gain
+24dB
+23.5dB
…
…
30
31
32
0dB
-0.5dB
-1dB
…
…
FE
FF
-103dB
-∞
4-9. Pseudo stereo
The sense of stereo is reproduced by signal processing of monaural voice.
Selection of filter effects of pseudo stereo
Default = 0
Select Address
Value
Operational explanation
&h71 [ 1:0 ]
0
Not using of pseudo stereo
1
Gain is set as "high"
2
Gain is set as "low"
If combined with the Surround’s setting of ON (&h70[7] = 1), it will become even wider.
Lch
Lch
Lch PHASE
SHIFTER
Rch PHASE
SHIFTER
EFFECT
GAIN
(High/Low/
OFF）
EFFECT
GAIN
(High/Low/
OFF）
Rch
Rch
4-10. Surround (Matrix Surround 3D)
It realizes the Surround with little feeling of fatigue even after wide seat spot and long-time watching & listening to. It
reproduces the feeling of broadening of the natural sounds in medium & high bands and realizes the sound field that do no
damage to the feeling of locating of the vocal.
If loop is used, then the number of stages of phase shifter can be increased in a pseudo way.
+
Lch
+ L-R
-
+
+
PHASE
SHIFTER
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© 2012 ROHM Co., Ltd. All rights reserved.
EFFECT
GAIN
LPF
+
Rch
29/53
Lch
+
Loop
Rch
2012.03 - Rev.A
Technical Note
BU9408KS2
ON/OFF of Surround function
Default = 0
Select Address
Value
Operational explanation
&h70 [ 7 ]
0
Turning the Surround effect OFF
1
Turning the Surround effect ON
Setting of using the LOOP
Default = 0
Select Address
Value
&h70 [ 5 ]
0
Not using of LOOP
Operational explanation
1
Using of LOOP
Setting of Surround gain
Default = Fh
Select Address
&h70 [ 3:0 ]
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© 2012 ROHM Co., Ltd. All rights reserved.
Operational explanation
Command
Gain
Command
Gain
0
1
2
3
4
5
6
7
0dB
-1dB
-2dB
-3dB
-4dB
-5dB
-6dB
-7dB
8
9
A
B
C
D
E
F
-8dB
-9dB
-10dB
-11dB
-12dB
-13dB
-14dB
-15dB
30/53
2012.03 - Rev.A
Technical Note
BU9408KS2
4-11. P2Bass (Perfect Pure Bass: Deep Bass Equalizer)
It is the deep bass equalizer making it possible that even thin-screen TV, by which the enclosure of speaker is restricted,
can reproduce the real sound close to powerful deep bass & original sound.
Solid & clear deep bass with little feeling of distortion is realized. Even boosting of bass does not interfere with vocal band,
therefore rich and natural deep band is realized.
Gain
Vocal
band
ボーカル帯域
P22Bass
gain
Bassゲイン
f
LPF Cutoff frequency
LPFカットオフ周波数
HPF
Cutoff frequency
HPFカットオフ周波数
2
ON/OFF of P Bass function
Default = 0
Select Address
&h73 [ 7 ]
Value
Operational explanation
2
0
Not using of P Bass function
1
Using of P2Bass function
2
Setting of P Bass smooth transition time
Default = 0
Select Address
Value
Operational explanation
&h73 [ 3:2 ]
0
21.4ms
1
10.7ms
2
5.4ms
3
2.7ms
2
P Bass smooth transition control
Default = 0
Select Address
&h77 [ 1:0 ]
Value
Operational explanation
2
0
P Bass smooth transition stop
1
Setting of the values into Coefficient RAM for P2Bass smooth transition
2
P2Bass smooth transition start
2
What is necessary is the time of waiting, which is more than the time selected by the setting of P Bass smooth transition
2
time, from the time the P Bass smooth transition start (&h77[1:0] = “2”) is executed until the following command is sent.
2
Please make sure to perform the P Bass smooth transition stop (&h77[1:0] = “0”) after the smooth transition is
completed.
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31/53
2012.03 - Rev.A
Technical Note
BU9408KS2
Setting of P2Bass deep bass gain
Default = 00h
Select Address
Operational explanation
Command
0
1
2
3
4
5
6
7
&h74 [ 7:4 ]
Gain
0dB
+1dB
+2dB
+3dB
+4dB
+5dB
+6dB
+7dB
Command
8
9
A
B
C
D
E
F
Gain
+8dB
+9dB
+10dB
+11dB
+12dB
+13dB
+14dB
+15dB
2
Setting of P Bass HPF cutoff frequency
Default = 0
Select Address
Value
Operational explanation
&h74 [ 3:2 ]
0
60Hz
1
80Hz
2
100Hz
3
120Hz
2
Setting of P Bass LPF cutoff frequency
Default = 0
Select Address
Value
&h74 [ 1:0 ]
0
120Hz
Operational explanation
1
160Hz
2
200Hz
3
240Hz
ON/OFF of pseudo bass function
It can contribute to bass emphasis effect caused by pseudo bass. And it can also be used independently.
Default = 0
Select Address
Value
Operational explanation
&h72 [ 7 ]
0
Not using of pseudo bass function
1
Using of pseudo bass function
Setting of pseudo bass gain
Default = 00h
Select Address
&h72 [ 6:4 ]
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Operational explanation
Command
0
1
2
3
32/53
Gain
-4dB
-2dB
0dB
+2dB
Command
4
5
6
7
Gain
+4dB
+6dB
+8dB
+10dB
2012.03 - Rev.A
Technical Note
BU9408KS2
4-12. P2Treble (Perfect Pure Treble: Medium・High-band equalizer)
It realizes good Clearness, sound stretch, and clear-cut manner.
It realizes such an effect that the sound is raised and can be heard when speaker is located on the underside of a device.
2
ON/OFF of P Treble function
Default = 0
Select Address
&h75 [ 7 ]
Value
Operational explanation
2
0
Not using of P Treble function
1
Using of P2Treble function
2
Setting of P Treble smooth transition time
Default = 0
Select Address
Value
&h75 [ 3:2 ]
0
21.4ms
Operational explanation
1
10.7ms
2
5.4ms
3
2.7ms
2
P Treble smooth transition control
Default = 0
Select Address
&h78 [ 1:0 ]
Value
Operational explanation
2
0
P Treble smooth transition stop
1
Setting of the values into Coefficient RAM for P2Treble smooth
transition
2
P2Treble smooth transitionＳtart
2
What is necessary is the time of waiting, which is more than the time selected by the setting of P Treble smooth
2
transition time, from the time the P Treble smooth transition start (&h78[1:0] = “2”) is executed until the following
2
command is sent. Please make sure to perform the P Treble smooth transition stop (&h78[1:0] = “0”) after the smooth
transition is completed.
2
Setting of P Treble medium・high-band gain
Default = 0h
Select Address
&h76 [ 7:4 ]
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© 2012 ROHM Co., Ltd. All rights reserved.
Operational explanation
Command
0
1
2
3
4
5
6
7
33/53
Gain
0dB
+1dB
+2dB
+3dB
+4dB
+5dB
+6dB
+7dB
Command
8
9
A
B
C
D
E
F
Gain
+8dB
+9dB
+10dB
+11dB
+12dB
+13dB
+14dB
+15dB
2012.03 - Rev.A
Technical Note
BU9408KS2
4-13.
Scaler 2
Scaler adjusts the gain in order to prevent the overflow in DSP.
Adjustable range is +24dB to -103dB and can be set by the step of 0.5dB.
Scaler 2 does not incorporate the smooth transition function.
Default = 30h
Select Address
Operational explanation
&h25 [ 7:0 ]
Command
00
01
Gain
+24dB
+23.5dB
…
…
30
31
32
0dB
-0.5dB
-1dB
…
…
FE
FF
-103dB
-∞
4-14. 7 band・parametric equalizer
7-band parametric equalizer can use Peaking filter, Low-shelf filter or high-shelf filter.
The setting is converted, in the IC, into digital filter’s coefficients (b0, b1, b2, a1, a2) by selecting the F，Q and Gain, and
transmitted to coefficient RAM. There is no smooth transition function.
Band1
Band2
Band3
Band4
Band5
Band6
Band7
Level
±18dB
(0.5dB step)
f
63
160
400
1k
2.5k
6.3k
16k
(Hz)
Selection of filter types
Default = 0
Select Address
Value
Operational explanation
bit[ 7:6 ]
0
Peaking filter
It sets to all band
1
Low-shelf filter
2
High-shelf filter
Setting of the Start of transmitting to coefficient RAM
It is transmitted to direct coefficient RAM.
Default = 0
Select Address
Value
bit [ 0 ]
0
Coefficient transmission stop
It sets to all band
1
Coefficient transmission start
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Operational explanation
34/53
2012.03 - Rev.A
Technical Note
BU9408KS2
Selection of frequency (F0)
Default = 0Eh
Select
Operational explanation
Address
bit [ 5:0 ]
It sets to all
band
Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency
20Hz
50Hz
125Hz
315Hz
800Hz
2kHz
5kHz
12.5kHz
00
08
10
18
20
28
30
38
01
22Hz
09
56Hz
11
140Hz
19
350Hz
21
900Hz
29
2.2kHz
31
5.6kHz
39
14kHz
63Hz
400Hz
2.5kHz
16kHz
25Hz
160Hz
1kHz
6.3kHz
02
0A
12
1A
22
2A
32
3A
03
28Hz
0B
70Hz
13
180Hz
1B
450Hz
23
1.1kHz
2B
2.8kHz
33
7kHz
3B
18kHz
32Hz
80Hz
200Hz
500Hz
1.25kHz
3.15kHz
8kHz
20kHz
04
0C
14
1C
24
2C
34
3C
05
35Hz
0D
90Hz
15
220Hz
1D
560Hz
25
1.4kHz
2D
3.5kHz
35
9kHz
3D
0E
100Hz
40Hz
250Hz
630Hz
1.6kHz
4kHz
10kHz
06
16
1E
26
2E
36
3E
07
45Hz
0F
110Hz
17
280Hz
1F
700Hz
27
1.8kHz
2F
4.5kHz
37
11kHz
3F
-
Selection of quality factor (Q)
Default = 4h
Select Address
Operational explanation
Command
0
1
2
3
4
5
6
7
bit [ 3:0 ]
It sets to every band
Quality factor
0.33
0.43
0.56
0.75
1.0
1.2
1.5
1.8
Command
8
9
A
B
C
D
E
F
Quality factor
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
Selection of Gain
Default = 40h
Select Address
Operational explanation
bit [ 6:0 ]
Command
1C
It sets to every band
Gain
-18dB
…
…
3E
3F
40
41
42
-1dB
-0.5dB
0dB
+0.5dB
+1dB
…
…
64
+18dB
If the coefficient of b0, b1, b2, a1, and a2 exceeds ±4, it may not operate normally.
The Select Address of each band is shown in the table below:
Band1
Band2
Band3
Band4
Band5
Band6
Band7
&h50h
&h54h
&h58h
&h5Ch
&h60h
&h64h
&h68h
F(frequency) selection bit [ 5:0 ]
&h51h
&h55h
&h59h
&h5Dh
&h61h
&h65h
&h69h
Q(Quality Factor) selection bit [ 3:0 ]
&h52h
&h56h
&h5Ah
&h5Eh
&h62h
&h66h
&h6Ah
Gain selection bit [ 6:0 ]
&h53h
&h57h
&h5Bh
&h5Fh
&h63h
&h67h
&h6Bh
Selection of filter type bit [ 7:6 ]
Setting
of
the
coefficient RAM
Start
of
transmitting
to
bit [ 0 ]
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35/53
2012.03 - Rev.A
Technical Note
BU9408KS2
4-15. Main output EVR (Electronic volume)
Volume is from+24dB to -103dB, and can be selected by the step of 0.5dB.
At the time of switching of Volume, smooth transition is performed.
The expression in the transition time from x[dB] to y[dB] is |(10^(x/20)-10^(y/20)|*21.4ms (Main output balance
Lch=Rch=0dB). The transition time is 21.4ms when it is from 0dB to -∞. Recommend that this setting value is 0dB and under.
Setting of Volume
Default = FFh
Select Address
Operational explanation
Command
00
01
&h26 [ 7:0 ]
Gain
+24dB
+23.5dB
…
…
30
31
32
0dB
-0.5dB
-1dB
…
…
FE
FF
-103dB
-∞
4-16. Main output balance
Balance can be attenuated, by the step width of 1dB, from the Volume setting value. At the time of switching, smooth
transition is performed. At the time of switching of Balance, smooth transition is performed.
The expression in the transition time from x[dB] to y[dB] is |(10^((Volume+x)/20)-10^((Volume+y)/20)|*21.4ms.
Setting of L/R Balance
Default = 80h
Select Address
Operational explanation
Command
00
01
&h27 [ 7:0 ]
Lch
0dB
0dB
Rch
-∞
-126dB
…
…
…
7E
7F
80
81
0dB
0dB
0dB
-1dB
-1dB
0dB
0dB
0dB
…
…
…
FE
FF
-126dB
-∞
0dB
0dB
4-17. Main output postscaler
It performs the level adjustment when the data calculated in the 32-bit-width DSP is outputted in the form of 24bitwidth.
Adjustable range is from +24dB to -103dB and can be set by the step of 0.5dB.
There is no smooth transition function in Postscaler.
Default = 30h
Select Address
Operational explanation
Command
00
01
&h28 [ 7:0 ]
…
30
31
32
0dB
-0.5dB
-1dB
…
…
36/53
…
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© 2012 ROHM Co., Ltd. All rights reserved.
Gain
+24dB
+23.5dB
FE
FF
-103dB
-∞
2012.03 - Rev.A
Technical Note
BU9408KS2
4-18. Main output clipper
When measuring the rated output (practical maximum output), it is measured where the total distortion rate (THD+N) is
10%. Clipping with any output amplitude is possible by using of clipper function, for example, the rated output of 10W or 5W
can be obtained by using an amplifier with 15W output.
Clip Level
Please set the &h27[7] at “H” when
using of clipper function.
Default = 0
Select Address
Value
Operational explanation
&h29 [ 7 ]
0
Not using clipper function
1
Using clipper function
Clip level is set in the form of higher-order 8 bit&h2A[7:0] and lower-order 8 bit&h2B[7:0].
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
clip_level[15:0]
0 0
1
~clip_level[15:0]
1 1
4
1
0
0
1
3
1
0
0
1
2
1
0
0
1
1
1
0
0
1
0
1
0
0
1
Maximum value
Minimum value
A positive clip level
A negative clip level
The
clip
leve
l becomes narrow if the setting value is reduced.
Negative clip level is set in such a way that it is the inversion data of positive clip level.
4-19. Selection of sub input data
Selection of Sub input (Sub woofer processing etc.).
2
2
The Sub woofer output interlocked with P Bass’s gain setting is possible by inputting the data that after P Bass processing.
In addition, in BU9409FV, the data can be inputted from SP conversion2.
Default = 0
Select Address
Value
&h2F [ 1:0 ]
0
Inputting of data that are after Scaler 1
1
Inputting of data that are after P2Bass processing
2
Inputting of data from SP conversion2
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© 2012 ROHM Co., Ltd. All rights reserved.
Operational explanation
37/53
2012.03 - Rev.A
Technical Note
BU9408KS2
4-20. Sub output channel mixer
Mixing setting of sound of the left channel and the right channel of the digital signal for sub output which is input into sound
DSP is done. The monaural conversion of the stereo signal is done here.
The data which is input into Lch of Sub output signal processing is mixed.
Default = 0
Select Address
Value
Operating explanation
&h22 [ 3:2 ]
0
Inputting the Lch data
1
Inputting the data of (Lch + Rch) / 2
2
Inputting the data of (Lch + Rch) / 2
3
Inputting the Rch data
The data which is input into Rch of Sub output signal processing is mixed.
Default = 0
Select Address
Value
Operating explanation
&h22 [ 1:0 ]
0
Inputting the Rch data
1
Inputting the data of （Lch + Rch） / 2
2
Inputting the data of （Lch + Rch） / 2
3
Inputting the Lch data
4-21. LPF for sub woofer output
It is the crossover filter (LPF) for sub woofer output.
LPF function ON/OFF.
Default = 0
Select Address
Value
Operating explanation
&h7A [ 7 ]
0
LPF function is not used
1
LPF function is used
Setting of the cut off frequency (Fc) of LPF
Default = 0h
Select Address
&h7A [ 6:4 ]
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Operating explanation
Command
0
1
2
3
38/53
Fc
60Hz
80Hz
100Hz
120Hz
Command
4
5
6
7
Fc
160Hz
200Hz
240Hz
280Hz
2012.03 - Rev.A
Technical Note
BU9408KS2
4-22. Sub output 3 band Parametric Equalizer
The peaking filter or the low shelf filter or the high shelf filter can be used by the parametric equalizer of 3 bands. By the fact
that F, Q and Gain are selected, it converts the setting to the coefficient (b0, b1, b2, a1 and a2) of the digital filter inside IC,
and transfers it to the coefficient RAM. There is no smooth transition function.
Band1
Band2
Band3
Level
±18dB
(0.5dB step)
f
63
80
100
(Hz)
Selection of filter type
Default = 0
Select Address
Value
Operating explanation
bit[ 7:6 ]
0
Peaking filter
It sets to all band
1
Low shelf filter
2
High shelf filter
Transfer start setting to coefficient RAM.
It transfers directly to coefficient RAM.
Default = 0
Select Address
Value
Operating explanation
bit [ 0 ]
0
Coefficient transmission stop
It sets to all band
1
Coefficient transmission start
Selection of frequency (F0)
Default = 0Eh
Select
Operating explanation
Address
bit [ 5:0 ]
It sets to all
band
Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency Command Frequency
20Hz
50Hz
125Hz
315Hz
800Hz
2kHz
5kHz
12.5kHz
00
08
10
18
20
28
30
38
01
22Hz
09
56Hz
11
140Hz
19
350Hz
21
900Hz
29
2.2kHz
31
5.6kHz
39
14kHz
63Hz
400Hz
2.5kHz
16kHz
25Hz
160Hz
1kHz
6.3kHz
02
0A
12
1A
22
2A
32
3A
03
28Hz
0B
70Hz
13
180Hz
1B
450Hz
23
1.1kHz
2B
2.8kHz
33
7kHz
3B
18kHz
32Hz
80Hz
200Hz
500Hz
1.25kHz
3.15kHz
8kHz
20kHz
04
0C
14
1C
24
2C
34
3C
05
35Hz
0D
90Hz
15
220Hz
1D
560Hz
25
1.4kHz
2D
3.5kHz
35
9kHz
3D
0E
100Hz
40Hz
250Hz
630Hz
1.6kHz
4kHz
10kHz
06
16
1E
26
2E
36
3E
07
45Hz
0F
110Hz
17
280Hz
1F
700Hz
27
1.8kHz
2F
4.5kHz
37
11kHz
3F
-
Selection of quality factor (Q)
Default = 4h
Select Address
Operating explanation
Command
0
1
2
3
4
5
6
7
bit [ 3:0 ]
It sets to all band
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39/53
Quality factor
0.33
0.43
0.56
0.75
1.0
1.2
1.5
1.8
Command
8
9
A
B
C
D
E
F
Quality factor
2.2
2.7
3.3
3.9
4.7
5.6
6.8
8.2
2012.03 - Rev.A
Technical Note
BU9408KS2
Selection of Gain
Default = 40h
Select Address
Operating explanation
bit [ 6:0 ]
Command
1C
…
…
It sets to all band
Gain
-18dB
3E
3F
40
41
42
-1dB
-0.5dB
0dB
+0.5dB
+1dB
…
…
64
+18dB
If the coefficient of b0, b1, b2, a1, and a2 exceeds ±4, it may not operate normally.
Select Address of every band is as in chart below
Band1
Band2
Band3
&h80h
&h84h
&h88h
F (frequency) selection bit [ 5:0 ]
&h81h
&h85h
&h89h
Q (quality factor) selection bit [ 3:0 ]
&h82h
&h86h
&h8Ah
Gain selection
&h83h
&h87h
&h8Bh
Selection of filter type bit [ 7:6 ]
Transfer start setting to coefficient RAM bit [ 0 ]
bit [ 6:0 ]
4-23. Sub output EVR (electronic volume)
The volume for sub output can select with 0.5dB step from +24dB to -103dB.
When changing volume, smooth transition is done.
The expression in the transition time from x[dB] to y[dB] is |(10^(x/20)-10^(y/20)|*21.4ms (Sub output balance Lch=Rch=0dB).
The transition time is 21.4ms when it is from 0dB to -∞. Recommend that this setting value is 0dB and under.
Volume setting
Default = FFh
Select Address
Operating explanation
Command
00
01
&h2C [ 7:0 ]
…
30
31
32
0dB
-0.5dB
-1dB
…
…
40/53
…
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© 2012 ROHM Co., Ltd. All rights reserved.
Gain
+24dB
+23.5dB
FE
FF
-103dB
-∞
2012.03 - Rev.A
Technical Note
BU9408KS2
4-24. Sub output balance
As for sub output balance, it is possible to be attenuated at 1dB step width from volume setting value. When changing
smooth transition is done.
When changing balance, smooth transition is done.
The expression in the transition time from x[dB] to y[dB] is |(10^((Volume+x)/20)-10^((Volume+y)/20)|*21.4ms.
L/R Balance setting
Default = 80h
Select Address
Operating explanation
Command
00
01
&h2D [ 7:0 ]
Lch
0dB
0dB
Rch
-∞
-126dB
…
…
…
7E
7F
80
81
0dB
0dB
0dB
-1dB
-1dB
0dB
0dB
0dB
…
…
…
FE
FF
-126dB
-∞
0dB
0dB
4-25. Sub output post scaler
The occasion when the data which is calculated with DSP of 32bit width is output at 24bit width, level adjustment is done.
The adjustment range can be set with 0.5dB step from +24dB to -103dB.
There is no smooth transition function in the sub output post scaler.
Default = 30h
Select Address
Operating explanation
Command
00
01
&h2E [ 7:0 ]
…
30
31
32
0dB
-0.5dB
-1dB
…
…
41/53
…
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© 2012 ROHM Co., Ltd. All rights reserved.
Gain
+24dB
+23.5dB
FE
FF
-103dB
-∞
2012.03 - Rev.A
Technical Note
BU9408KS2
4-26. Sub output clipper
The case when rated output (practical maximum output) of the television is measured, total harmonic distortion + noise
(THD+N) measures at the place of 10%. It can obtain the rated output of 10W and 5W for example making use of the
amplifier of 15W output, because it is possible to clip with optional output amplitude by using the clipper function.
C lip L e v e l
Please designate &h30 [7] as” H when
function.
using
sub
output
clipper
Default = 0
Select Address
Value
Operating explanation
&h30 [ 7 ]
0
Clipper function is not used
1
Clipper function is used
As for clip level, it sets with superior 8 bits &h31 [7: 0] and subordinate 8 bits &h32 [7: 0].
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
clip_level[15:0]
0 0
1
~clip_level[15:0]
1 1
4
1
0
0
1
3
1
0
0
1
2
1
0
0
1
1
1
0
0
1
0
1
0
0
1
Maximum value
Minimum value
A positive clip level
A negative clip level
When
settin
g value is made small, clip level becomes narrow.
As for negative clip level, the reversal data of positive clip level is set.
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42/53
2012.03 - Rev.A
Technical Note
BU9408KS2
4-27. Direct setting five coefficient of b0, b1, b2, a1 and a2 of Bi-quad Filter
7 bands Parametric Equalizer of main output and of 3 bands Parametric Equalizer of sub output have used the secondary
IIR type digital filter (Bi-quad Filter).
It is possible to set five coefficient 24 bit of b0, b1, b2, a1 and a2 of Bi-quad Filter (-4～+4) directly from an external.
When this function is used, it can do the filter type and frequency setting, Q value (quality factor) setting and gain setting
other than Peaking, Low-Shelf and High-Shelf unrestrictedly.
(Note) five coefficient have the necessity to make below the ±4, there is no read-out function of setting value and an
automatic renewal function of coefficient RAM.
Register for the coefficient transfer of 24bit
Before transferring into coefficient RAM in a lumping, the data is housed in the register for coefficient transfer from the
micro-computer.
Default = 00h
Select Address
Operating explanation
&h8D [ 7:0]
bit[23:16] which transfers 24 bit coefficient
&h8E [ 7:0]
bit[15:8] which transfers 24 bit coefficient
&h8F [ 7:0]
bit[7:0] which transfers 24 bit coefficient
It starts to transmit the coefficient of 24bit into coefficient RAM
Default = 0
Select Address
Value
&h8C [ 7 ]
0
Coefficient transmission stop
Operating explanation
1
Coefficient transmission start
Coefficient number appointment of coefficient RAM
Default = 00h
Select Address
Operating explanation
&h8C [ 6:0]
Coefficient number appointment of coefficient RAM
Appointment of coefficient number other than 14H↔45H is prohibition
Main output　7Band Parametric EQ
Coefficient
number ：
Coefficient
number ：
Coefficient
number ：
Coefficient
number ：
Coefficient
number ：
Coefficient
number ：
14H.
19H.
1EH.
23H.
28H.
2DH.
b0
+
+
b0
-1
Z
-1
15H.
b1
+
+
Z-1
Z
Z
BAND1 (Main)
+
b0
-1
-1
1AH.
a1
18H
16H.
b2
17H
+
b1
+
Z-1 Z-1
1BH.
a2
b2
+
1CH
BAND2 (Main)
+
b0
-1
Z
-1
Z
1FH.
a1
1DH
+
b1
+
+
Z-1 Z-1
b2
Z
BAND3 (Main)
+
b0
-1
Z
24H.
a1
22H
20H.
a2
21H
+
b1
+
+
Z-1 Z-1
b2
Z
b0
-1
Z
29H.
b1
Z-1 Z-1
2AH.
a2
BAND4 (Main)
+
-1
a1
27H
25H.
a2
26H
-1
+
b2
+
+
2BH
Z
BAND5 (Main)
a2
+
32H.
+
b0
-1
-1
Z
2EH.
a1
2CH
Coefficient
number ：
b1
Z-1 Z-1
2FH.
b2
30H
+
+
Z
BAND6 (Main)
a2
+
Z
33H.
a1
31H
+
-1
b1
35H
+
+
Z-1 Z-1
34H.
b2
Coefficient
number ：
37H.
b0
Coefficient
number ：
+
Z-1
38H.
b1
3CH.
+
b0
3AH
+
Z-1
39H.
+
Z-1 Z-1
a1
3BH
b2
BAND1 (Sub)
a2
3DH.
b1
Coefficient
number ：
+
41H.
+
b0
3FH
+
+
Z-1 Z-1
3EH.
b2
BAND2 (Sub)
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© 2012 ROHM Co., Ltd. All rights reserved.
a2
+
Z-1 Z-1
42H.
a1
40H
+
b1
44H
+
+
Z-1 Z-1
Z-1
a1
45H
43H.
b2
Z-1
a2
BAND3 (Sub)
43/53
a1
36H
BAND7 (Main)
Sub output　3Band Parametric EQ
2012.03 - Rev.A
Z-1
a2
Z-1
Technical Note
BU9408KS2
4-28. About the automatic renewal of five coefficients of b0, b1, b2, a1 and a2 of Bi-quad Filter
BASS, MIDDLE, TREBLE, main output 7 bands Parametric Equalizer and sub output 3 band Parametric Equalizer have
used coefficient RAM. As for this coefficient RAM, because direct access is not possible from the micro-computer, it cannot
refresh the register efficiently.
There is an automatic renewal function of coefficient RAM in this DSP, the automatic write-in renewal of coefficient RAM is
possible by using this function. However when 4-26 「the function of direct setting a coefficient RAM」 is utilized, it is not
possible to utilize automatic write-in renewal.
Selection of using the automatic write-in renewal function
Default = 0
Select Address
Value
Operating explanation
&h6D [ 0 ]
0
Automatic write-in renewal function is used
1
Automatic write-in renewal function is not used
The separate setting of Filter of automatic write-in renewal function
Default = 00h
Select Address
Filter
&h6E [ 0 ]
BASS
Operating explanation
0：Automatic renewal function OFF
1：Automatic renewal function ON
&h6E [ 1 ]
MIDDLE
0：Automatic renewal function OFF
1：Automatic renewal function ON
&h6E [ 2 ]
TREBLE
&h6E [ 4 ]
Sub BAND1
0：Automatic renewal function OFF
1：Automatic renewal function ON
0：Automatic renewal function OFF
1：Automatic renewal function ON
&h6E [ 5 ]
Sub BAND2
0：Automatic renewal function OFF
1：Automatic renewal function ON
&h6E [ 6 ]
Sub BAND3
0：Automatic renewal function OFF
1：Automatic renewal function ON
&h6F [ 0 ]
Main MAND1
0：Automatic renewal function OFF
1：Automatic renewal function ON
&h6F [ 1 ]
Main MAND2
0：Automatic renewal function OFF
1：Automatic renewal function ON
&h6F [ 2 ]
Main MAND3
0：Automatic renewal function OFF
1：Automatic renewal function ON
&h6F [ 3 ]
Main MAND4
0：Automatic renewal function OFF
1：Automatic renewal function ON
&h6F [ 4 ]
Main MAND5
&h6F [ 5 ]
Main MAND6
0：Automatic renewal function OFF
1：Automatic renewal function ON
0：Automatic renewal function OFF
1：Automatic renewal function ON
&h6F [ 6 ]
Main MAND7
0：Automatic renewal function OFF
1：Automatic renewal function ON
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44/53
2012.03 - Rev.A
Technical Note
BU9408KS2
5.
P-S Conversion 1 and P-S Conversion 2
BU9408KS2 has two built-in parallel-serial conversion circuits (P-S Conversion 1 and P-S Conversion 2). P-S conversion 1
converts the output from the ASRC or DSP (Main/Sub) output to 3-line serial data before sending it from DATAMO, BCKO
and LRCKO (pins 27, 28 and 29). (Refer to &h04 [1:0])
P-S conversion 2 converts the ASRC or DSP (Main/Sub) output or DF1 output into 3-line serial data before transmitting it
from DATASO, BCKO and LRCKO (pins 26, 28 and 29). Moreover, it is also possible to output the synchronous clock for
serial transfer from ERR1_LRC and an ERR2_BCK terminal by an output option (Refer to &h04 [5:4]).
The three output formats are IIS, left-justified and right-justified. 16bit, 20bit and 24bit output can be selected for each
format.
The timing charts for each transfer format are as follows:
IIS Format
LRCKO
BCKO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
DATAO
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
LSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MSB
S
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LSB
S
16bit
16bit
20bit
20bit
24bit
24bit
Left-Justified Format
LRCKO
BCKO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MSB
DATAO
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MSB
S
15
16
LSB
S
16bit
16bit
20bit
20bit
24bit
24bit
Right-Justified Format
LRCKO
BCKO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MSB
DATAO
31
32
1
2
3
4
5
6
LSB
S
7
8
9
10
11
12
13
14
15
16
MSB
LSB
S
16bit
16bit
20bit
20bit
24bit
24bit
5-1. 3-line Serial Output Format Configuration
Default = 0
Select Address
Value
P-S Conversion 1 &h0D [3:2]
0
IIS format
Operation Description
P-S Conversion 2 &h0E [3:2]
1
Left-justified format
2
Right-justified format
5-2. 3-line Serial Output Data Bit Width Configuration
Default = 0
Select Address
Value
P-S Conversion 1 &h0D [1:0]
0
16 bit
P-S Conversion 2 &h0E [1:0]
1
20 bit
2
24 bit
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© 2012 ROHM Co., Ltd. All rights reserved.
Operation Description
45/53
2012.03 - Rev.A
Technical Note
BU9408KS2
6.
8x Over-Sampling Digital Filter (DF)
In each BU9408KS2 audio analog signal output DAC, an 8x over-sampling digital filter is inserted into the previous step of
the DAC input.
In addition to filter calculations, this block also performs pre-scaler, volume and Lch/Rch mix functions.
BU9408KS2’s DF+DAC configurations are as follows:
DF1
DF2
Pre-scaler
Pre-scaler
Volume
Volume
Chanel Mixer
Chanel Mixer
X8 Oversampling
Digital filter
X8 Oversampling
Digital filter
ΔΣDAC
16bit DAC
AOUTL2
(22PIN)
AOUTR2
(20PIN)
AOUTL1
(17PIN)
AOUTR1
(16PIN)
6-1. Pre-Scaler Function (Attenuation)
The signal levels are adjusted in order to bring out the audio DAC performance.
For DF1, refer to &h90[7:0] and &h91[7:0]. The default value is h4000.
For DF1, refer to &h93[7:0] and &h94[7:0]. The default value is h4000.
6-2. Volume Function
The volume value can be configured in 0.5dB increments from +6dB to -121dB.
To change the volume value, coefficient soft transition takes place.
The expression in the transition time from x[dB] to y[dB] is |(10^(x/20)-10^(y/20)|*21.4ms. The transition time is 21.4ms when
it is from 0dB to -∞. Recommend that this setting value is 0dB and under.
Default = FFh
Select Address
Operation Description
DF1 &h92 [ 7:0 ]
DF2 &h95 [ 7:0 ]
Calculation format: (12-command value) x 0.5dB
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46/53
2012.03 - Rev.A
Technical Note
BU9408KS2
6-3. Channel Mixer
Performs mixing configuration of left and right channel sounds of digital signals input to the DAC.
Stereo signals are converted to monaural here.
Mixes DAC Lch input data.
Default = 0
Select Address
Value
Operation Description
DF1 &h23 [ 3:2 ]
0
Inputs Lch data
DF2 &h23 [ 7:6 ]
1
Inputs (Lch+Rch)/2 data
2
Inputs (Lch+Rch)/2 data
3
Inputs Rch data
Mixes DAC Rch input data.
Default = 0
Select Address
Value
DF1 &h23 [ 1:0 ]
0
Inputs Rch data
DF2 &h23 [ 5:4 ]
1
Inputs (Lch+Rch)/2 data
2
Inputs (Lch+Rch)/2 data
3
Inputs Lch data
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© 2012 ROHM Co., Ltd. All rights reserved.
Operation Description
47/53
2012.03 - Rev.A
Technical Note
BU9408KS2
7. Mute Function by MUTE1B, MUTE2B and MUTE3B Terminal
BU9408KS2 has a mute function by an external terminal.
It's possible to mute DSP's main and sub digital output by MUTE1B (12pin) terminal to “L”.
It's possible to mute DF1+ΔΣDAC output by MUTE2B (13pin) terminal to “L”.
It's possible to mute DF2＋16bit DAC output by MUTE3B (14pin) terminal to “L”.
Soft mute transition time setup of a MUTE1B terminal (12PIN)
Mute the Main and Sub output of DSP.
Select the transition time of entering from 0dB to mute state.
Default = 0
Select Address
Value
Operating Description
&h10 [ 1:0 ]
0
21.4ms
(Release mute time is 21.4ms.)
1
10.7ms
(Release mute time is 10.7ms.)
2
5.4ms
(Release mute time is 10.7ms.)
3
2.7ms
(Release mute time is 10.7ms.)
Soft mute transition time setup of a MUTE2B terminal (13PIN)
Mute the AOUTL2(22PIN) and AOUTR2(20PIN) output of DF1+ΔΣDAC.
Select the transition time of entering from 0dB to mute state.
Default = 0
Select Address
Value
Operating Description
&h10 [ 3:2 ]
0
21.4ms
(Release mute time is 21.4ms.)
1
10.7ms
(Release mute time is 10.7ms.)
2
5.4ms
(Release mute time is 10.7ms.)
3
2.7ms
(Release mute time is 10.7ms.)
Soft mute transition time setup of a MUTE3B terminal (14PIN)
Mute the AOUTL1(17PIN) and AOUTR1(16PIN) output of DF2+16bit DAC.
Select the transition time of entering from 0dB to mute state.
Default = 0
Select Address
Value
&h10 [ 5:4 ]
0
21.4ms
(Release mute time is 21.4ms.)
1
10.7ms
(Release mute time is 10.7ms.)
2
5.4ms
(Release mute time is 10.7ms.)
3
2.7ms
(Release mute time is 10.7ms.)
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© 2012 ROHM Co., Ltd. All rights reserved.
Operating Description
48/53
2012.03 - Rev.A
Technical Note
BU9408KS2
8. Commands Transmitted after Reset Release
The following commands must be transmitted after reset release, including after power supply stand-up.
0．Turn power on.
↓
Wait approximately 1ms until oscillation is stable. (The time to stabilization should be adjusted according to the
pendulum product.)
↓
1. Reset release (RESETB = “H”), Mute release (MUTE1B,MUTE2B,MUTE3B = “H”)
↓
Wait approximately 500us until RAM initialization is complete.
↓
2. &hF1[2] = 0 : Signals from the analog block are connected to the digital block.
↓
3. &hF3[1] = 0 : CLK100M for a down sample block of ASRC is set as a normal mode. (&hF3 = 00h）
↓
4．&hB0[5:4] = 0 : Configure PLL clock to regular use state. (&hB0 = 02）
↓
5. &hB1[7:0] = AAh : The phase of the clock outputted from PLL is adjusted.
↓
6. &h03[5:4][1:0] = 0 : Select input at SP1 and SP2.
↓
7. &h18[7] = 0 : Set 1 when use SPDIF. (Needless set when not use SPDIF.)
↓
8. &hA0 = A6h : Configure PLLA1.
&hA1 = A0h
&hA2 = A4h
&hA3 = A4h
&hA4 = 00h
&hA7 = 40h
↓
9. &hA8 = A6h : Configure PLLA2.
&hA9 = A0h
&hAA = A4h
&hAB = A4h
&hAC = 00h
&hAF = 40h
↓
Wait approximately 20ms until PLL is stable.
↓
10. &h01[7:6] = 0 : The data clear of built-in RAM is completed and it changes into the condition
that RAM can be used.
↓
11. &h08[4][0] = 0 : Configure system clock..
↓
12. &h14 = C0h : The data clear of ASRC is completed and it changes into normal condition.
&h14 = 40h
&h14 = 01h
↓
13. Configuration of other registers.
&h26[7:0] = **h : Mute release of Main data output volume （30h = 0dB）
&h2C[7:0] = **h : Mute release of Sub data output volume (30h = 0dB)
&h92[7:0] = **h : Mute release of DF1+ΔΣDAC output volume （0Ch = 0dB）
&h95[7:0] = **h : Mute release of DF2+16bitDACoutput volume （0Ch = 0dB）
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© 2012 ROHM Co., Ltd. All rights reserved.
49/53
2012.03 - Rev.A
Technical Note
BU9408KS2
9.
Audio Interface Signal Specification
○Electric specification and timing of MCK, BCK, LRCK, and SDATA1 and SDATA2
LR C K
tBLR DG
tLBR DG
BCK
tBC KH
tBC KL
tSU;SD
tHD;SD
DATA
Fig 9-1 Audio interface timing
Parameter
1
2
3
4
Max.
Unit
Frequency
fSCLK
4.096
24.576
MHz
dSCLK
40
60
%
Frequency
fLRCK
32
48
kHz
DUTY
dLRCK
40
60
%
Cycle
tBCK
325
－
ns
H width
tBCKH
130
－
ns
L width
tBCKL
130
－
ns
It is time to the edge of LRCK from a BCK rising edge.*1
tBLRDG
20
－
ns
LRCK
BCK
7
8
Min.
DUTY
MCK
5
6
Sign
9
It is time to a BCK rising edge from the edge of LRCK.*1
tLBRDG
20
-
ns
10
Setup time of SDATA
tSU;SD
20
-
ns
11
Hold time of SDATA
tHD;SD
20
－
ns
*1 This standard value has specified that the edge of LRCK and the rising edge of BCK do not overlap.
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© 2012 ROHM Co., Ltd. All rights reserved.
50/53
2012.03 - Rev.A
Technical Note
BU9408KS2
10. Notes at the Time of Reset
Since the state of IC is not decided, please make it into RESETB=L at the time of a power supply injection, and surely apply
reset.
Reset of BU9408KS2 is performing noise removal by MCLK.
Therefore, in order to apply reset, a MCLK clock pulse is required of the state of RESETB=L more than 10 times.
The power-on reset after a power supply injection, and when you usually apply reset at the time of operation, please be sure
to carry out in the state where the clock is inputted, from MCLK.
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© 2012 ROHM Co., Ltd. All rights reserved.
51/53
2012.03 - Rev.A
Technical Note
BU9408KS2
●Cautions
(1) ABSOLUTE MAXIMUM RATINGS
Permanent device damage may occur and break mode (open or short) can not be specified if power supply, operating
temperature, and those of ABSOLUTE MAXIMUM RATINGS are exceeded. If such a special condition is expected,
components for safety such as fuse must be used.
(2)Regarding of SCLI and SDAI terminals
SCLI and the SDAI terminal do not support 5 V-tolerant. Please use it within absolute maximum rating (4.5V).
(3) Power Supply
Power and Ground line must be designed as low impedance in the PCB. Print patterns if digital power supply and analog
power supply must be separated even if these have same voltage level. Print patterns for ground must be designed as
same as power supply. These considerations avoid analog circuits from the digital circuit noise. All pair of power supply
and ground must have their own de-coupling capacitor. Those capacitor should be checked about their specification, etc.
(nominal electrolytic capacitor degrades its capacity at low temperature) and choose the constant of an electrolytic
capacitor.
(4) Functionality in the strong electro-magnetic field
Malfunction may occur if in the strong electro-magnetic field.
(5) Input terminals
All LSI contain parasitic components. Some are junctions which normally reverse bias. When these junctions forward bias,
currents flows on unwanted path, malfunction or device damage may occur. To prevent this, all input terminal voltage
must be between ground and power supply, or in the range of guaranteed value in the Electrical characteristics. And no
voltage should be supplied to all input terminal when power is not supplied.
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© 2012 ROHM Co., Ltd. All rights reserved.
52/53
2012.03 - Rev.A
Technical Note
BU9408KS2
●Ordering Information
B
U
9
4
0
8
Part Number
K
S
E2
2
Package
KS2: SQFP-T52
Packaging and forming specification
None: Tray, Tube
●Physical Dimension Tape and Reel Information
SQFP-T52
<Tape and Reel information>
12.0±0.3
10.0±0.2
27
40
26
52
14
Container
Tray (with dry pack)
Quantity
1000pcs
Direction of feed Direction of product is fixed in a tray
0.5
10.0 ± 0.2
12.0 ± 0.3
39
1pin
13
1
1.4 ± 0.1
0.1 ± 0.1
0.125±0.1
0.15
0.65
0.3±0.1
∗ Order quantity needs to be multiple of the minimum quantity.
(Unit : mm)
●Marking Diagram(s)(TOP VIEW)
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© 2012 ROHM Co., Ltd. All rights reserved.
53/53
2012.03 - Rev.A
Datasheet
Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
, transport
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice - GE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,
please consult with ROHM representative in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
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for infringement of any intellectual property rights or other damages arising from use of such information or data.:
2.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the information contained in this document.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice - GE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.001