Si52146 PCI-Express Gen1, Gen2, & Gen3 Six Output Clock Generator (Chinese)

Si52146
P C I - E X P R E S S 1 代、 2 代 和 3 代 六 输 出
时钟发生器
特点







PCI-Express 1 代、 2 代和 3 代兼容
100 MHz 下支持串行 ATA (SATA)

低功耗推拉式 HCSL 兼容差分输出 
无需终端电阻
各时钟专用输出使能引脚

引脚可选扩频控制

最高六个 PCI-Express 时钟输出

25 MHz 晶体输入或时钟输入
支持 I2C,带逆读功能
使用三角扩频改善图最大程度地减少
电磁干扰 (EMI)
工业温度:–40 至 85 oC
3.3 V 电源
32- 引脚 QFN 封装
应用
网络附加存储
 多功能打印机
无线接入点
 交换机


订购信息:
参阅第 18 页
Si52146 是高性能 PCIe 时钟发生器,可用一个 25 MHz 晶体作为六个
PCIe 时钟的源或时钟输入。时钟输出兼容 PCIe 1 代、 2 代和 3 代规格。
设备有六个用于启用和禁用差分输出的输出使能控制引脚。另还有一个用
于降低 EMI 的扩频控制引脚。 Si52146 的小体积和低功耗使其成为消费者
和嵌入应用的理想解决方案。
引脚分配
功能方框图
DIFF0
SCLK
28
CKPWRGD/PDB1
29
SDATA
30
VDD_CORE
31
XOUT
OE_DIFF01
32
XIN/CLKIN
OE_DIFF11
描述
27
26
25
VDD_DIFF
1
24 VDD_DIFF
OE_DIFF21
2
23 DIFF5
SSON2
3
OE_DIFF31
4
22 DIFF5
21 VDD_DIFF
33
GND
OE_DIFF41
5
OE_DIFF51
6
19 DIFF4
NC
7
18
VDD_DIFF
8
17 DIFF3
20
DIFF4
XIN/CLKIN
DIFF1
DIFF4
10
11
12
13
14
15
16
VDD_DIFF
DIFF2
DIFF2
VDD_DIFF
DIFF3
9
DIFF1
DIFF2
DIFF1
Divider
DIFF0
PLL1
(SSC)
DIFF0
XOUT
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
DIFF3
专利申请中
DIFF5
SCLK
SDATA
Control & Memory
CKPWRGD/PDB
Control
RAM
OE [5:0]
SSON
修订版 1.2 2/14
版权所有 © 2014 Silicon Laboratories
Si52146
Si52146
2
??? 1.2
Si52146
目录
章节
页码
1. 电气规格 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. 功能描述 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. 晶体建议 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. CKPWRGD/PDB (掉电)引脚 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3. PDB (掉电)断言 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.4. PDB 无效置位 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.5. OE 引脚 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.6. OE 断言 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.7. OE 无效置位 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.8. SSON 引脚 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. 测试和测量设置 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. 控制寄存器 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1. I2C 接口 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. 数据协议 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. 引脚描述:32 引脚 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. 订购指南 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7. 封装外形 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
文档修改列表 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
联系信息 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
??? 1.2
3
Si52146
1. 电气规格
Table 1. DC Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
3.3 V Operating Voltage
VDD core
3.3 ±5%
3.135
3.3
3.465
V
3.3 V Input High Voltage
VIH
Control input pins
2.0
—
VDD + 0.3
V
3.3 V Input Low Voltage
VIL
Control input pins
VSS – 0.3
—
0.8
V
Input High Voltage
VIHI2C
SDATA, SCLK
2.2
—
—
V
Input Low Voltage
VILI2C
SDATA, SCLK
—
—
1.0
V
Input High Leakage Current
IIH
Except internal pull-down
resistors, 0 < VIN < VDD
—
—
5
A
Input Low Leakage Current
IIL
Except internal pull-up
resistors, 0 < VIN < VDD
–5
—
—
A
High-impedance Output
Current
IOZ
–10
—
10
A
Input Pin Capacitance
CIN
1.5
—
5
pF
COUT
—
—
6
pF
LIN
—
—
7
nH
Power Down Current
IDD_PD
—
—
1
mA
Dynamic Supply Current
IDD_3.3V
—
—
60
mA
Output Pin Capacitance
Pin Inductance
4
All outputs enabled.
Differential clocks with 5”
traces and 2 pF load.
??? 1.2
Si52146
Table 2. AC Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
LACC
Measured at VDD/2 differential
—
—
250
ppm
TDC
Measured at VDD/2
47
—
53
%
CLKIN Rise and Fall Times
TR/TF
Measured between 0.2 VDD and
0.8 VDD
0.5
—
4.0
V/ns
CLKIN Cycle to Cycle Jitter
TCCJ
Measured at VDD/2
—
—
250
ps
CLKIN Long Term Jitter
TLTJ
Measured at VDD/2
—
—
350
ps
Input High Voltage
VIH
XIN/CLKIN pin
2
—
VDD+0.3
V
Input Low Voltage
VIL
XIN/CLKIN pin
—
—
0.8
V
Input High Current
IIH
XIN/CLKIN pin, VIN = VDD
—
—
35
uA
Input Low Current
IIL
XIN/CLKIN pin, 0 < VIN <0.8
–35
—
—
uA
TDC
Measured at 0 V differential
45
—
55
%
TSKEW
Measured at 0 V differential
—
—
800
ps
DIFF Cycle to Cycle Jitter
TCCJ
Measured at 0 V differential
—
35
50
ps
PCIe Gen 1 Pk-Pk
Pk-Pk
PCIe Gen 1
0
30
50
ps
PCIe Gen 2 Phase Jitter
RMSGEN2
10 kHz < F < 1.5 MHz
0
1.75
2.1
ps
PCIe Gen 2 Phase Jitter
RMSGEN2
1.5 MHz < F < Nyquist
0
1.75
2.0
ps
PCIe Gen 3 Phase Jitter
RMSGEN3
Includes PLL BW 2–4 MHz,
CDR = 10 MHz)
0
0.5
0.6
ps
Long Term Accuracy
LACC
Measured at 0 V differential
—
—
100
ppm
Rising/Falling Slew Rate
TR/TF
Measured differentially from
±150 mV
1
—
8
V/ns
Voltage High
VHIGH
—
—
1.15
V
Voltage Low
VLOW
–0.3
—
—
V
VOX
300
—
550
mV
—
–0.5
—
%
Crystal
Long-term Accuracy
Clock Input
CLKIN Duty Cycle
DIFF at 0.7 V
Duty Cycle
Output-to-Output skew
Crossing Point Voltage at
0.7 V Swing
Spread Range
SPR-2
Down spread
Modulation Frequency
FMOD
30
31.5
33
kHz
Clock Stabilization from
Power-up
TSTABLE
—
—
1.8
ms
Stopclock Set-up Time
TSS
10.0
—
—
ns
Enable/Disable and Setup
Note: Visit www.pcisig.com for complete PCIe specifications.
??? 1.2
5
Si52146
Table 3. Absolute Maximum Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD_3.3V
Functional
—
—
4.6
V
Input Voltage
VIN
Relative to VSS
–0.5
—
4.6
VDC
Temperature, Storage
TS
Non-functional
–65
—
150
°C
Temperature, Operating Ambient
TA
Functional
–40
—
85
°C
Temperature, Junction
TJ
Functional
—
—
150
°C
Dissipation, Junction to Case
ØJC
JEDEC (JESD 51)
—
—
17
°C/W
Dissipation, Junction to Ambient
ØJA
JEDEC (JESD 51)
—
—
35
°C/W
ESDHBM
JEDEC (JESD 22-A114)
2000
—
—
V
UL-94
UL (Class)
Main Supply Voltage
ESD Protection (Human Body Model)
Flammability Rating
V–0
Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up.
Power supply sequencing is not required.
6
??? 1.2
Si52146
2. 功能描述
2.1. 晶体建议
如果使用晶体输入,则设备需要并联谐振 25 MHz 晶体。
Table 4. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
25 MHz
AT
Parallel
12–15 pF
Shunt
Cap (max)
Motional
(max)
Tolerance
(max)
Stability
(max)
Aging
(max)
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
2.1.1. 晶体负载
晶体负载是实现低 ppm 性能的关键。为实现低 / 零 ppm 错误,请使用第 2.1.2 节中的计算估计合适的电容性负载
(CL)。
图 1 显示的是使用两个微调电容的典型晶体结构。请注意微调电容与晶体是串联的。
Figure 1. Crystal Capacitive Clarification
2.1.2. 计算负载电容
除标准外部微调电容外,还可考虑使用走线电容和引脚电容正确地计算晶体负载。每一侧的电容都是与晶体串联的。
两侧总电容是晶体负载电容 (CL) 上标示的两倍。计算后的微调电容用于使两侧的电容负载相等。
Figure 2. Crystal Loading Example
使用以下公式为 Ce1 和 Ce2 计算微调电容值。
??? 1.2
7
Si52146
Load Capacitance (each side)
Ce = 2 x CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe





=
1
1
( Ce1 + Cs1
+ Ci1 +
1
Ce2 + Cs2 + Ci2
)
CL: 晶体负载电容
CLe: 从晶体来看使用标准值微调电容时的实际负载
Ce: 外部微调电容
Cs: 杂散电容 (阶梯)
Ci : 内部电容 (引线框架、接合线等)
2.2. CKPWRGD/PDB (掉电)引脚
CKPWRGD/PDB 引脚是双功能引脚。初次加电时,引脚作为 CKPWRGD 引脚使用。初次加电后,若 CKPWRGD
引脚电位低,则输出将被禁用,但晶体振荡器和 I2C 逻辑将激活。 CKPWRGD 引脚由时钟芯片采样为高时,引脚发
挥 PDB 功能。引脚发挥 PDB 功能且被拉低时,设备将进入掉电模式。 CKPWRGD/PDB 引脚虽然有一个内置
100 k 电阻,但仍需要随时处于驱动状态。
2.3. PDB (掉电)断言
PDB 引脚是用于以无干扰的方式禁用所有输出时钟的异步低电平输入。掉电模式下所有输出均将被拉低。在掉电模
式下,所有输出、晶体振荡器以及 I2C 逻辑都将被禁用。
2.4. PDB 无效置位
CKPWRGD/PDB 引脚上应用有效上升沿时,将在两到六个输出时钟周期内以无干扰方式启用所有输出。
2.5. OE 引脚
OE 引脚是用于启用和禁用输出时钟的有效高输入。要启用输出时钟, OE 引脚和 I2C OE 位应为逻辑高。默认情况
下, OE 引脚和 I2C OE 位即设置为逻辑高。有两种禁用输出时钟的方法:将 OE 拉到逻辑低,或将 I2C OE 位设置
为逻辑低。 OE 引脚虽然有一个内置 100 k 电阻,但仍需要随时处于驱动状态。
2.6. OE 断言
OE 引脚是用于分别同步停止和开始输出时钟而其他时钟发生器持续发生作用时的有效高输入。OE 断言功能是通过
将 OE 引脚和 I2C OE 位拉高使各个停止的输入恢复正常运行实现的。时钟恢复时不会产生短时或延长的时钟脉冲。
从断言到有效输出的最高延迟不超过二到六个输出时钟周期。
2.7. OE 无效置位
OE 功能是通过将引脚或 I2C OE 位设置为逻辑低实现的。相应的输出将完全停止且最终输出状态被拉为低。
2.8. SSON 引脚
SSON 是用于在输出上启用 –0.5% 扩频的有效输入。采样高时,输出时钟上即启用
–0.5% 扩频。采样低时,输出时钟不扩频。
8
??? 1.2
Si52146
3. 测试和测量设置
图 3 显示 HCSL 兼容时钟输出的测试负载配置。
M e a s u re m e n t
P o in t
L1
O U T+
5 0
2 pF
L1 = 5"
M e a s u re m e n t
P o in t
L1
O U T-
5 0
2 pF
Figure 3. 0.7 V Differential Load Configuration
关于如何终止 LVDS、 LVPECL 或 CML 信号水平的差分输出的建议,请见应用注释 AN781。
Figure 4. Differential Output Signals (for AC Parameters Measurement)
??? 1.2
9
Si52146
VMIN = –0.30V
VMIN = –0.30V
Figure 5. Single-ended Measurement for Differential Output Signals
(for AC Parameters Measurement)
10
??? 1.2
Si52146
4. 控制寄存器
4.1. I2C 接口
为提高时钟合成器的灵活性和功能,可使用 I2C 接口。通过 I2C 接口可使用各种设备功能,如启用单个时钟输出。
I2C 接口相关的寄存器在加电时初始化为默认设置。此接口的使用是可选的。若需要更改时钟寄存器,则这种更改通
常是在系统初始化时进行的。
4.2. 数据协议
时钟驱动器 I2C 协议可接受控制器的写字节、读字节、写块和读块操作。写 / 读块操作是从最低到最高按顺序访问各
字节 (从最高有效位开始) ,并有在传输完任何完整字节后停止的能力。对于写字节和读字节操作,系统控制器可
访问独立索引的字节。 .
写块和读块协议请见 表 5,写字节和读字节协议请见 表 6。从接收器地址为 11010110 (D6h)。
Table 5. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
Block Read Protocol
Description
Bit
1
Start
8:2
Slave address—7 bits
Description
Start
Slave address—7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code—8 bits
18:11
19
Acknowledge from slave
19
Acknowledge from slave
Byte Count—8 bits
20
Repeat start
27:20
28
36:29
37
45:38
Acknowledge from slave
27:21
Command Code–8 bits
Slave address—7 bits
Data byte 1–8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 2–8 bits
46
Acknowledge from slave
....
Data Byte/Slave Acknowledges
....
Data Byte N–8 bits
....
Acknowledge from slave
....
Stop
37:30
38
46:39
47
55:48
??? 1.2
Byte Count from slave—8 bits
Acknowledge
Data byte 1 from slave—8 bits
Acknowledge
Data byte 2 from slave—8 bits
56
Acknowledge
....
Data bytes from slave/Acknowledge
....
Data Byte N from slave—8 bits
....
NOT Acknowledge
....
Stop
11
Si52146
Table 6. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
Byte Read Protocol
Description
Bit
Start
1
Slave address–7 bits
8:2
Start
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
19
27:20
Command Code–8 bits
18:11
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Data byte–8 bits
20
Repeated start
28
Acknowledge from slave
29
Stop
27:21
??? 1.2
Slave address–7 bits
28
Read
29
Acknowledge from slave
37:30
12
Description
Data from slave–8 bits
38
NOT Acknowledge
39
Stop
Si52146
Control Register 0. Byte 0
Bit
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D2
D1
D0
Name
Type
重置设置 = 00000000
Bit
Name
Function
7:0
Reserved
Register 1. Byte 1
Bit
D7
D6
D5
Name
Type
D4
D3
DIFF0_OE
R/W
R/W
R/W
R/W
DIFF1_OE
R/W
R/W
DIFF2_OE
R/W
R/W
重置设置 = 00010101
Bit
Name
7:5
Reserved
4
DIFF0_OE
Function
Output Enable for DIFF0.
0: Output disabled.
1: Output Enabled.
3
Reserved
2
DIFF1_OE
Output Enable for DIFF1.
0: Output disabled.
1: Output enabled.
1
Reserved
0
DIFF2_OE
Output Enable for DIFF2.
0: Output disabled.
1: Output enabled.
??? 1.2
13
Si52146
Register 2. Byte 2
Bit
D7
D6
D5
Name
DIFF3_OE
DIFF4_OE
DIFF5_OE
Type
R/W
R/W
R/W
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
D2
D1
D0
重置设置 = 11100000
Bit
Name
Function
7
DIFF3_OE
Output Enable for DIFF3.
0: Output disabled.
1: Output enabled.
6
DIFF4_OE
Output Enable for DIFF4.
0: Output disabled.
1: Output enabled.
5
DIFF5_OE
Output Enable for DIFF5.
0: Output disabled.
1: Output enabled.
4:0
Reserved
Register 3. Byte 3
Bit
D7
D6
Name
Type
D5
D4
D3
Rev Code[3:0]
R/W
R/W
R/W
Vendor ID[3:0]
R/W
R/W
重置设置 = 00001000
14
Bit
Name
Function
7:4
Rev Code[3:0]
Program Revision Code.
3:0
Vendor ID[3:0]
Vendor Identification Code.
??? 1.2
R/W
R/W
R/W
Si52146
Register 4. Byte 4
Bit
D7
D6
D5
D4
Name
Type
D3
D2
D1
D0
R/W
R/W
R/W
R/W
BC[7:0]
R/W
R/W
R/W
R/W
重置设置 = 00000110
Bit
Name
7:0
BC[7:0]
Function
Byte Count Register.
Register 5. Byte 5
Bit
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0]
Type
R/W
R/W
R/W
R/W
重置设置 = 11011000
Bit
Name
7
DIFF_Amp_Sel
6
DIFF_Amp_Cntl[2]
5
DIFF_Amp_Cntl[1]
4
DIFF_Amp_Cntl[0]
3:0
Reserved
Function
Amplitude Control for DIFF Differential Outputs.
0: Differential outputs with Default amplitude.
1: Differential outputs amplitude is set by Byte 5[6:4].
DIFF Differential Outputs Amplitude Adjustment.
000: 300 mV 001: 400 mV 010: 500 mV 011: 600 mV
100: 700 mV 101: 800 mV 110: 900 mV 111: 1000 mV
??? 1.2
15
Si52146
SDATA
SCLK
29
CKPWRGD/PDB1
30
VDD_CORE
31
XOUT
OE_DIFF01
32
XIN/CLKIN
OE_DIFF11
5. 引脚描述:32 引脚 QFN
28
27
26
25
VDD_DIFF
1
24 VDD_DIFF
OE_DIFF21
2
23 DIFF5
SSON 2
3
22 DIFF5
OE_DIFF31
4
OE_DIFF41
5
OE_DIFF51
6
19 DIFF4
NC
7
18
VDD_DIFF
8
17 DIFF3
21 VDD_DIFF
33
GND
9
10
11
12
13
14
15
16
DIFF0
DIFF0
DIFF1
DIFF1
VDD_DIFF
DIFF2
DIFF2
VDD_DIFF
20
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
DIFF4
DIFF3
Table 7. Si52146 32-Pin QFN Descriptions
Pin #
Name
1
VDD_DIFF
PWR 3.3 V power supply
2
OE_DIFF2
I,PU
Active high input pin enables DIFF2 (internal 100 k pull-up).
3
SSON
I, PD
Active high input pin enables –0.5% spread on DIFF clocks
(internal 100 k pull-down)
4
OE_DIFF3
I,PU
Active high input pin enables DIFF3 (internal 100 k pull-up).
5
OE_DIFF4
I,PU
Active high input pin enables DIFF4 (internal 100 k pull-up).
6
OE_DIFF5
I,PU
Active high input pin enables DIFF5 (internal 100 k pull-up).
7
NC
NC
No connect
8
VDD_DIFF
9
DIFF0
O, DIF 0.7 V, 100 MHz differential clock output
10
DIFF0
O, DIF 0.7 V, 100 MHz differential clock output
11
DIFF1
O, DIF 0.7 V, 100 MHz differential clock output
12
DIFF1
O, DIF 0.7 V, 100 MHz differential clock output
16
Type
Description
PWR 3.3 V power supply
??? 1.2
Si52146
Table 7. Si52146 32-Pin QFN Descriptions (Continued)
Pin #
Name
Type
Description
13
VDD_DIFF
14
DIFF2
O, DIF 0.7 V, 100 MHz differential clock output
15
DIFF2
O, DIF 0.7 V, 100 MHz differential clock output
16
VDD_DIFF
17
DIFF3
O, DIF 0.7 V, 100 MHz differential clock output
18
DIFF3
O, DIF 0.7 V, 100 MHz differential clock output
19
DIFF4
O, DIF 0.7 V, 100 MHz differential clock output
20
DIFF4
O, DIF 0.7 V, 100 MHz differential clock output
21
VDD_DIFF
22
DIFF5
O, DIF 0.7 V, 100 MHz differential clock output
23
DIFF5
O, DIF 0.7 V, 100 MHz differential clock output
24
VDD_DIFF
25
SCLK
I
26
SDATA
I/O
27
CKPWRGD/PDB
I, PU
28
VDD_CORE
29
XOUT
O
25.00 MHz crystal output, Float XOUT if using only CLKIN (clock input)
30
XIN/CLKIN
I
25.00 MHz crystal input or 3.3 V, 25 MHz clock input
31
OE_DIFF0
I,PU
Active high input pin enables DIFF0 (internal 100 k pull-up).
32
OE_DIFF1
I,PU
Active high input pin enables DIFF1 (internal 100 k pull-up).
33
GND
GND
Ground for bottom pad of the IC.
PWR 3.3 V power supply
PWR 3.3 V power supply
PWR 3.3 V power supply
PWR 3.3 V power supply
I2C compatible SCLOCK
I2C compatible SDATA
Active low input for asserting power down (PDB) and disabling all
outputs (internal 100 k pull-up).
PWR 3.3 V power supply
??? 1.2
17
Si52146
6. 订购指南
Part Number
Package Type
Temperature
Si52146-A01AGM
32-pin QFN
Industrial, –40 to 85 C
Si52146-A01AGMR
32-pin QFN—Tape and Reel
Industrial, –40 to 85 C
Lead-free
18
??? 1.2
Si52146
7. 封装外形
图 6 说明 Si52146 的封装详细信息。表 8 列出插图中的尺寸值。
Figure 6. 32-Pin Quad Flat No Lead (QFN) Package
Table 8. Package Diagram Dimensions
Symbol
A
A1
b
D
D2
e
E
E2
L
aaa
bbb
ccc
ddd
Millimeters
Min
Nom
Max
0.70
0.00
0.18
0.75
0.02
0.25
5.00 BSC
3.20
0.50 BSC
5.00 BSC
3.20
0.40
0.10
0.10
0.08
0.10
0.80
0.05
0.30
3.15
3.15
0.30
3.25
3.25
0.50
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
4. This drawing conforms to the JEDEC Solid State Outline MO-220.
??? 1.2
19
Si52146
文档修改列表
修订版 0.1 至修订版 1.0









更新引脚名称。
更新表 1。
更新表 2。
更新表 3。
更新第 2.1 节。
更新第 2.1.1 节。
更新第 2.2-2.8 节。
更新第 4.2 节。
更新表 7。
修订版 1.0 至修订版 1.1

从表 3 删除了湿敏度规格。
修订版 1.1 至修订版 1.2


20
更新了表 2。
更新了第 3 节。
??? 1.2
Si52146
注意:
??? 1.2
21
ClockBuilder Pro
One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
www.silabs.com/CBPro
Timing Portfolio
www.silabs.com/timing
SW/HW
Quality
Support and Community
www.silabs.com/CBPro
www.silabs.com/quality
community.silabs.com
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations
thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®,
USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of
ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
http://www.silabs.com