Si52146

Si52146
P C I - E X P R E S S G E N 1 , G E N 2, G E N 3 , & G EN 4 S IX O U T P U T
CLOCK GENERATOR
Features








PCI-Express Gen 1, Gen 2, Gen 3,
and Gen 4 common clock compliant
Gen 3 SRNS Compliant
Supports Serial-ATA (SATA) at
100 MHz
Low power push-pull HCSL
compatible differential outputs
No termination resistors required
Dedicated output enable pins for
each clock
Pin selectable spread control
Up to six PCI-Express clock outputs

25 MHz crystal input or clock input

I2C support with readback
capabilities
Triangular spread spectrum profile
for maximum electromagnetic
interference (EMI) reduction
Industrial temperature:
–40 to 85 °C
3.3 V Power supply
32-pin QFN package




Ordering Information:
See page 18
Applications
Wireless access point
Switches
SCLK
28
CKPWRGD/PDB1
29
27
26
25
1
24 VDD_DIFF
OE_DIFF21
2
23 DIFF5
SSON2
3
22 DIFF5
OE_DIFF31
4
OE_DIFF41
5
OE_DIFF51
6
19 DIFF4
NC
7
18
VDD_DIFF
8
17 DIFF3
21 VDD_DIFF
33
GND
10
11
12
13
14
15
16
VDD_DIFF
DIFF2
DIFF2
VDD_DIFF
20
9
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Functional Block Diagram
30
SDATA
31
VDD_CORE
32
VDD_DIFF
DIFF1
The Si52146 is a high-performance, PCIe clock generator that can source six
PCIe clocks from a 25 MHz crystal or clock input. The clock outputs are
compliant to PCIe Gen 1, Gen 2, Gen 3, Gen 3 SRNS and Gen 4 common
clock specifications. The device has six output enable control pins for
enabling and disabling differential outputs. A spread spectrum control pin for
EMI reduction is also available. The small footprint and low power
consumption makes the Si52146 the ideal clock solution for consumer and
embedded applications. Measuring PCIe clock jitter is quick and easy with the
Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/
pcie-learningcenter.
XOUT
Description
XIN/CLKIN
Pin Assignments
OE_DIFF01

DIFF1

DIFF0
Network attached storage
Multi-function printer
OE_DIFF11

DIFF0

DIFF4
DIFF3
Patents pending
DIFF0
XIN/CLKIN
DIFF1
XOUT
PLL1
(SSC)
Divider
DIFF2
DIFF3
DIFF4
DIFF5
SCLK
SDATA
Control & Memory
CKPWRGD/PDB
Control
RAM
OE [5:0]
SSON
Rev. 1.4 4/16
Copyright © 2016 by Silicon Laboratories
Si52146
Si52146
2
Rev. 1.4
Si52146
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. CKPWRGD/PDB (Power Down) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3. PDB (Power Down) Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.4. PDB Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.5. OE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.6. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.7. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.8. SSON Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5. Pin Descriptions: 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Rev. 1.4
3
Si52146
1. Electrical Specifications
Table 1. DC Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
3.3 V Operating Voltage
VDD core
3.3 ±5%
3.135
3.3
3.465
V
3.3 V Input High Voltage
VIH
Control input pins
2.0
—
VDD + 0.3
V
3.3 V Input Low Voltage
VIL
Control input pins
VSS – 0.3
—
0.8
V
Input High Voltage
VIHI2C
SDATA, SCLK
2.2
—
—
V
Input Low Voltage
VILI2C
SDATA, SCLK
—
—
1.0
V
Input High Leakage Current
IIH
Except internal pull-down
resistors, 0 < VIN < VDD
—
—
5
A
Input Low Leakage Current
IIL
Except internal pull-up
resistors, 0 < VIN < VDD
–5
—
—
A
High-impedance Output
Current
IOZ
–10
—
10
A
Input Pin Capacitance
CIN
1.5
—
5
pF
COUT
—
—
6
pF
LIN
—
—
7
nH
Power Down Current
IDD_PD
—
—
1
mA
Dynamic Supply Current
IDD_3.3V
—
—
60
mA
Output Pin Capacitance
Pin Inductance
4
All outputs enabled. Differential clocks with 5” traces
and 2 pF load.
Rev. 1.4
Si52146
Table 2. AC Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
LACC
Measured at VDD/2 differential
—
—
250
ppm
TDC
Measured at VDD/2
47
—
53
%
CLKIN Rise and Fall Times
TR/TF
Measured between 0.2 VDD and
0.8 VDD
0.5
—
4.0
V/ns
CLKIN Cycle to Cycle Jitter
TCCJ
Measured at VDD/2
—
—
250
ps
CLKIN Long Term Jitter
TLTJ
Measured at VDD/2
—
—
350
ps
Input High Voltage
VIH
XIN/CLKIN pin
2
—
VDD+0.3
V
Input Low Voltage
VIL
XIN/CLKIN pin
—
—
0.8
V
Input High Current
IIH
XIN/CLKIN pin, VIN = VDD
—
—
35
uA
Input Low Current
IIL
XIN/CLKIN pin, 0 < VIN <0.8
–35
—
—
uA
TDC
Measured at 0 V differential
45
—
55
%
TSKEW
Measured at 0 V differential
—
—
800
ps
DIFF Cycle to Cycle Jitter
TCCJ
Measured at 0 V differential
—
35
50
ps
PCIe Gen 1 Pk-Pk,
Common Clock
Pk-Pk
PCIe Gen 1
0
30
50
ps
PCIe Gen 2 Phase Jitter,
Common Clock
RMSGEN2
10 kHz < F < 1.5 MHz
0
1.75
2.1
ps
PCIe Gen 2 Phase Jitter,
Common Clock
RMSGEN2
1.5 MHz < F < Nyquist
0
1.75
2.0
ps
PCIe Gen 3 Phase Jitter,
Common Clock
RMSGEN3
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
0
0.5
0.6
ps
PCIe Gen 3 Phase Jitter,
Separate Reference No
Spread, SRNS
RMSGEN3_SRNS
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
—
0.35
0.42
ps
PCIe Gen 4 Phase Jitter,
Common Clock
RMSGEN4
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
—
0.5
0.6
ps
Long Term Accuracy
LACC
Measured at 0 V differential
—
—
100
ppm
Rising/Falling Slew Rate
TR/TF
Measured differentially from
±150 mV
1
—
8
V/ns
Voltage High
VHIGH
—
—
1.15
V
Voltage Low
VLOW
–0.3
—
—
V
VOX
300
—
550
mV
—
–0.5
—
%
Crystal
Long-term Accuracy
Clock Input
CLKIN Duty Cycle
DIFF at 0.7 V
Duty Cycle
Output-to-Output skew
Crossing Point Voltage at
0.7 V Swing
Spread Range
SPR-2
Down spread
Notes:
1. Visit www.pcisig.com for complete PCIe specifications.
2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Rev. 1.4
5
Si52146
Table 2. AC Electrical Specifications (Continued)
Parameter
Symbol
Modulation Frequency
Test Condition
FMOD
Min
Typ
Max
Unit
30
31.5
33
kHz
—
—
1.8
ms
10.0
—
—
ns
Enable/Disable and Setup
Clock Stabilization from
Power-up
TSTABLE
Stopclock Set-up Time
TSS
Measured from the point both VDD
and clock input are valid
Notes:
1. Visit www.pcisig.com for complete PCIe specifications.
2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Table 3. Absolute Maximum Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD_3.3V
Functional
—
—
4.6
V
Input Voltage
VIN
Relative to VSS
–0.5
—
4.6
VDC
Temperature, Storage
TS
Non-functional
–65
—
150
°C
Temperature, Operating Ambient
TA
Functional
–40
—
85
°C
Temperature, Junction
TJ
Functional
—
—
150
°C
Dissipation, Junction to Case
ØJC
JEDEC (JESD 51)
—
—
17
°C/W
Dissipation, Junction to Ambient
ØJA
JEDEC (JESD 51)
—
—
35
°C/W
ESDHBM
JEDEC (JESD 22-A114)
2000
—
—
V
UL-94
UL (Class)
Main Supply Voltage
ESD Protection (Human Body Model)
Flammability Rating
V–0
Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power
supply sequencing is not required.
6
Rev. 1.4
Si52146
2. Functional Description
2.1. Crystal Recommendations
If using crystal input, the device requires a parallel resonance 25 MHz crystal.
Table 4. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
25 MHz
AT
Parallel
12–15 pF
Shunt
Cap (max)
Motional
(max)
Tolerance
(max)
Stability
(max)
Aging
(max)
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
2.1.1. Crystal Loading
Crystal loading is critical in achieving low ppm performance. In order to achieve low zero ppm error, use the
calculations in section 2.1.2 to estimate the appropriate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two trim capacitors. It is important that the trim capacitors
are in series with the crystal.
Figure 1. Crystal Capacitive Clarification
2.1.2. Calculating Load Capacitors
In addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate
the crystal loading correctly. The capacitance on each side is in series with the crystal. The total capacitance on
both sides is twice the specified crystal load capacitance (CL). Trim capacitors are calculated to provide equal
capacitive loading on both sides.
Figure 2. Crystal Loading Example
Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2.
Rev. 1.4
7
Si52146
Load Capacitance (each side)
Ce = 2 x CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe
=
1
1
( Ce1 + Cs1
+ Ci1 +
1
Ce2 + Cs2 + Ci2
)
CL:
Crystal load capacitance
CLe: Actual loading seen by crystal using standard value trim capacitors
Ce: External trim capacitors
Cs: Stray capacitance (terraced)
Ci : Internal capacitance (lead frame, bond wires, etc.)
2.2. CKPWRGD/PDB (Power Down) Pin
The CKPWRGD/PDB pin is a dual-function pin. During initial power up, the pin functions as the CKPWRGD pin.
Upon the first power up, if the CKPWRGD pin is low, the outputs will be disabled, but the crystal oscillator and I2C
logics will be active. Once the CKPWRGD pin has been sampled high by the clock chip, the pin assumes a PDB
functionality. When the pin has assumed a PDB functionality and is pulled low, the device will be placed in power
down mode. The CKPWRGD/PDB pin is required to be driven at all times even though it has an internal 100 k
resistor.
2.3. PDB (Power Down) Assertion
The PDB pin is an asynchronous active low input used to disable all output clocks in a glitch-free manner. All
outputs will be driven low in power down mode. In power down mode, all outputs, the crystal oscillator, and the I2C
logic are disabled.
2.4. PDB Deassertion
When a valid rising edge on CKPWRGD/PDB pin is applied, all outputs are enabled in a glitch-free manner within
two to six output clock cycles.
2.5. OE Pin
The OE pin is an active high input used to enable and disable the output clock. To enable the output clock, the OE
pin and the I2C OE bit need to be a logic high. By default, the OE pin and the I2C OE bit are set to a logic high.
There are two methods to disable the output clock: the OE pin is pulled to a logic low, or the I2C OE bit is set to a
logic low. The OE pin is required to be driven at all times even though it has an internal 100 k resistor.
2.6. OE Assertion
The OE pin is an active high input used for synchronous stopping and starting the respective output clock while the
rest of the clock generator continues to function. The assertion of the OE function is achieved by pulling the OE pin
and the I2C OE bit high which causes the respective stopped output to resume normal operation. No short or
stretched clock pulses are produced when the clocks resume. The maximum latency from the assertion to active
outputs is no more than two to six output clock cycles.
2.7. OE Deassertion
The OE function is deasserted by pulling the pin or the I2C OE bit to a logic low. The corresponding output is
stopped cleanly and the final output state is driven low.
2.8. SSON Pin
The SSON pin is an active input used to enable –0.5% spread spectrum on the outputs. When sampled high,
–0.5% spread is enabled on the output clocks. When sampled low, the output clocks are non-spread.
8
Rev. 1.4
Si52146
3. Test and Measurement Setup
Figure 3 shows the test load configuration for the HCSL compatible clock outputs.
M e a s u re m e n t
P o in t
L1
O U T+
5 0
2 pF
L1 = 5"
M e a s u re m e n t
P o in t
L1
O U T-
5 0
2 pF
Figure 3. 0.7 V Differential Load Configuration
Please reference application note AN781 for recommendations on how to terminate the differential outputs for
LVDS, LVPECL, or CML signalling levels.
Figure 4. Differential Output Signals (for AC Parameters Measurement)
Rev. 1.4
9
Si52146
VMIN = –0.30V
VMIN = –0.30V
Figure 5. Single-ended Measurement for Differential Output Signals
(for AC Parameters Measurement)
10
Rev. 1.4
Si52146
4. Control Registers
4.1. I2C Interface
To enhance the flexibility and function of the clock synthesizer, an I2C interface is provided. Through the I2C
interface, various device functions are available, such as individual clock output enablement. The registers
associated with the I2C interface initialize to their default setting at power-up. The use of this interface is optional.
Clock device register changes are normally made at system initialization, if any are required.
4.2. Data Protocol
The clock driver I2C protocol accepts byte write, byte read, block write, and block read operations from the
controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most
significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read
operations, the system controller can access individually indexed bytes. .
The block write and block read protocol is outlined in Table 5 while Table 6 outlines byte write and byte read
protocol. The slave receiver address is 11010110 (D6h).
Table 5. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
Block Read Protocol
Description
Bit
Start
1
Slave address—7 bits
8:2
Description
Start
Slave address—7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code—8 bits
18:11
19
Acknowledge from slave
19
Acknowledge from slave
Byte Count—8 bits
20
Repeat start
27:20
28
36:29
37
45:38
Acknowledge from slave
27:21
Command Code–8 bits
Slave address—7 bits
Data byte 1–8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 2–8 bits
46
Acknowledge from slave
....
Data Byte/Slave Acknowledges
....
Data Byte N–8 bits
....
Acknowledge from slave
....
Stop
37:30
38
46:39
47
55:48
Rev. 1.4
Byte Count from slave—8 bits
Acknowledge
Data byte 1 from slave—8 bits
Acknowledge
Data byte 2 from slave—8 bits
56
Acknowledge
....
Data bytes from slave/Acknowledge
....
Data Byte N from slave—8 bits
....
NOT Acknowledge
....
Stop
11
Si52146
Table 6. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
Byte Read Protocol
Description
Bit
Start
1
Slave address–7 bits
8:2
Start
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
19
27:20
Command Code–8 bits
18:11
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Data byte–8 bits
20
Repeated start
28
Acknowledge from slave
29
Stop
27:21
Rev. 1.4
Slave address–7 bits
28
Read
29
Acknowledge from slave
37:30
12
Description
Data from slave–8 bits
38
NOT Acknowledge
39
Stop
Si52146
Control Register 0. Byte 0
Bit
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D2
D1
D0
Name
Type
Reset settings = 00000000
Bit
Name
7:0
Reserved
Function
Control Register 1. Byte 1
Bit
D7
D6
D5
Name
Type
D4
D3
DIFF1_OE
DIFF0_OE
R/W
R/W
R/W
R/W
R/W
R/W
DIFF2_OE
R/W
R/W
Reset settings = 00010101
Bit
Name
7:5
Reserved
4
DIFF0_OE
Function
Output Enable for DIFF0.
0: Output disabled.
1: Output Enabled.
3
Reserved
2
DIFF1_OE
Output Enable for DIFF1.
0: Output disabled.
1: Output enabled.
1
Reserved
0
DIFF2_OE
Output Enable for DIFF2.
0: Output disabled.
1: Output enabled.
Rev. 1.4
13
Si52146
Control Register 2. Byte 2
Bit
D7
D6
D5
Name
DIFF3_OE
DIFF4_OE
DIFF5_OE
Type
R/W
R/W
R/W
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
D2
D1
D0
Reset settings = 11100000
Bit
Name
Function
7
DIFF3_OE
Output Enable for DIFF3.
0: Output disabled.
1: Output enabled.
6
DIFF4_OE
Output Enable for DIFF4.
0: Output disabled.
1: Output enabled.
5
DIFF5_OE
Output Enable for DIFF5.
0: Output disabled.
1: Output enabled.
4:0
Reserved
Control Register 3. Byte 3
Bit
D7
D6
Name
Type
D5
D4
D3
Rev Code[3:0]
R/W
R/W
R/W
Vendor ID[3:0]
R/W
R/W
Reset settings = 00001000
14
Bit
Name
Function
7:4
Rev Code[3:0]
Program Revision Code.
3:0
Vendor ID[3:0]
Vendor Identification Code.
Rev. 1.4
R/W
R/W
R/W
Si52146
Control Register 4. Byte 4
Bit
D7
D6
D5
D4
Name
Type
D3
D2
D1
D0
R/W
R/W
R/W
R/W
BC[7:0]
R/W
R/W
R/W
R/W
Reset settings = 00000110
Bit
Name
7:0
BC[7:0]
Function
Byte Count Register.
Control Register 5. Byte 5
Bit
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0]
Type
R/W
R/W
R/W
R/W
Reset settings = 11011000
Bit
Name
7
DIFF_Amp_Sel
Function
Amplitude Control for DIFF Differential Outputs.
0: Differential outputs with Default amplitude.
1: Differential outputs amplitude is set by Byte 5[6:4].
6
DIFF_Amp_Cntl[2]
5
DIFF_Amp_Cntl[1]
4
DIFF_Amp_Cntl[0]
3:0
Reserved
DIFF Differential Outputs Amplitude Adjustment.
000: 300 mV 001: 400 mV 010: 500 mV
100: 700 mV 101: 800 mV 110: 900 mV
Rev. 1.4
011: 600 mV
111: 1000 mV
15
Si52146
SDATA
SCLK
29
CKPWRGD/PDB1
30
VDD_CORE
31
XOUT
OE_DIFF01
32
XIN/CLKIN
OE_DIFF11
5. Pin Descriptions: 32-Pin QFN
28
27
26
25
VDD_DIFF
1
24 VDD_DIFF
OE_DIFF21
2
23 DIFF5
SSON 2
3
22 DIFF5
OE_DIFF31
4
OE_DIFF41
5
OE_DIFF51
6
19 DIFF4
NC
7
18
VDD_DIFF
8
17 DIFF3
21 VDD_DIFF
33
GND
9
10
11
12
13
14
15
16
DIFF0
DIFF0
DIFF1
DIFF1
VDD_DIFF
DIFF2
DIFF2
VDD_DIFF
20
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
DIFF4
DIFF3
Table 7. Si52146 32-Pin QFN Descriptions
Pin #
Name
1
VDD_DIFF
PWR 3.3 V power supply
2
OE_DIFF2
I,PU
Active high input pin enables DIFF2 (internal 100 k pull-up).
3
SSON
I, PD
Active high input pin enables –0.5% spread on DIFF clocks
(internal 100 k pull-down)
4
OE_DIFF3
I,PU
Active high input pin enables DIFF3 (internal 100 k pull-up).
5
OE_DIFF4
I,PU
Active high input pin enables DIFF4 (internal 100 k pull-up).
6
OE_DIFF5
I,PU
Active high input pin enables DIFF5 (internal 100 k pull-up).
7
NC
NC
No connect
8
VDD_DIFF
9
DIFF0
O, DIF 0.7 V, 100 MHz differential clock output
10
DIFF0
O, DIF 0.7 V, 100 MHz differential clock output
11
DIFF1
O, DIF 0.7 V, 100 MHz differential clock output
12
DIFF1
O, DIF 0.7 V, 100 MHz differential clock output
16
Type
Description
PWR 3.3 V power supply
Rev. 1.4
Si52146
Table 7. Si52146 32-Pin QFN Descriptions (Continued)
Pin #
Name
Type
Description
13
VDD_DIFF
14
DIFF2
O, DIF 0.7 V, 100 MHz differential clock output
15
DIFF2
O, DIF 0.7 V, 100 MHz differential clock output
16
VDD_DIFF
17
DIFF3
O, DIF 0.7 V, 100 MHz differential clock output
18
DIFF3
O, DIF 0.7 V, 100 MHz differential clock output
19
DIFF4
O, DIF 0.7 V, 100 MHz differential clock output
20
DIFF4
O, DIF 0.7 V, 100 MHz differential clock output
21
VDD_DIFF
22
DIFF5
O, DIF 0.7 V, 100 MHz differential clock output
23
DIFF5
O, DIF 0.7 V, 100 MHz differential clock output
24
VDD_DIFF
25
SCLK
I
26
SDATA
I/O
27
CKPWRGD/PDB
I, PU
28
VDD_CORE
29
XOUT
O
25.00 MHz crystal output, Float XOUT if using only CLKIN (clock input)
30
XIN/CLKIN
I
25.00 MHz crystal input or 3.3 V, 25 MHz clock input
31
OE_DIFF0
I,PU
Active high input pin enables DIFF0 (internal 100 k pull-up).
32
OE_DIFF1
I,PU
Active high input pin enables DIFF1 (internal 100 k pull-up).
33
GND
GND
Ground for bottom pad of the IC.
PWR 3.3 V power supply
PWR 3.3 V power supply
PWR 3.3 V power supply
PWR 3.3 V power supply
I2C compatible SCLOCK
I2C compatible SDATA
Active low input for asserting power down (PDB) and disabling all
outputs (internal 100 k pull-up).
PWR 3.3 V power supply
Rev. 1.4
17
Si52146
6. Ordering Guide
Part Number
Package Type
Temperature
Si52146-A01AGM
32-pin QFN
Industrial, –40 to 85 C
Si52146-A01AGMR
32-pin QFN—Tape and Reel
Industrial, –40 to 85 C
Lead-free
18
Rev. 1.4
Si52146
7. Package Outline
Figure 6 illustrates the package details for the Si52146. Table 8 lists the values for the dimensions shown in the
illustration.
Figure 6. 32-Pin Quad Flat No Lead (QFN) Package
Table 8. Package Diagram Dimensions
Symbol
A
A1
b
D
D2
e
E
E2
L
aaa
bbb
ccc
ddd
eee
Millimeters
Nom
0.75
0.02
0.25
5.00 BSC
3.20
0.50 BSC
5.00 BSC
3.20
0.40
0.10
0.10
0.08
0.10
0.08
Min
0.70
0.00
0.18
3.15
3.15
0.30
Max
0.80
0.05
0.30
3.25
3.25
0.50
Notes:
4. All dimensions shown are in millimeters (mm) unless otherwise noted.
5. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
6. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
7. This drawing conforms to the JEDEC Solid State Outline MO-220.
Rev. 1.4
19
Si52146
8. Land Pattern
Figure 7. QFN Land Pattern
Table 9. Land Pattern Dimensions
20
Dimension
mm
S1
4.01
S
4.01
L1
3.20
W1
3.20
e
0.50
W
0.26
Rev. 1.4
Si52146
Table 9. Land Pattern Dimensions
L
0.86
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Patter Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to
be 60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 3x3 array of 0.85 mm square openings on a 1.00mm pitch can be used for the center ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Rev. 1.4
21
Si52146
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0









Updated Pin Names.
Updated Table 1.
Updated Table 2.
Updated Table 3.
Updated section 2.1.
Updated section 2.1.1.
Updated sections 2.2 through 2.8.
Updated section 4.2.
Updated Table 7.
Revision 1.0 to Revision 1.1

Removed Moisture Sensitivity Level specification
from Table 3.
Revision 1.1 to Revision 1.2


Updated Table 2.
Updated section 3.
Revision 1.2 to Revision 1.3

Updated Features on page 1
 Updated Description on page 1.
 Updated specs in Table 2, “AC Electrical
Specifications,” on page 5.
 Updated the package outline.
Revision 1.3 to Revision 1.4

22
Added test condition for Tstable in Table 2.
Rev. 1.4