Si52147 PCI-E XPRESS 1 代 、 2 代 和 3 代 九 输 出 时 钟 发 生 器 特点 PCI-Express 1 代、 2 代和 3 代兼容 100 MHz 下支持串行 ATA (SATA) 低功耗推拉式差分输出缓冲器 无需终端电阻 所有时钟的输出使能引脚 扩频使能引脚 25 MHz 晶体输入或时钟输入 最高九个时钟输出 支持 I2C，带逆读功能 使用三角扩频改善图最大程度地减少 电磁干扰 (EMI) 工业温度： –40 至 85 oC 3.3 V 电源 48 引脚 QFN 封装 应用 网络附加存储 多功能打印机 订购信息： 参阅 第 20 页。 无线接入点 服务器 描述 DIFF3 PLL1 (SSC) Divider XIN/CLKIN XOUT SCLK NC SDATA NC 41 VDD_CORE VSS_CORE 42 CKPWRGD/PDB1 NC VSS_DIFF 43 40 39 38 37 36 DIFF8 VDD_DIFF 2 35 DIFF8 OE_DIFF0 3 34 VDD_DIFF OE_DIFF11 4 33 DIFF7 SSON2 5 VSS_DIFF 6 VSS_DIFF 7 OE_DIFF21 8 29 VSS_DIFF OE_DIFF31 9 28 DIFF5 OE_DIFF[4:5]1 10 27 DIFF5 32 DIFF7 31 DIFF6 49 GND 30 DIFF6 26 DIFF4 OE_DIFF[6:8]1 11 25 DIFF4 13 14 15 16 17 18 19 20 21 22 23 24 DIFF2 DIFF2 DIFF3 DIFF3 VDD_DIFF VSS_DIFF 12 DIFF1 VDD_DIFF DIFF1 DIFF2 44 VSS_DIFF XOUT 45 DIFF0 DIFF1 46 DIFF0 XIN/CLKIN 47 1 VDD_DIFF DIFF0 48 VDD_DIFF 1 功能方框图 NC 引脚分配 Si52147 是高性能 PCIe 时钟发生器，可用一个 25 MHz 晶体作为九个 PCIe 时钟的源或时钟输入。时钟输出兼容 PCIe 1 代、 2 代和 3 代规格。 设备有六个用于启用和禁用差分输出的硬件输出使能控制引脚。另还有一 个用于降低 EMI 的扩频控制引脚。 Si52147 的小体积和低功耗使其成为消 费者和嵌入应用的理想解决方案。 Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. DIFF4 DIFF5 专利申请中 DIFF6 SCLK SDATA Control & Memory DIFF7 CKPWRGD/PDB Control OE [8:0] RAM DIFF8 SSON 修订版 1.2 2/14 版权所有 © 2014 Silicon Laboratories Si52147 Si52147 2 ??? 1.2 Si52147 目录 章节 页码 1. 电气规格 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. 功能描述 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. 晶体建议 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. CKPWRGD/PDB （掉电）引脚 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3. PDB （掉电）断言 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.4. PDB 无效置位 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.5. OE 引脚 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.6. OE 断言 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.7. OE 无效置位 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.8. SSON 引脚 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. 测试和测量设置 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. 控制寄存器 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1. I2C 接口 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2. 数据协议 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. 引脚描述：48 引脚 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. 订购指南 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7. 封装外形 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 文档修改列表 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 联系信息 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ??? 1.2 3 Si52147 1. 电气规格 Table 1. DC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit 3.3 V Operating Voltage VDD core 3.3 ±5% 3.135 3.3 3.465 V 3.3 V Input High Voltage VIH Control input pins 2.0 — VDD + 0.3 V 3.3 V Input Low Voltage VIL Control input pins VSS – 0.3 — 0.8 V Input High Voltage VIHI2C SDATA, SCLK 2.2 — — V Input Low Voltage VILI2C SDATA, SCLK — — 1.0 V Input High Leakage Current IIH Except internal pull-down resistors, 0 < VIN < VDD — — 5 A Input Low Leakage Current IIL Except internal pull-up resistors, 0 < VIN < VDD –5 — — A High-impedance Output Current IOZ –10 — 10 A Input Pin Capacitance CIN 1.5 — 5 pF COUT — — 6 pF LIN — — 7 nH Power Down Current IDD_PD — — 1 mA Dynamic Supply Current IDD_3.3V — — 85 mA Output Pin Capacitance Pin Inductance 4 All outputs enabled. Differential clocks with 5” traces and 2 pF load. ??? 1.2 Si52147 Table 2. AC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit LACC Measured at VDD/2 differential — — 250 ppm TDC Measured at VDD/2 47 — 53 % CLKIN Rise and Fall Times TR/TF Measured between 0.2 VDD and 0.8 VDD 0.5 — 4.0 V/ns CLKIN Cycle to Cycle Jitter TCCJ Measured at VDD/2 — — 250 ps CLKIN Long Term Jitter TLTJ Measured at VDD/2 — — 350 ps Input High Voltage VIH XIN/CLKIN pin 2 — VDD+0.3 V Input Low Voltage VIL XIN/CLKIN pin — — 0.8 V Input High Current IIH XIN/CLKIN pin, VIN = VDD — — 35 uA Input Low Current IIL XIN/CLKIN pin, 0 < VIN <0.8 –35 — — uA TDC Measured at 0 V differential 45 — 55 % TSKEW Measured at 0 V differential — — 800 ps Cycle to Cycle Jitter TCCJ Measured at 0 V differential — 35 50 ps PCIe Gen 1 Pk-Pk Jitter Pk-Pk PCIe Gen 1 0 40 50 ps PCIe Gen 2 Phase Jitter RMSGEN2 10 kHz < F < 1.5 MHz 0 1.8 2.0 ps 1.5 MHz < F < Nyquist 0 1.8 2.1 ps RMSGEN3 Includes PLL BW 2–4 MHz, CDR = 10 MHz 0 0.5 0.6 ps Long Term Accuracy LACC Measured at 0 V differential — — 100 ppm Rising/Falling Slew Rate TR/TF Measured differentially from ±150 mV 1 — 8 V/ns Voltage High VHIGH — — 1.15 V Voltage Low VLOW –0.3 — — V VOX 300 — 550 mV — –0.5 — % Crystal Long-term Accuracy Clock Input CLKIN Duty Cycle DIFF at 0.7 V Duty Cycle Output-to-Output skew PCIe Gen 3 Phase Jitter Crossing Point Voltage at 0.7 V Swing Spread Range SPR-2 Down spread Modulation Frequency FMOD 30 31.5 33 kHz Clock Stabilization from Power-up TSTABLE — — 1.8 ms Stopclock Set-up Time TSS 10.0 — — ns Enable/Disable and Setup Note: Visit www.pcisig.com for complete PCIe specifications. ??? 1.2 5 Si52147 Table 3. Absolute Maximum Conditions Parameter Symbol Test Condition Min Typ Max Unit VDD_3.3V Functional — — 4.6 V Input Voltage VIN Relative to VSS –0.5 — 4.6 VDC Temperature, Storage TS Non-functional –65 — 150 °C Temperature, Operating Ambient TA Functional –40 — 85 °C Temperature, Junction TJ Functional — — 150 °C Dissipation, Junction to Case ØJC JEDEC (JESD 51) — — 22 °C/W Dissipation, Junction to Ambient ØJA JEDEC (JESD 51) — — 30 °C/W ESDHBM JEDEC (JESD 22-A114) 2000 — — V UL-94 UL (Class) Main Supply Voltage ESD Protection (Human Body Model) Flammability Rating V–0 Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. 6 ??? 1.2 Si52147 2. 功能描述 2.1. 晶体建议 如果使用晶体输入，则设备需要并联谐振 25 MHz 晶体。 Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap 25 MHz AT Parallel 12–15 pF Shunt Cap (max) Motional (max) Tolerance (max) Stability (max) Aging (max) 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 2.1.1. 晶体负载 晶体负载是实现低 ppm 性能的关键。为实现低 / 零 ppm 错误，请使用第 2.1.2 节中的计算估计合适的电容性负载 (CL)。 图 1 显示的是使用两个微调电容的典型晶体结构。 请注意微调电容与晶体是串联的。 Figure 1. Crystal Capacitive Clarification 2.1.2. 计算负载电容 除标准外部微调电容外，还可考虑使用走线电容和引脚电容正确地计算晶体负载。每一侧的电容都是与晶体串联的。 两侧总电容是晶体负载电容 (CL) 上标示的两倍。 计算后的微调电容用于使两侧的电容负载相等。 Figure 2. Crystal Loading Example 使用以下公式为 Ce1 和 Ce2 计算微调电容值。 ??? 1.2 7 Si52147 Load Capacitance (each side) Ce = 2 x CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL: 晶体负载电容 CLe: 从晶体来看使用标准值微调电容时的实际负载 Ce: 外部微调电容 Cs: 杂散电容 （阶梯） Ci : 内部电容 （引线框架、接合线等） 2.2. CKPWRGD/PDB （掉电）引脚 CKPWRGD/PDB 引脚是双功能引脚。初次加电时，引脚作为 CKPWRGD 引脚使用。初次加电后，若 CKPWRGD 引脚电位低，则输入将被禁用，但晶体振荡器和 I2C 逻辑将激活。 CKPWRGD 引脚由时钟芯片采样为高时，引脚发 挥 PDB 功能。引脚发挥 PDB 功能且被拉低时，设备将进入掉电模式。 CKPWRGD/PDB 引脚虽然有一个内置 100 k 电阻，但仍需要随时处于驱动状态。 2.3. PDB （掉电）断言 PDB 引脚是用于以无干扰的方式禁用所有输出时钟的异步低电平输入。掉电模式下所有输出均将被拉低。在掉电模 式下，所有输出、晶体振荡器以及 I2C 逻辑都将被禁用。 2.4. PDB 无效置位 CKPWRGD/PDB 引脚上应用有效上升沿时，将在两到六个输出时钟周期内以无干扰方式启用所有输出。 2.5. OE 引脚 OE 引脚是用于启用和禁用输出时钟的有效高输入。要启用输出时钟， OE 引脚和 I2C OE 位应为逻辑高。默认情况 下， OE 引脚和 I2C OE 位即设置为逻辑高。有两种禁用输出时钟的方法：将 OE 拉到逻辑低，或将 I2C OE 位设置 为逻辑低。 OE 引脚虽然有一个内置 100 k 电阻，但仍需要随时处于驱动状态。 2.6. OE 断言 OE 引脚是用于分别同步停止和启动输出时钟而其他时钟发生器继续发生作用时的高电平输入。OE 断言功能是通过 将 OE 引脚和 I2C OE 位拉高使各个停止的输入恢复正常运行实现的。时钟恢复时不会产生短时或延长的时钟脉冲。 从断言到有效输出的最高延迟不超过二到六个输出时钟周期。 2.7. OE 无效置位 OE 功能是通过将引脚或 I2C OE 位设置为逻辑低实现的。相应的输出将完全停止且最终输出状态被拉低。 2.8. SSON 引脚 SSON 是用于在输出上启用 –0.5% 扩频的有效输入。采样高时，输出时钟上即启用 –0.5% 扩频。采样低时，输出时 钟不扩频。 8 ??? 1.2 Si52147 3. 测试和测量设置 图 3 显示 HCSL 兼容输出时钟的测试负载配置。 M e a s u re m e n t P o in t L1 O U T+ 5 0 2 pF L1 = 5" M e a s u re m e n t P o in t L1 O U T- 5 0 2 pF Figure 3. 0.7 V Differential Load Configuration 关于如何终止 LVDS、 LVPECL 或 CML 信号水平的差分输出的建议，请见应用注释 AN781。 Figure 4. Differential Output Signals (for AC Parameters Measurement) ??? 1.2 9 Si52147 VMIN = –0.30V VMIN = –0.30V Figure 5. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement) 10 ??? 1.2 Si52147 4. 控制寄存器 4.1. I2C 接口 为提高时钟合成器的灵活性和功能，可使用 I2C 接口。通过 I2C 接口可使用各种设备功能，如启用单个时钟输出。与 I2C 接口相关的寄存器在加电时初始化为默认设置。此接口的使用是可选的。若需要更改时钟寄存器，则这种更改通 常是在系统初始化时进行的。 4.2. 数据协议 时钟驱动器 I2C 协议可接受控制器的写字节、读字节、写块和读块操作。写 / 读块操作是从最低到最高按顺序访问各 字节 （从最高有效位开始） ，并有在传输完任何完整字节后停止的能力。对于写字节和读字节操作，系统控制器可 访问独立索引的字节。 写块和读块协议请见 表 5，写字节和读字节协议请见 表 6。从接收器地址为 11010110 (D6h)。 Table 5. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Block Read Protocol Description Bit 1 Start 8:2 Slave address—7 bits Description Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code—8 bits 18:11 19 Acknowledge from slave 19 Acknowledge from slave Byte Count—8 bits 20 Repeat start 27:20 28 36:29 37 45:38 Acknowledge from slave 27:21 Command Code–8 bits Slave address–7 bits Data byte 1–8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2–8 bits 46 Acknowledge from slave .... Data Byte/Slave Acknowledges .... Data Byte N–8 bits .... Acknowledge from slave .... Stop 37:30 38 46:39 47 55:48 ??? 1.2 Byte Count from slave–8 bits Acknowledge Data byte 1 from slave–8 bits Acknowledge Data byte 2 from slave–8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data Byte N from slave–8 bits .... NOT Acknowledge .... Stop 11 Si52147 Table 6. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Byte Read Protocol Description Bit Start 1 Slave address–7 bits 8:2 Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 Command Code–8 bits 18:11 Command Code–8 bits Acknowledge from slave 19 Acknowledge from slave Data byte–8 bits 20 Repeated start 28 Acknowledge from slave 29 Stop 27:21 ??? 1.2 Slave address–7 bits 28 Read 29 Acknowledge from slave 37:30 12 Description Data from slave–8 bits 38 NOT Acknowledge 39 Stop Si52147 Control Register 0. Byte 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W D2 D1 D0 DIFF1_OE DIFF2_OE DIFF3_OE R/W R/W R/W Name Type 重置设置 = 00000000 Bit Name Function 7:0 Reserved Control Register 1. Byte 1 Bit D7 D6 D5 Name Type D4 D3 DIFF0_OE R/W R/W R/W R/W R/W 重置设置 = 00010111 Bit Name 7:5 Reserved 4 DIFF0_OE 3 Reserved 2 DIFF1_OE Function Output Enable for DIFF0. 0: Output disabled. 1: Output enabled. Output Enable for DIFF1. 0: Output disabled. 1: Output enabled. 1 DIFF2_OE Output Enable for DIFF2. 0: Output disabled. 1: Output enabled. 0 DIFF3_OE Output Enable for DIFF3. 0: Output disabled. 1: Output enabled. ??? 1.2 13 Si52147 Control Register 2. Byte 2 Bit D7 D6 D5 D4 D3 Name DIFF4_OE DIFF5_OE DIFF6_OE DIFF7_OE DIFF8_OE Type R/W R/W R/W R/W R/W 重置设置 = 11111000 14 Bit Name Function 7 DIFF4_OE Output Enable for DIFF4. 0: Output disabled. 1: Output enabled. 6 DIFF5_OE Output Enable for DIFF5. 0: Output disabled. 1: Output enabled. 5 DIFF6_OE Output Enable for DIFF6. 0: Output disabled. 1: Output enabled. 4 DIFF7_OE Output Enable for DIFF7. 0: Output disabled. 1: Output enabled. 3 DIFF8_OE Output Enable for DIFF8. 0: Output disabled. 1: Output enabled. 2:0 Reserved ??? 1.2 D2 D1 D0 R/W R/W R/W Si52147 Control Register 3. Byte 3 Bit D7 D6 Name Type D5 D4 D3 Rev Code[3:0] R/W R/W R/W D2 D1 D0 Vendor ID[3:0] R/W R/W R/W R/W R/W D3 D2 D1 D0 R/W R/W R/W R/W 重置设置 = 00001000 Bit Name Function 7:4 Rev Code[3:0] Program Revision Code. 3:0 Vendor ID[3:0] Vendor Identification Code. Control Register 4. Byte 4 Bit D7 D6 D5 D4 Name Type BC[7:0] R/W R/W R/W R/W 重置设置 = 00000110 Bit Name 7:0 BC[7:0] Function Byte Count Register. ??? 1.2 15 Si52147 Control Register 5. Byte 5 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0] Type R/W R/W R/W R/W 重置设置 = 11011000 Bit Name 7 DIFF_Amp_Sel Function Amplitude Control for DIFF Differential Outputs. 0: Differential outputs with Default amplitude. 1: Differential outputs amplitude is set by Byte 5[6:4]. 16 6 DIFF_Amp_Cntl[2] 5 DIFF_Amp_Cntl[1] 4 DIFF_Amp_Cntl[0] 3:0 Reserved DIFF Differential Outputs Amplitude Adjustment. 000: 300 mV 001: 400 mV 010: 500 mV 011: 600 mV 100: 700 mV 101: 800 mV 110: 900 mV 111: 1000 mV ??? 1.2 Si52147 NC NC VSS_DIFF VSS_CORE NC NC XIN/CLKIN XOUT VDD_CORE CKPWRGD/PDB1 SDATA SCLK 5. 引脚描述：48 引脚 QFN 48 47 46 45 44 43 42 41 40 39 38 37 VDD_DIFF 1 36 DIFF8 VDD_DIFF 2 35 DIFF8 OE_DIFF0 1 3 34 VDD_DIFF OE_DIFF1 1 4 33 DIFF7 SSON 2 5 32 DIFF7 VSS_DIFF 6 31 DIFF6 VSS_DIFF 7 30 DIFF6 OE_DIFF2 1 8 29 VSS_DIFF OE_DIFF3 1 9 28 DIFF5 OE_DIFF[4:5]1 10 27 DIFF5 OE_DIFF[6:8]1 11 26 DIFF4 VDD_DIFF 12 49 GND 17 18 19 20 21 VSS_DIFF DIFF1 DIFF1 DIFF2 DIFF2 DIFF3 22 23 24 VSS_DIFF 16 VDD_DIFF 15 DIFF3 14 DIFF0 VDD_DIFF 13 DIFF0 25 DIFF4 Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. . Table 7. Si 52147 48-Pin QFN Descriptions Pin # Name Type Description 1 VDD_DIFF PWR 3.3 V Power Supply 2 VDD_DIFF PWR 3.3 V Power Supply 3 OE_DIFF0 I,PU Active high input pin enables DIFF0 (internal 100 k pull-up). 4 OE_DIFF1 I,PU Active high input pin enables DIFF1 (internal 100 k pull-up). 5 SSON I, PD Active high input pin enables –0.5% spread on DIFF clocks (internal 100 k pull-down) 6 VSS_DIFF GND Ground 7 VSS_DIFF GND Ground ??? 1.2 17 Si52147 Table 7. Si 52147 48-Pin QFN Descriptions (Continued) Pin # Name Type 8 OE_DIFF2 I,PU Active high input pin enables DIFF2 (internal 100 k pull-up). 9 OE_DIFF3 I,PU Active high input pin enables DIFF3 (internal 100 k pull-up). 10 OE_DIFF[4:5] I,PU Active high input pin enables DIFF[4:5] (internal 100 k pull-up). 11 OE_DIFF[6:8] I,PU Active high input pin enables DIFF[6:8] (internal 100 k pull-up). 12 VDD_DIFF PWR 3.3 V Power Supply 13 VDD_DIFF PWR 3.3 V Power Supply 14 DIFF0 O, DIF 0.7 V, 100 MHz differential clock output 15 DIFF0 O, DIF 0.7 V, 100 MHz differential clock output 16 VSS_DIFF 17 DIFF1 O, DIF 0.7 V, 100 MHz differential clock output 18 DIFF1 O, DIF 0.7 V, 100 MHz differential clock output 19 DIFF2 O, DIF 0.7 V, 100 MHz differential clock output 20 DIFF2 O, DIF 0.7 V, 100 MHz differential clock output 21 DIFF3 O, DIF 0.7 V, 100 MHz differential clock output 22 DIFF3 O, DIF 0.7 V, 100 MHz differential clock output 23 VDD_DIFF PWR 3.3V Power Supply 24 VSS_DIFF GND 25 DIFF4 O, DIF 0.7 V, 100 MHz differential clock output 26 DIFF4 O, DIF 0.7 V, 100 MHz differential clock output 27 DIFF5 O, DIF 0.7 V, 100 MHz differential clock output 28 DIFF5 O, DIF 0.7 V, 100 MHz differential clock output 29 VSS_DIFF 30 DIFF6 O, DIF 0.7 V, 100 MHz differential clock output 31 DIFF6 O, DIF 0.7 V, 100 MHz differential clock output 32 DIFF7 O, DIF 0.7 V, 100 MHz differential clock output 33 DIFF7 O, DIF 0.7 V, 100 MHz differential clock output 34 VDD_DIFF 35 DIFF8 O, DIF 0.7 V, 100 MHz differential clock output 36 DIFF8 O, DIF 0.7 V, 100 MHz differential clock output 18 GND GND Description Ground Ground Ground PWR 3.3 V Power Supply ??? 1.2 Si52147 Table 7. Si 52147 48-Pin QFN Descriptions (Continued) Pin # Name Type Description 2 37 SCLK I I C compatible SCLOCK 38 SDATA I/O 39 CKPWRGD/PDB I, PU 40 VDD_CORE 41 XOUT O 25.00 MHz crystal output, Float XOUT if using only CLKIN (Clock input). 42 XIN/CLKIN I 25.00 MHz crystal input or 3.3 V, 25 MHz Clock Input. 43 NC NC No Connect 44 NC NC No Connect 45 VSS_CORE GND Ground 46 VSS_DIFF GND Ground 47 NC NC No Connect 48 NC NC No Connect 49 GND GND I2C compatible SDATA Active low input pin asserts power down (PDB) and disables all outputs (internal 100 k pull-up). PWR 3.3 V Power Supply Ground for bottom pad of the IC. ??? 1.2 19 Si52147 6. 订购指南 Part Number Package Type Temperature Si52147-A01AGM 48-pin QFN Industrial, –40 to 85 C Si52147-A01AGMR 48-pin QFN—Tape and Reel Industrial, –40 to 85 C Lead-free 20 ??? 1.2 Si52147 7. 封装外形 图 6 说明 Si52147 的封装详细信息。表 8 列出插图中的尺寸值。 Figure 6. 48-Pin Quad Flat No Lead (QFN) Package Table 8. Package Diagram Dimensions Symbol Millimeters Min Nom Max A 0.70 0.75 0.80 A1 0.00 0.025 0.05 b 0.15 0.20 0.25 D D2 6.00 BSC 4.30 4.40 e 0.40 BSC E 6.00 BSC 4.50 E2 4.30 4.40 4.50 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.07 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. ??? 1.2 21 Si52147 文档修改列表 修订版 0.1 至修订版 1.0 更新引脚输出。 更新表 2。 更新第 2.1 节。 更新第 2.1.1 节。 更新第 2.2-2.8 节。 更新第 4.2 节。 更新表 7。 修订版 1.0 至修订版 1.1 从表 3 删除了湿敏度规格。 修订版 1.1 至修订版 1.2 22 更新了表 2。 更新了第 3 节。 ??? 1.2 Si52147 注意： ??? 1.2 23 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. 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