SL28PCIe14 PCI-Express Gen 2 & Gen 3 Clock Generator & Fan-out Buffer with EProClock® Technology Features • Four PCI-Express Gen2 & Gen 3 Clocks • 25MHz Crystal Input or Clock input • PCI-Express Gen 2 & Gen 3 Compliant • Low power push-pull type differential output buffers • Integrated resistors on differential clocks • HW Selectable Buffered Input or crystal synthesizer mode • Dedicated Output Enable pin for all clocks • HW Selectable Frequency and Spread Control • EProClock® Programmable Technology • I2C support with readback capabilities • Triangular Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • Industrial Temperature -40oC to 85oC • 3.3V Power supply • 32-pin QFN package Block Diagram XIN XOUT SS [1:0] Pin Configuration Crystal/ CLKIN PLL 1 (SSC) Divider SRC [3:0] DIFFIN DIFFIN# OE_SRC [3:0] IN_SEL EProClock Technology SCLK SDATA Logic Core VR PD# * Internal 100K-ohm pull-upresistor ** Internal 100K-ohm pull-down resistor DOC#: SP-AP-0014 (Rev. 0.2) 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 Page 1 of 13 www.silabs.com SL28PCIe14 32-QFN Pin Definitions Pin No. VDD Type PWR 2 SS0** I, PD 3 SS1** I, PD 1 Name Description 3.3V Power Supply Freqency/Spread Control. Default SS[1:0] =00. (internal 100K-ohm pull-down) SS1 0 0 1 1 MID MID SS0 0 1 0 1 0 1 Frequency 100M 100M 100M 100M 125MHz 200MHz Spread OFF -0.5% -/+0.25 -0.75% OFF OFF Note Default 4 IN_SEL* I, PU 3.3V input to select between crystal input or external differential buffer input mode. 0 = Synthesizer mode, 1=Fan-out Buffer mode (internal 100K-ohm pull-up; switching is not glitchless) 5 VSS GND Ground 6 OE_SRC0* I,PU 3.3V input to enabled SRC0 clock. (internal 100K-ohm pull-up) 7 OE_SRC1* I,PU 3.3V input to enabled SRC1 clock. (internal 100K-ohm pull-up) 8 VDD PWR 3.3V Power Supply 9 OE_SRC2* I,PU 3.3V input to enabled SRC2 clock. (internal 100K-ohm pull-up) GND Ground 10 VSS 11 SRC0 O, DIF 100MHz True differential serial reference clock 12 SRC0# O, DIF 100MHz Complement differential serial reference clock 13 SRC1 O, DIF 100MHz True differential serial reference clock 14 SRC1# O, DIF 100MHz Complement differential serial reference clock 15 VDD 16 VSS 17 SRC2# PWR 3.3V Power Supply GND Ground O, DIF 100MHz Complement differential serial reference clock 18 SRC2 O, DIF 100MHz True differential serial reference clock 19 SRC3# O, DIF 100MHz Complement differential serial reference clock 20 SRC3 O, DIF 100MHz True differential serial reference clock 21 VSS GND 22 VDD PWR 3.3V Power Supply 23 OE_SRC3* I,PU 3.3V input to enabled SRC3 clock. (internal 100K-ohm pull-up) 24 SCLK I 25 SDATA I/O 26 CKPWRGD/PD#* I,PU 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the SS[1:0]. After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for asserting power down (active LOW) 27 VDD PWR 3.3V Power Supply Ground SMBus compatible SCLOCK SMBus compatible SDATA 28 XOUT O 25.00MHz Crystal output, Float XOUT if using only CLKIN (Clock input) 29 XIN / CLKIN I 25.00MHz Crystal input or 3.3V, 25MHz Clock Input 30 DIFFIN I True differential serial reference clock input 31 DIFFIN# I Complement differential serial reference clock 32 VSS DOC#: SP-AP-0014 (Rev. 0.2) GND Ground Page 2 of 13 SL28PCIe14 EProClock® Programmable Technology EProClock® is the world’s first non-volatile programmable clock. The EProClock® technology allows board designer to promptly achieve optimum compliance and clock signal integrity; historically, attainable typically through device and/or board redesigns. - Custom frequency sets EProClock® technology can be configured through SMBus or hard coded. - Differential and single-ended slew rate control - Differential skew control on true or compliment or both - Differential duty cycle control on true or compliment or both - Differential amplitude control Features: - Program Internal or External series resistor on single-ended clocks - > 4000 bits of configurations - Program different spread profiles - Can be configured through SMBus or hard coded - Program different spread modulation rate Frequency/Spread Select Pin (SS[1:0]) SS1 SS0 Frequency (MHz) Spread (%) 0 0 100.00 OFF 0 1 100.00 - 0.5 1 0 100.00 +/- 0.25 1 1 100.00 - 0.75 MID 0 125 OFF MID 1 200 OFF Note Default Value for SS [1:0] =00 Frequency/Spread Select Pin SS[1:0] Apply the appropriate logic levels to SS [1:0] inputs before CKPWRGD assertion to achieve clock frequency selection. When the clock chip sampled HIGH on CKPWRGD and indicates that the voltage is stable then SS [1:0] input values are sampled. This process employs a one-shot functionality and once the CKPWRGD sampled a valid HIGH, all other SS[1:0], and CKPWRGD transitions are ignored. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers are individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit 7 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation (6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 Description Start DOC#: SP-AP-0014 (Rev. 0.2) Block Read Protocol Bit 1 Description Start Page 3 of 13 SL28PCIe14 Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 8:2 Description Slave address–7 bits Block Read Protocol Bit 8:2 Description Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 28 36:29 37 45:38 46 Command Code–8 bits 18:11 Acknowledge from slave 19 Byte Count–8 bits 20 Acknowledge from slave 27:21 Command Code–8 bits Acknowledge from slave Repeat start Slave address–7 bits Data byte 1–8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2–8 bits 37:30 Acknowledge from slave 38 .... Data Byte /Slave Acknowledges .... Data Byte N–8 bits 46:39 47 .... Acknowledge from slave .... Stop 55:48 Byte Count from slave–8 bits Acknowledge Data byte 1 from slave–8 bits Acknowledge Data byte 2 from slave–8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave–8 bits .... NOT Acknowledge .... Stop Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Description Start Byte Read Protocol Bit 1 Slave address–7 bits 8:2 Description Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 Command Code–8 bits 18:11 Acknowledge from slave 19 Data byte–8 bits 28 Acknowledge from slave 29 Stop 20 27:21 Command Code–8 bits Acknowledge from slave Repeated start Slave address–7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave–8 bits 38 NOT Acknowledge 39 Stop Control Registers Byte 0: Control Register 0 Bit @Pup Type Name 7 0 R/W RESERVED RESERVED 6 0 R/W RESERVED RESERVED DOC#: SP-AP-0014 (Rev. 0.2) Description Page 4 of 13 SL28PCIe14 Byte 0: Control Register 0 5 0 R/W RESERVED RESERVED 4 0 R/W RESERVED RESERVED 3 0 R/W RESERVED RESERVED 2 0 R/W RESERVED RESERVED 1 0 R/W RESERVED RESERVED 0 0 R/W RESERVED RESERVED Byte 1: Control Register 1 Bit @Pup Type Name 7 0 R/W RESERVED RESERVED Description 6 0 R/W RESERVED RESERVED 5 0 R/W RESERVED RESERVED 4 0 R/W RESERVED RESERVED 3 0 R/W RESERVED RESERVED 2 1 R/W SRC0_OE 1 0 R/W RESERVED 0 1 R/W SRC1_OE Output enable for SRC0 0 = Output Disabled, 1 = Output Enabled RESERVED Output enable for SRC1 0 = Output Disabled, 1 = Output Enabled Byte 2: Control Register 2 Bit @Pup Type Name 7 1 R/W SRC2_OE Output enable for SRC2 0 = Output Disabled, 1 = Output Enabled Description 6 1 R/W SRC3_OE Output enable for SRC3 0 = Output Disabled, 1 = Output Enabled 5 0 R/W RESERVED RESERVED 4 0 R/W RESERVED RESERVED 3 0 R/W RESERVED RESERVED 2 0 R/W RESERVED RESERVED 1 0 R/W RESERVED RESERVED 0 0 R/W RESERVED RESERVED Byte 3: Control Register 3 Bit @Pup Type Name 7 0 R Rev Code Bit 3 Revision Code Bit 3 Description 6 0 R Rev Code Bit 2 Revision Code Bit 2 5 0 R Rev Code Bit 1 Revision Code Bit 1 4 0 R Rev Code Bit 0 Revision Code Bit 0 3 1 R Vendor ID bit 3 Vendor ID Bit 3 2 0 R Vendor ID bit 2 Vendor ID Bit 2 1 0 R Vendor ID bit 1 Vendor ID Bit 1 0 0 R Vendor ID bit 0 Vendor ID Bit 0 Byte 4: Control Register 4 Bit @Pup Type DOC#: SP-AP-0014 (Rev. 0.2) Name Description Page 5 of 13 SL28PCIe14 Byte 4: Control Register 4 7 0 R/W BC7 6 0 R/W BC6 5 0 R/W BC5 4 0 R/W BC4 3 0 R/W BC3 2 1 R/W BC2 1 1 R/W BC1 0 1 R/W BC0 Byte count register for block read operation. The default value for Byte count is 7. In order to read beyond Byte 7, the user should change the byte count limit.to or beyond the byte that is desired to be read. Byte 5: Control Register 5 Bit @Pup Type Name 7 1 R/W RESERVED RESERVED Description 6 1 R/W SRC_AMP2 5 0 R/W SRC_AMP1 4 1 R/W SRC_AMP0 SRC amplitude adjustment 000= 300mV, 001=400mV, 010=500mV, 011= 600mV 100= 700mV, 101=800mV, 110=900mV, 111= 1000mV 3 1 R/W RESERVED RESERVED 2 0 R/W RESERVED RESERVED 1 0 R/W RESERVED RESERVED 0 0 R/W RESERVED RESERVED OE[3:0] Assertion PD# (Power down) Assertion All differential outputs that were stopped are to resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2 and 6 clocks of the internal reference clock with all differential outputs resuming simultaneously. All stopped differential outputs must be driven HIGH within 10 ns of OE deassertion to a voltage greater than 200 mV. When PD# has been sampled LOW by the internal reference clock all differential clocks will be stopped in a glitch-free mannter to the LOW-LOW state within their next two consecutive rising edges. OE[3:0] Deassertion The impact of deasserting the OE pins is that all SRC outputs that are set in the control registers to stoppable via deassertion of OE are to be stopped after their next transition. The final state of all stopped SRC clocks is Low/Low. PD# (Power down) Clarification The CKPWRGD/PD# pin is a dual-function pin. During initial power up, the pin functions as CKPWRGD. Once CKPWRGD has been sampled HIGH by the clock chip, the pin assumes PD# functionality. The PD# pin is an asynchronous active LOW input used to shut off all clocks cleanly before shutting off power to the device. This signal is synchronized internally to the device before powering down the clock synthesizer. PD# is also an asynchronous input for powering up the system. When PD# is asserted LOW, clocks are driven to a LOW value and held before turning off the VCOs and the crystal oscillator. PD# Deassertion The power up latency will be less than 2ms for crystal input reference and less than 8ms for differential input reference clock. This is the delay from the power supply reaching the minimum value specified in the datasheet, until the time that the part is ready to sample any latched inputs on the first rising edge of CLKPWRGD. After the first rising edge on the CKPWRGD this pin becmoes PD#. After a valid rising edge on CKPWRGD/PD# pin, a time of not more than 1.8ms is allowed for the clock device’s internal PLL’s to power up and lock. After this time, all outputs are enabled in a glitch-free manner within a few clock cycles of each clock. . . . DOC#: SP-AP-0014 (Rev. 0.2) Page 6 of 13 SL28PCIe14 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit – 4.6 V –0.5 4.6 VDC –65 150 °C Functional –40 85 °C Commercial Temperature, Operating Ambient Functional 0 85 °C VDD_3.3V Main Supply Voltage Functional VIN Input Voltage Relative to VSS TS Temperature, Storage Non-functional TA Industrial Temperature, Operating Ambient TA TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case JEDEC (JESD 51) – 20 °C/ W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/ W ESDHBM ESD Protection (Human Body Model) JEDEC (JESD 22 - A114) 2000 – V UL-94 Flammability Rating UL (Class) Max. Unit 3.135 3.465 V 2.0 VDD + 0.3 V VSS – 0.3 0.8 V 2.2 – V V–0 Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description Condition VDD core 3.3V Operating Voltage VIH 3.3V Input High Voltage (SE) VIL 3.3V Input Low Voltage (SE) VIHI2C Input High Voltage SDATA, SCLK VILI2C Input Low Voltage SDATA, SCLK VIH_SS[1:0]_HIGH SS Input High Voltage VIH_SS[1:0]_MID SS Input MIDVoltage VIL_SS[1:0]_LOW SS Input Low Voltage IIH Input High Leakage Current Except internal pull-down resistors, 0 < VIN < VDD – IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN < VDD VOH 3.3V Output High Voltage (SE) IOH = –1 mA 3.3V Output Low Voltage (SE) IOL = 1 mA – 0.4 V IOZ High-impedance Output Current –10 10 A CIN Input Pin Capacitance 1.5 5 pF COUT Output Pin Capacitance LIN Pin Inductance IDD_PD Power Down Current – 1 mA IDD_3.3V Dynamic Supply Current in synthesizer mode Differential clocks with 5” traces and 2pF load, frequency at 100MHz. – 50 mA IDD_3.3V Dynamic Supply Current in fanout mode Differential clocks with 5” traces and 2pF load, frequency at 100MHz. – 30 mA VOL DOC#: SP-AP-0014 (Rev. 0.2) 3.3 ± 5% Min. – 1.0 V 0.7 VDD+0.3 V 0.7 1.5 V VSS – 0.3 0.35 V 5 A –5 – A 2.4 – V – 6 pF 7 nH Page 7 of 13 SL28PCIe14 AC Electrical Specifications Parameter Description Condition Min. Max. Unit – 250 ppm Crystal LACC Long-term Accuracy Measured at VDD/2 differential Clock Input TDC CLKIN Duty Cycle Measured at VDD/2 47 53 % TR/TF CLKIN Rise and Fall Times Measured between 0.2VDD and 0.8VDD 0.5 4.0 V/ns TCCJ CLKIN Cycle to Cycle Jitter (Sythesizer) Measured at VDD/2 – 250 ps TLTJ CLKIN Long Term Jitter – 350 ps VIH Input High Voltage XIN / CLKIN pin 2 VDD+0.3 V VIL Input Low Voltage XIN / CLKIN pin – 0.8 V IIH Input HighCurrent XIN / CLKIN pin, VIN = VDD IIL Input LowCurrent XIN / CLKIN pin, 0 < VIN <0.8 TDC Duty Cycle RMSGEN1 Measured at VDD/2 – 35 uA –35 – uA Measured at 0V differential 45 55 % Output PCIe* Gen1 REFCLK phase jitter BER = 1E-12 (including PLL BW 8 - 16 MHz, ζ = 0.54, Td=10 ns, Ftrk=1.5 MHz) 0 108 ps Output PCIe* Gen2 REFCLK phase jitter Includes PLL BW 8 - 16 MHz, Jitter Peaking = 3dB, ζ = 0.54, Td=10 ns), Low Band, F < 1.5MHz 0 3.0 ps Output PCIe* Gen2 REFCLK phase jitter Includes PLL BW 8 - 16 MHz, Jitter Peaking = 3dB, ζ = 0.54, Td=10 ns), Low Band, F < 1.5MHz 0 3.1 ps Output phase jitter impact – PCIe* Gen3 Includes PLL BW 2 - 4 MHz, CDR = 10MHz) 0 1.0 ps TCCJ Cycle to Cycle Jitter Measured at 0V differential – 85 ps TCCJ Additive Cycle to Cycle Jitter In buffer mode. Measured at 0V differential – 50 ps LACC Long-term Accuracy Measured at 0V differential T R / TF Rising/Falling Slew rate Measured differentially from ±150 mV VOX Crossing Point Voltage at 0.7V Swing SRC at 0.7V RMSGEN2 RMSGEN2 RMSGEN3 – 100 ppm 2.5 8 V/ns 300 550 mV – 1.8 ms 10.0 – ns ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up TSS Stopclock Set-up Time DOC#: SP-AP-0014 (Rev. 0.2) Page 8 of 13 SL28PCIe14 Test and Measurement Set-up For Differential Clock Signals This diagram shows the test load configuration for the differential clock signals Figure 1. 0.7V Differential Load Configuration Figure 2. Differential Measurement for Differential Output Signals (for AC Parameters Measurement) DOC#: SP-AP-0014 (Rev. 0.2) Page 9 of 13 SL28PCIe14 Figure 3. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement) DOC#: SP-AP-0014 (Rev. 0.2) Page 10 of 13 SL28PCIe14 Ordering Information Part Number Package Type Product Flow Lead-free SL28PCIe14ALC 32-pin QFN Commercial, 0 to 85C SL28PCIe14ALCT 32-pin QFN – Tape and Reel Commercial, 0 to 85C SL28PCIe14ALI 32-pin QFN Industrial, -40 to 85C SL28PCIe14ALIT 32-pin QFN – Tape and Reel Industrial, -40 to 85C Package Diagrams 32-Lead QFN 5x 5mm DOC#: SP-AP-0014 (Rev. 0.2) Page 11 of 13 SL28PCIe14 Document History Page Document Title: SL28PCIe14 PC PCI-Express Gen 2 & Gen 3 Clock Generator & Fan-out Buffer with EProClock® Technology DOC#: SP-AP-0014 (Rev. 0.2) REV. ECR# Issue Date Orig. of Change AA 1695 02/09/11 JMA DOC#: SP-AP-0014 (Rev. 0.2) Description of Change Initial Release Page 12 of 13 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. 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