SL28PCIe16

SL28PCIe16
EProClock® PCI Express Gen 2 & Gen 3 Clock Generator
Features
• 25MHz Crystal Input or Clock input
• Optimized 100 MHz Operating Frequencies to Meet the
Next Generation PCI-Express Gen 2 & Gen 3
• Low power push-pull type differential output buffers
• Integrated voltage regulator
• Integrated resistors on differential clocks
• Six 100-MHz differential SRC clocks
• EProClock® Programmable Technology
• I2C support with readback capabilities
• Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Industrial Temperature -40oC to 85oC
• 3.3V Power supply
• 32-pin QFN package
• Low jitter (<50ps)
Pin Configuration
Block Diagram
XIN
XOUT
Crystal/
CLKIN
PLL 1
(SSC)
Divider
SRC [5:0]
EProClock
Technology
SCLK
SDATA
Logic
Core
VR
DOC#: SP-AP-0790 (Rev. 0.3)
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
Page 1 of 12
www.silabs.com
SL28PCIe16
32-QFN Pin Definitions
Pin No.
1
Name
VDD_SRC
Type
PWR
3.3V Power Supply
2
VDD_SRC
PWR
3.3V Power Supply
3
NC
NC
4
VSS
GND
Ground
5
VSS
GND
Ground
6
SRC0
O, DIF 100MHz True differential serial reference clock
7
SRC0#
O, DIF 100MHz Complement differential serial reference clock
8
VDD_SRC
PWR
Description
No Connect.
3.3V Power Supply
9
SRC1
O, DIF 100MHz True differential serial reference clock
10
SRC1#
O, DIF 100MHz Complement differential serial reference clock
11
SRC2
O, DIF 100MHz True differential serial reference clock
12
SRC2#
O, DIF 100MHz Complement differential serial reference clock
13
VSS_SRC
GND
Ground
14
VDD_SRC
PWR
3.3V Power Supply
15
SRC3#
O, DIF 100MHz Complement differential serial reference clock
16
SRC3
O, DIF 100MHz True differential serial reference clock
17
SRC4#
O, DIF 100MHz Complement differential serial reference clock
18
SRC4
O, DIF 100MHz True differential serial reference clock
19
VDD_SRC
20
SRC5#
O, DIF 100MHz Complement differential serial reference clock
PWR
21
SRC5
O, DIF 100MHz True differential serial reference clock
22
VSS_SRC
23
SCLK
I
24
SDATA
I/O
25
XOUT
O
25.00MHz Crystal output, Float XOUT if using only CLKIN (Clock input)
26
XIN / CLKIN
I
25.00MHz Crystal input or 3.3V, 25MHz Clock Input
27
VSS_CORE
GND
28
NC
GND
NC
3.3V Power Supply
Ground
SMBus compatible SCLOCK
SMBus compatible SDATA
Ground
No Connect.
29
VDD_CORE
PWR
3.3V Power Supply
30
VDD_SRC
PWR
3.3V Power Supply
31
NC
32
VSS_SRC
NC
GND
No Connect.
Ground
EProClock® Programmable Technology
EProClock® is the world’s first non-volatile programmable
clock. The EProClock® technology allows board designer to
promptly achieve optimum compliance and clock signal
integrity; historically, attainable typically through device and/or
board redesigns.
- Differential skew control on true or compliment or both
EProClock® technology can be configured through SMBus or
hard coded.
- Program Internal or External series resistor on single-ended
clocks
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
- Differential and single-ended slew rate control
Features:
- Program different spread profiles
- > 4000 bits of configurations
- Program different spread modulation rate
- Can be configured through SMBus or hard coded
- Custom frequency sets
DOC#: SP-AP-0790 (Rev. 0.3)
Page 2 of 12
SL28PCIe16
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
Table 1. Command Code Definition
Bit
7
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
Description
Start
Block Read Protocol
Bit
1
Slave address–7 bits
Write
8:2
9
Acknowledge from slave
Command Code–8 bits
10
18:11
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Byte Count–8 bits
20
Repeat start
Acknowledge from slave
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
27:21
Read = 1
29
Acknowledge from slave
37:30
46
Acknowledge from slave
....
Data Byte /Slave Acknowledges
....
Data Byte N–8 bits
....
Acknowledge from slave
....
Stop
Slave address–7 bits
28
38
46:39
47
55:48
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
56
Acknowledge
....
Data bytes from slave / Acknowledge
....
Data Byte N from slave–8 bits
....
NOT Acknowledge
....
Stop
Control Registers
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
Description
Start
DOC#: SP-AP-0790 (Rev. 0.3)
Byte Read Protocol
Bit
1
Description
Start
Page 3 of 12
SL28PCIe16
Table 3. Byte Read and Byte Write Protocol
8:2
Slave address–7 bits
8:2
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
19
27:20
Command Code–8 bits
18:11
Acknowledge from slave
19
Data byte–8 bits
20
28
Acknowledge from slave
29
Stop
27:21
Command Code–8 bits
Acknowledge from slave
Repeated start
Slave address–7 bits
28
Read
29
Acknowledge from slave
37:30
Data from slave–8 bits
38
NOT Acknowledge
39
Stop
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED
6
0
RESERVED
RESERVED
5
1
Spread Enable
4
0
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Enable spread for SRC outputs
0=Disable, 1= -0.5%
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
0
RESERVED
6
1
SRC0_OE
5
0
RESERVED
RESERVED
4
0
RESERVED
RESERVED
3
1
SRC1_OE
2
1
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
RESERVED
Output enable for SRC0
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC1
0 = Output Disabled, 1 = Output Enabled
Byte 2: Control Register 2
Bit
@Pup
Name
7
0
RESERVED
RESERVED
6
0
RESERVED
RESERVED
5
0
RESERVED
RESERVED
4
0
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
DOC#: SP-AP-0790 (Rev. 0.3)
Description
Page 4 of 12
SL28PCIe16
Byte 2: Control Register 2 (continued)
Bit
@Pup
Name
Description
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
1
SRC4_OE
Output enable for SRC4
0 = Output Disabled, 1 = Output Enabled
6
1
SRC5_OE
Output enable for SRC5
0 = Output Disabled, 1 = Output Enabled
5
0
RESERVED
RESERVED
4
0
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Byte 4: Control Register 4
Bit
@Pup
Name
7
0
RESERVED
RESERVED
Description
6
0
RESERVED
RESERVED
5
1
RESERVED
RESERVED
4
0
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Byte 5: Control Register 5
Bit
@Pup
Name
7
0
RESERVED
RESERVED
Description
6
0
RESERVED
RESERVED
5
0
RESERVED
RESERVED
4
1
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Byte 6: Control Register 6
Bit
@Pup
Name
7
0
SRC[5:4]_AMP1
6
1
SRC[5:4]_AMP0
DOC#: SP-AP-0790 (Rev. 0.3)
Description
SRC[5:4] amplitude adjustment
00= 700mV, 01=800mV, 10=900mV, 11= 1000mV
Page 5 of 12
SL28PCIe16
Byte 6: Control Register 6
5
0
SRC[3:1]_AMP1
SRC[3:1] amplitude adjustment
00= 700mV, 01=800mV, 10=900mV, 11= 1000mV
4
1
SRC[3:1]_AMP0
3
0
RESERVED
RESERVED
2
1
RESERVED
RESERVED
1
0
SRC0_AMP1
0
1
SRC0_AMP0
SRC0 amplitude adjustment
00= 700mV, 01=800mV, 10=900mV, 11= 1000mV
Byte 7: Vendor ID
Bit
@Pup
Name
7
0
Rev Code Bit 3
Revision Code Bit 3
Description
6
0
Rev Code Bit 2
Revision Code Bit 2
5
0
Rev Code Bit 1
Revision Code Bit 1
4
1
Rev Code Bit 0
Revision Code Bit 0
3
1
Vendor ID bit 3
Vendor ID Bit 3
2
0
Vendor ID bit 2
Vendor ID Bit 2
1
0
Vendor ID bit 1
Vendor ID Bit 1
0
0
Vendor ID bit 0
Vendor ID Bit 0
Byte 8: Control Register 8
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED
6
0
RESERVED
RESERVED
5
0
RESERVED
4
0
BC4
3
1
BC3
2
1
BC2
1
1
BC1
0
1
BC0
RESERVED
Byte count register for block read operation.
The default value for Byte count is 9.
In order to read beyond Byte 9, the user should change the byte count
limit.to or beyond the byte that is desired to be read.
Byte 9: Control Register 9
Bit
@Pup
Name
7
0
RESERVED
6
1
SRC3_OE
Output enable for SRC3
0 = Output Disabled, 1 = Output Enabled
5
1
SRC2_OE
Output enable for SRC2
0 = Output Disabled, 1 = Output Enabled
4
0
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
1
RESERVED
RESERVED
DOC#: SP-AP-0790 (Rev. 0.3)
Description
RESERVED
Page 6 of 12
SL28PCIe16
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
–
4.6
V
–0.5
4.6
VDC
–65
150
°C
Functional
–40
85
°C
Commercial Temperature,
Operating Ambient
Functional
0
85
°C
VDD_3.3V
Main Supply Voltage
VIN
Input Voltage
Relative to VSS
TS
Temperature, Storage
Non-functional
TA
Industrial Temperature,
Operating Ambient
TA
Functional
TJ
Temperature, Junction
Functional
–
150
°C
ØJC
Dissipation, Junction to Case
JEDEC (JESD 51)
–
20
°C/
W
ØJA
Dissipation, Junction to Ambient JEDEC (JESD 51)
–
60
°C/
W
ESDHBM
ESD Protection (Human Body
Model)
JEDEC (JESD 22 - A114)
2000
–
V
UL-94
Flammability Rating
UL (Class)
V–0
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
Description
VDD core
3.3V Operating Voltage
VIH
3.3V Input High Voltage
VIL
3.3V Input Low Voltage
Condition
Min.
Max.
Unit
3.135
3.465
V
Single-Ended Clock
2.0
VDD + 0.3
V
Single-Ended Clock
VSS – 0.3
0.8
V
3.3 ± 5%
VIHI2C
Input High Voltage
SDATA, SCLK
2.2
–
V
VILI2C
Input Low Voltage
SDATA, SCLK
–
1.0
V
IIH
Input High Leakage Current
Except internal pull-down resistors, 0 < VIN <
VDD
–
5
A
Except internal pull-up resistors, 0 < VIN < VDD
–5
–
A
0.7
0.9
V
3.3V Output Low Voltage (DIFF)
–
0.4
V
High-impedance Output Current
–10
10
A
CIN
Input Pin Capacitance
1.5
5
pF
COUT
Output Pin Capacitance
6
pF
LIN
Pin Inductance
IDD_3.3V
Dynamic Supply Current
IIL
Input Low Leakage Current
VOH
3.3V Output High Voltage (DIFF)
VOL
IOZ
DOC#: SP-AP-0790 (Rev. 0.3)
Differential clocks with 7” traces and 2pF load.
–
7
nH
–
65
mA
Page 7 of 12
SL28PCIe16
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
–
250
ppm
Crystal
LACC
Long-term Accuracy
Measured at VDD/2 differential
Clock Input
TDC
CLKIN Duty Cycle
Measured at VDD/2
47
53
%
TR/TF
CLKIN Rise and Fall Times
Measured between 0.2VDD and 0.8VDD
0.5
4.0
V/ns
TCCJ
CLKIN Cycle to Cycle Jitter
Measured at VDD/2
–
250
ps
TLTJ
CLKIN Long Term Jitter
Measured at VDD/2
–
350
ps
VIH
Input High Voltage
XIN / CLKIN pin
2
VDD+0.3
V
VIL
Input Low Voltage
XIN / CLKIN pin
–
0.8
V
IIH
Input High Current
XIN / CLKIN pin, VIN = VDD
–
35
uA
IIL
Input Low Current
XIN / CLKIN pin, 0 < VIN <0.8
–35
–
uA
TDC
SRC Duty Cycle
Measured at 0V differential
SRC at 0.7V
45
55
%
10.0010
ns
TPERIOD
100 MHz SRC Period
Measured at 0V differential at 0.1s
9.99900
TPERIODSS
100 MHz SRC Period, SSC
Measured at 0V differential at 0.1s
10.02406
10.02607
ns
TPERIODAbs
100 MHz SRC Absolute Period
10.1260
ns
Measured at 0V differential at 1 clock
9.87400
TPERIODSSAbs 100 MHz SRC Absolute Period, SSC
Measured at 0V differential at 1 clock
9.87406
10.1762
ns
TCCJ
SRC Cycle to Cycle Jitter
Measured at 0V differential
–
50
ps
RMSGEN1
Output PCIe* Gen1 REFCLK phase
jitter
BER = 1E-12 (including PLL BW 8 - 16
MHz, ζ = 0.54, Td=10 ns,
Ftrk=1.5 MHz)
0
108
ps
Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz
0
3.0
ps
Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz
0
3.1
ps
Includes PLL BW 2 - 4 MHz,
CDR = 10MHz)
Measured at 0V differential
0
1.0
ps
LACC
Output phase jitter impact – PCIe*
Gen3
SRC Long Term Accuracy
–
100
ppm
T R / TF
SRC Rising/Falling Slew Rate
Measured differentially from ±150 mV
2.5
8
V/ns
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
–
1.8
ms
10.0
–
ns
RMSGEN2
RMSGEN2
RMSGEN3
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
TSS
Stopclock Set-up Time
DOC#: SP-AP-0790 (Rev. 0.3)
Page 8 of 12
SL28PCIe16
Test and Measurement Set-up
This diagram shows the test load configuration for the differential clock signals
Figure 1. 0.7V Differential Load Configuration
Figure 2. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)
DOC#: SP-AP-0790 (Rev. 0.3)
Page 9 of 12
SL28PCIe16
Figure 3. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)
DOC#: SP-AP-0790 (Rev. 0.3)
Page 10 of 12
SL28PCIe16
Ordering Information
Part Number
Package Type
Product Flow
Lead-free
SL28PCIe16ALC
32-pin QFN
Commercial, 0 to 85C
SL28PCIe16ALCT
32-pin QFN–Tape and Reel
Commercial, 0 to 85C
SL28PCIe16ALI
32-pin QFN
Industrial, -40 to 85C
SL28PCIe16ALIT
32-pin QFN–Tape and Reel
Industrial, -40 to 85C
Package Diagrams
32-Lead QFN 5 x 5mm
DOC#: SP-AP-0790 (Rev. 0.3)
Page 11 of 12
SL28PCIe16
Document History Page
Document Title: SL28PCIe16 PC EProClock® PCI Express Gen 2 & Gen 3 Clock Generator
DOC#: SP-AP-0790 (Rev. 0.3)
REV.
Issue Date
Orig. of
Change
AA
11/15/10
JMA
Initial Release
AA
12/15/10
TRP
1. Updated Control Registers
2. Updated VOH/VOL spec
3. Removed IDD_PD spec
4. Updated foot note
AB
1/13/11
TRP
1. Updated IDD current
2. Updated Byte8 default
3. Removed skew spec
Description of Change
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
DOC#: SP-AP-0790 (Rev. 0.3)
Page 12 of 12