PCI Express Compliance Report Page 1 of 26 Data File Overview File Type Time Domain Differential Waveform File C:\Users\lilua\Desktop\Si52147 Samples\Si52147_SN001_waveform_25C.bin Waveform File Creation Date 2015-09-09 14:48:02 GMT-07:00 Edge Filtering On Clock Frequency 100.007 MHz Number of Edges 256,268 Sample Interval 50.000 ps Average Threshold Voltage -364.726 μV Jitter Summary # 1 Class GEN1 Data Rate Architecture Specs PLL1 BW PLL1 Peak 2.5 Gb/s Common Clock 1.1 2.1 3.1 22 MHz 3 dB PLL2 BW PLL2 Peak 1.5 MHz 3 dB CDR BW Specification CDR Peak HF RMS LF RMS Pk-Pk 1.5 MHz 0 dB 86 ps Analysis Result HF RMS LF RMS 2.51 ps 1.69 ps Pk-Pk Compliance Result 23.00 ps PASS 2 GEN2 5 Gb/s Common Clock 3.1 5 MHz 0.5 dB 16 MHz 0.5 dB N/A N/A 3.1 ps 3 ps 1.30 ps 1.01 ps 11.04 ps 3 GEN2 5 Gb/s Common Clock 3.1 5 MHz 1 dB 16 MHz 0.5 dB N/A N/A 3.1 ps 3 ps 1.38 ps 816.12 fs 9.53 ps PASS 4 GEN2 5 Gb/s Common Clock 3.1 8 MHz 3 dB 16 MHz 0.5 dB N/A N/A 3.1 ps 3 ps 1.32 ps 417.64 fs 4.15 ps PASS 5 GEN2 5 Gb/s Common Clock 3.1 5 MHz 0.5 dB 16 MHz 1 dB N/A N/A 3.1 ps 3 ps 1.37 ps 1.06 ps 11.67 ps PASS 6 GEN2 5 Gb/s Common Clock 3.1 5 MHz 1 dB 16 MHz 1 dB N/A N/A 3.1 ps 3 ps 1.45 ps 869.23 fs 10.20 ps PASS 7 GEN2 5 Gb/s Common Clock 3.1 8 MHz 3 dB 16 MHz 1 dB N/A N/A 3.1 ps 3 ps 1.34 ps 449.02 fs 4.51 ps PASS 8 GEN2 5 Gb/s Common Clock 2.1 3.1 5 MHz 0.5 dB 16 MHz 3 dB N/A N/A 3.1 ps 3 ps 1.56 ps 1.08 ps 9 GEN2 5 Gb/s Common Clock 1.1 2.1 3.1 5 MHz 1 dB 16 MHz 3 dB N/A N/A 3.1 ps 3 ps 1.65 ps 900.38 fs 10.64 ps 12.02 ps PASS PASS PASS 10 GEN2 5 Gb/s Common Clock 2.1 3.1 8 MHz 3 dB 16 MHz 11 GEN3 8 Gb/s Common Clock 3.1 4.0 2 MHz 0.01 dB 2 MHz 12 GEN3 8 Gb/s Common Clock 3.1 4.0 2 MHz 2 dB 13 GEN3 8 Gb/s Common Clock 3.1 4.0 14 GEN3 8 Gb/s N/A 3.1 ps 3 ps 1.54 ps 0.01 dB 10 MHz 0 dB 1 ps 132.92 fs 23.63 fs 2 MHz 0.01 dB 10 MHz 0 dB 1 ps 220.41 fs 133.68 fs 2.11 ps 4 MHz 0.01 dB 2 MHz 0.01 dB 10 MHz 0 dB 1 ps 306.15 fs 99.54 fs Common Clock 3.1 4.0 4 MHz 2 dB 0.01 dB 10 MHz 0 dB 1 ps 294.18 fs 171.27 fs 2.62 ps 15 GEN3 8 Gb/s Common Clock 3.1 4.0 2 MHz 0.01 dB 2 MHz 1 dB 10 MHz 0 dB 1 ps 168.76 fs 82.68 fs 1.61 ps 16 GEN3 8 Gb/s Common Clock 3.1 4.0 2 MHz 2 dB 2 MHz 1 dB 10 MHz 0 dB 1 ps 151.95 fs 71.58 fs 1.48 ps 17 GEN3 8 Gb/s Common Clock 3.1 4.0 4 MHz 0.01 dB 2 MHz 1 dB 10 MHz 0 dB 1 ps 345.70 fs 132.84 fs 3.39 ps 18 GEN3 8 Gb/s Common Clock 3.1 4.0 4 MHz 2 dB 1 dB 10 MHz 0 dB 1 ps 325.89 fs 184.16 fs 2.90 ps 19 GEN3 8 Gb/s Common Clock 3.1 4.0 2 MHz 0.01 dB 5 MHz 0.01 dB 10 MHz 0 dB 1 ps 375.57 fs 115.91 fs 3.58 ps 20 GEN3 8 Gb/s Common Clock 3.1 4.0 2 MHz 2 dB 5 MHz 0.01 dB 10 MHz 0 dB 1 ps 457.62 fs 183.62 fs 4.52 ps 21 GEN3 8 Gb/s Common Clock 3.1 4.0 4 MHz 0.01 dB 5 MHz 0.01 dB 10 MHz 0 dB 1 ps 302.31 fs 42.17 fs 3.10 ps 22 GEN3 8 Gb/s Common Clock 3.1 4.0 4 MHz 2 dB 0.01 dB 10 MHz 0 dB 1 ps 382.88 fs 84.86 fs 3.56 ps 23 GEN3 8 Gb/s Common Clock 3.1 4.0 2 MHz 0.01 dB 5 MHz 1 dB 10 MHz 0 dB 1 ps 363.62 fs 155.78 fs 3.22 ps 24 GEN3 8 Gb/s Common Clock 3.1 4.0 2 MHz 2 dB 1 dB 10 MHz 0 dB 1 ps 443.94 fs 195.52 fs 4.16 ps 2 MHz 2 MHz 5 MHz 5 MHz 3 dB N/A 470.50 fs 4.93 ps Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. 1.34 ps 2.91 ps PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PCI Express Compliance Report Page 2 of 26 # Class Data Rate PLL1 BW Architecture Specs PLL1 Peak PLL2 BW PLL2 Peak CDR BW Specification CDR Peak HF RMS LF RMS Pk-Pk Analysis Result HF RMS LF RMS Pk-Pk Compliance Result 25 GEN3 8 Gb/s Common Clock 3.1 4.0 4 MHz 0.01 dB 5 MHz 1 dB 10 MHz 0 dB 1 ps 278.01 fs 80.18 fs 2.72 ps 26 GEN3 8 Gb/s Common Clock 3.1 4.0 4 MHz 2 dB 1 dB 10 MHz 0 dB 1 ps 317.39 fs 43.47 fs 3.00 ps 27 GEN4 16 Gb/s Common Clock 4.0 2 MHz 0.01 dB 2 MHz 0.01 dB 10 MHz 0 dB 1 ps 132.92 fs 23.63 fs 1.34 ps PASS 28 GEN4 16 Gb/s Common Clock 4.0 2 MHz 2 dB 2 MHz 0.01 dB 10 MHz 0 dB 1 ps 220.41 fs 133.68 fs 2.11 ps PASS 29 GEN4 16 Gb/s Common Clock 4.0 4 MHz 0.01 dB 2 MHz 0.01 dB 10 MHz 0 dB 1 ps 306.15 fs 99.54 fs 2.91 ps PASS 30 GEN4 16 Gb/s Common Clock 4.0 4 MHz 2 dB 0.01 dB 10 MHz 0 dB 1 ps 294.18 fs 171.27 fs 2.62 ps PASS 31 GEN4 16 Gb/s Common Clock 4.0 2 MHz 0.01 dB 2 MHz 1 dB 10 MHz 0 dB 1 ps 168.76 fs 82.68 fs 1.61 ps PASS 32 GEN4 16 Gb/s Common Clock 4.0 2 MHz 2 dB 2 MHz 1 dB 10 MHz 0 dB 1 ps 151.95 fs 71.58 fs 1.48 ps PASS 33 GEN4 16 Gb/s Common Clock 4.0 4 MHz 0.01 dB 2 MHz 1 dB 10 MHz 0 dB 1 ps 345.70 fs 132.84 fs 3.39 ps PASS 34 GEN4 16 Gb/s Common Clock 4.0 4 MHz 2 dB 1 dB 10 MHz 0 dB 1 ps 325.89 fs 184.16 fs 2.90 ps PASS 35 GEN4 16 Gb/s Common Clock 4.0 2 MHz 0.01 dB 5 MHz 0.01 dB 10 MHz 0 dB 1 ps 375.57 fs 115.91 fs 3.58 ps PASS 36 GEN4 16 Gb/s Common Clock 4.0 2 MHz 2 dB 5 MHz 0.01 dB 10 MHz 0 dB 1 ps 457.62 fs 183.62 fs 4.52 ps PASS 37 GEN4 16 Gb/s Common Clock 4.0 4 MHz 0.01 dB 5 MHz 0.01 dB 10 MHz 0 dB 1 ps 302.31 fs 42.17 fs 3.10 ps PASS 38 GEN4 16 Gb/s Common Clock 4.0 4 MHz 2 dB 0.01 dB 10 MHz 0 dB 1 ps 382.88 fs 84.86 fs 3.56 ps PASS 39 GEN4 16 Gb/s Common Clock 4.0 2 MHz 0.01 dB 5 MHz 1 dB 10 MHz 0 dB 1 ps 363.62 fs 155.78 fs 3.22 ps PASS 40 GEN4 16 Gb/s Common Clock 4.0 2 MHz 2 dB 5 MHz 1 dB 10 MHz 0 dB 1 ps 443.94 fs 195.52 fs 4.16 ps PASS 41 GEN4 16 Gb/s Common Clock 4.0 4 MHz 0.01 dB 5 MHz 1 dB 10 MHz 0 dB 1 ps 278.01 fs 80.18 fs 2.72 ps PASS 42 GEN4 16 Gb/s Common Clock 4.0 4 MHz 2 dB 1 dB 10 MHz 0 dB 1 ps 317.39 fs 43.47 fs 3.00 ps PASS 5 MHz 2 MHz 2 MHz 5 MHz 5 MHz PASS PASS (1) Spread Spectrum Clocking (SSC) separation is intended to remove the energy associated with the spread spectrum (30KHz-33KHz) in the low frequency range (0.01-1.5MHz) specified by the PCI-Express Base Specification in order to define separate low frequency Rj and Dj components. This feature should be turned off for data sets that do not have spread spectrum clocking. Unfiltered Waveform Jitter Information vs. Time Time Interval Error Period Cycle-to-Cycle Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 3 of 26 Reference Clock AC Specifications Specification Analysis Result Test Min Max Min Max Avg Compliance Result Rising Edge Rate .6 V/ns 4 V/ns 1.31 V/ns 1.36 V/ns 1.33 V/ns PASS Falling Edge Rate .6 V/ns 4 V/ns 1.31 V/ns 1.35 V/ns 1.33 V/ns PASS Diff Input High 150 mV 225.70 mV 225.70 mV 225.70 mV PASS Diff Input Low -150 mV -225.70 mV -225.70 mV -225.70 mV PASS Average Clock Period Accuracy -300 ppm 2,800 ppm N/A N/A -73 ppm PASS Absolute Period 9.847 ns 10.203 ns 9.992 ns 10.006 ns 9.999 ns PASS Cycle to Cycle Jitter 150 ps 0.00 fs 11.65 ps 1.95 ps PASS Duty Cycle 40 % 60 % 49.5 % 50.0 % 49.9 % PASS Detailed Jitter Reports In the pages that follow, jitter response is analyzed for each selected standard, architecture and filter parameter combination. # Class Data Rate Architecture 1 GEN1 2.5 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 1.1 · 2.1 · 3.1 22 MHz 3 dB Specification Analysis Compliance Result Result Refclk HF RMS Jitter 2.512 ps Refclk LF RMS Jitter 1.691 ps N/A 23.003 ps PASS Test Pk-pk Phase Jitter at BER 10^-6 86 ps Low Frequency Phase Jitter 1.5 MHz 3 dB 1.5 MHz 0 dB 10 ns N/A N/A High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 4 of 26 # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 2 GEN2 5 Gb/s Common Clock 3.1 5 MHz 0.5 dB 16 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 3.1 ps 1.295 ps PASS Refclk LF RMS Jitter 3 ps 1.008 ps PASS 11.045 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 0.5 dB N/A Low Frequency Phase Jitter N/A 12 ns On (1) High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 3 GEN2 5 Gb/s Common Clock 3.1 5 MHz 1 dB 16 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 3.1 ps 1.376 ps PASS Refclk LF RMS Jitter 3 ps 816.120 fs PASS Test Pk-pk Phase Jitter at BER 10^-6 9.526 ps Low Frequency Phase Jitter 0.5 dB N/A N/A 12 ns On (1) N/A High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 5 of 26 # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 4 GEN2 5 Gb/s Common Clock 3.1 8 MHz 3 dB 16 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 3.1 ps 1.315 ps PASS Refclk LF RMS Jitter 3 ps 417.635 fs PASS Test Pk-pk Phase Jitter at BER 10^-6 4.152 ps 0.5 dB N/A N/A 12 ns On (1) N/A Low Frequency Phase Jitter High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 5 GEN2 5 Gb/s Common Clock 3.1 5 MHz 0.5 dB 16 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 3.1 ps 1.371 ps PASS Refclk LF RMS Jitter 3 ps 1.056 ps PASS 11.667 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 1 dB N/A N/A 12 ns On (1) High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 6 of 26 # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 6 GEN2 5 Gb/s Common Clock 3.1 5 MHz 1 dB 16 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 3.1 ps 1.454 ps PASS Refclk LF RMS Jitter 3 ps 869.229 fs PASS 10.200 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 1 dB N/A Low Frequency Phase Jitter N/A 12 ns On (1) High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 7 GEN2 5 Gb/s Common Clock 3.1 8 MHz 3 dB 16 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 3.1 ps 1.340 ps PASS Refclk LF RMS Jitter 3 ps 449.017 fs PASS Test Pk-pk Phase Jitter at BER 10^-6 4.510 ps Low Frequency Phase Jitter 1 dB N/A N/A 12 ns On (1) N/A High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 7 of 26 # Class Data Rate Architecture 8 GEN2 5 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 2.1 · 3.1 5 MHz 0.5 dB 16 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 3.1 ps 1.559 ps PASS Refclk LF RMS Jitter 3 ps 1.081 ps PASS 12.020 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 3 dB N/A N/A Low Frequency Phase Jitter 12 ns On (1) High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture 9 GEN2 5 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 1.1 · 2.1 · 3.1 5 MHz 1 dB Specification Analysis Compliance Result Result Refclk HF RMS Jitter 3.1 ps 1.652 ps PASS Refclk LF RMS Jitter 3 ps 900.379 fs PASS 10.644 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 16 MHz 3 dB N/A N/A 12 ns On (1) High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 8 of 26 # Class Data Rate Architecture 10 GEN2 5 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 2.1 · 3.1 8 MHz 3 dB 16 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 3.1 ps 1.537 ps PASS Refclk LF RMS Jitter 3 ps 470.504 fs PASS Test Pk-pk Phase Jitter at BER 10^-6 4.935 ps 3 dB N/A N/A 12 ns On (1) N/A Low Frequency Phase Jitter High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture 11 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 2 MHz 0.01 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 132.923 fs PASS Refclk LF RMS Jitter 23.631 fs N/A 1.344 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 0.01 dB 10 MHz 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 9 of 26 # Class Data Rate Architecture 12 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 2 MHz 2 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 220.406 fs PASS Refclk LF RMS Jitter 133.682 fs N/A 2.111 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 0.01 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture 13 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 4 MHz 0.01 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 306.155 fs PASS Refclk LF RMS Jitter 99.543 fs N/A 2.906 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 0.01 dB 10 MHz 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 10 of 26 # Class Data Rate Architecture 14 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 4 MHz 2 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 294.181 fs PASS Refclk LF RMS Jitter 171.271 fs N/A 2.622 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 0.01 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture 15 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 2 MHz 0.01 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 168.765 fs PASS Refclk LF RMS Jitter 82.676 fs N/A 1.615 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 1 dB 10 MHz 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 11 of 26 # Class Data Rate Architecture 16 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 2 MHz 2 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 151.948 fs PASS Refclk LF RMS Jitter 71.583 fs N/A 1.479 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 1 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture 17 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 4 MHz 0.01 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 345.702 fs PASS Refclk LF RMS Jitter 132.840 fs N/A 3.388 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 1 dB 10 MHz 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 12 of 26 # Class Data Rate Architecture 18 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 4 MHz 2 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 325.886 fs PASS Refclk LF RMS Jitter 184.162 fs N/A 2.899 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 1 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture 19 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 2 MHz 0.01 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 375.565 fs PASS Refclk LF RMS Jitter 115.907 fs N/A 3.584 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 0.01 dB 10 MHz 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 13 of 26 # Class Data Rate Architecture 20 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 2 MHz 2 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 457.624 fs PASS Refclk LF RMS Jitter 183.624 fs N/A 4.524 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 0.01 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture 21 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 4 MHz 0.01 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 302.315 fs PASS Refclk LF RMS Jitter 42.168 fs N/A 3.098 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 0.01 dB 10 MHz 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 14 of 26 # Class Data Rate Architecture 22 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 4 MHz 2 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 382.880 fs PASS Refclk LF RMS Jitter 84.858 fs N/A 3.562 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 0.01 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture 23 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 2 MHz 0.01 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 363.617 fs PASS Refclk LF RMS Jitter 155.775 fs N/A 3.222 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 1 dB 10 MHz 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 15 of 26 # Class Data Rate Architecture 24 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 2 MHz 2 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 443.937 fs PASS Refclk LF RMS Jitter 195.517 fs N/A 4.162 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 1 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture 25 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 4 MHz 0.01 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 278.005 fs PASS Refclk LF RMS Jitter 80.184 fs N/A 2.723 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 1 dB 10 MHz 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 16 of 26 # Class Data Rate Architecture 26 GEN3 8 Gb/s Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation Common Clock 3.1 · 4.0 4 MHz 2 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 317.388 fs PASS Refclk LF RMS Jitter 43.469 fs N/A 2.999 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 1 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns Off (1) High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 27 GEN4 16 Gb/s Common Clock 4.0 2 MHz 0.01 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 132.923 fs PASS Refclk LF RMS Jitter 23.631 fs N/A 1.344 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 0.01 dB 10 MHz 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 17 of 26 # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 28 GEN4 16 Gb/s Common Clock 4.0 2 MHz 2 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 220.406 fs PASS Refclk LF RMS Jitter 133.682 fs N/A 2.111 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 0.01 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 29 GEN4 16 Gb/s Common Clock 4.0 4 MHz 0.01 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 306.155 fs PASS Refclk LF RMS Jitter 99.543 fs N/A 2.906 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 0.01 dB 10 MHz 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 18 of 26 # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 30 GEN4 16 Gb/s Common Clock 4.0 4 MHz 2 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 294.181 fs PASS Refclk LF RMS Jitter 171.271 fs N/A 2.622 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 0.01 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 31 GEN4 16 Gb/s Common Clock 4.0 2 MHz 0.01 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 168.765 fs PASS Refclk LF RMS Jitter 82.676 fs N/A 1.615 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 1 dB 10 MHz 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 19 of 26 # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 32 GEN4 16 Gb/s Common Clock 4.0 2 MHz 2 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 151.948 fs PASS Refclk LF RMS Jitter 71.583 fs N/A 1.479 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 1 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 33 GEN4 16 Gb/s Common Clock 4.0 4 MHz 0.01 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 345.702 fs PASS Refclk LF RMS Jitter 132.840 fs N/A 3.388 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 1 dB 10 MHz 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 20 of 26 # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 34 GEN4 16 Gb/s Common Clock 4.0 4 MHz 2 dB 2 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 325.886 fs PASS Refclk LF RMS Jitter 184.162 fs N/A 2.899 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 1 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 35 GEN4 16 Gb/s Common Clock 4.0 2 MHz 0.01 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 375.565 fs PASS Refclk LF RMS Jitter 115.907 fs N/A 3.584 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 0.01 dB 10 MHz 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 21 of 26 # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 36 GEN4 16 Gb/s Common Clock 4.0 2 MHz 2 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 457.624 fs PASS Refclk LF RMS Jitter 183.624 fs N/A 4.524 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 0.01 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 37 GEN4 16 Gb/s Common Clock 4.0 4 MHz 0.01 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 302.315 fs PASS Refclk LF RMS Jitter 42.168 fs N/A 3.098 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 0.01 dB 10 MHz 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 22 of 26 # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 38 GEN4 16 Gb/s Common Clock 4.0 4 MHz 2 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 382.880 fs PASS Refclk LF RMS Jitter 84.858 fs N/A 3.562 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 0.01 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 39 GEN4 16 Gb/s Common Clock 4.0 2 MHz 0.01 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 363.617 fs PASS Refclk LF RMS Jitter 155.775 fs N/A 3.222 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 1 dB 10 MHz 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 23 of 26 # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 40 GEN4 16 Gb/s Common Clock 4.0 2 MHz 2 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 443.937 fs PASS Refclk LF RMS Jitter 195.517 fs N/A 4.162 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 1 dB 10 MHz Low Frequency Phase Jitter 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 41 GEN4 16 Gb/s Common Clock 4.0 4 MHz 0.01 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 278.005 fs PASS Refclk LF RMS Jitter 80.184 fs N/A 2.723 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 1 dB 10 MHz 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 24 of 26 # Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation 42 GEN4 16 Gb/s Common Clock 4.0 4 MHz 2 dB 5 MHz Specification Analysis Compliance Result Result Refclk HF RMS Jitter 1 ps 317.388 fs PASS Refclk LF RMS Jitter 43.469 fs N/A 2.999 ps N/A Test Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter 1 dB 10 MHz 0 dB 12 ns N/A High Frequency Phase Jitter Filter Magnitude Responses Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. PCI Express Compliance Report Page 25 of 26 Transfer Function Constants H1 BW H1 Peaking H1 Omega H1 Zeta H2 BW H2 Peaking H2 Omega H2 Zeta H3 BW H3 Peaking H3 Omega H3 Zeta # Class Architecture Specs 1 GEN1 Common Clock 1.1 2.1 3.1 22 MHz 3 dB 7.46800E+7 5.40000E-1 1.5 MHz 3 dB 5.09000E+6 5.40000E-1 1.5 MHz 0 dB 2 GEN2 Common Clock 1.1 2.1 3.1 5 MHz 0.5 dB 8.30009E+6 1.75000E+0 16 MHz 0.5 dB 2.65716E+7 1.75000E+0 12 ns 3 GEN2 Common Clock 1.1 2.1 3.1 5 MHz 1 dB 1.14605E+7 1.16000E+0 16 MHz 0.5 dB 2.65716E+7 1.75000E+0 12 ns 4 GEN2 Common Clock 1.1 2.1 3.1 8 MHz 3 dB 2.70428E+7 5.40000E-1 16 MHz 0.5 dB 2.65716E+7 1.75000E+0 12 ns 5 GEN2 Common Clock 1.1 2.1 3.1 5 MHz 0.5 dB 8.30009E+6 1.75000E+0 16 MHz 1 dB 3.66624E+7 1.16000E+0 12 ns 6 GEN2 Common Clock 1.1 2.1 3.1 5 MHz 1 dB 1.14605E+7 1.16000E+0 16 MHz 1 dB 3.66624E+7 1.16000E+0 12 ns 7 GEN2 Common Clock 1.1 2.1 3.1 8 MHz 3 dB 2.70428E+7 5.40000E-1 16 MHz 1 dB 3.66624E+7 1.16000E+0 12 ns 8 GEN2 Common Clock 1.1 2.1 3.1 5 MHz 0.5 dB 8.30009E+6 1.75000E+0 16 MHz 3 dB 5.40919E+7 5.40000E-1 12 ns 9 GEN2 Common Clock 1.1 2.1 3.1 5 MHz 1 dB 1.14605E+7 1.16000E+0 16 MHz 3 dB 5.40919E+7 5.40000E-1 12 ns 10 GEN2 Common Clock 1.1 2.1 3.1 8 MHz 3 dB 2.70428E+7 5.40000E-1 16 MHz 3 dB 5.40919E+7 5.40000E-1 12 ns 11 GEN3 Common Clock 3.1 4.0 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 12 GEN3 Common Clock 3.1 4.0 2 MHz 2 dB 6.02000E+6 7.30000E-1 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 13 GEN3 Common Clock 3.1 4.0 4 MHz 0.01 dB 8.96000E+5 1.40000E+1 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 14 GEN3 Common Clock 3.1 4.0 4 MHz 2 dB 1.20400E+7 7.30000E-1 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 15 GEN3 Common Clock 3.1 4.0 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 2 MHz 1 dB 4.62000E+6 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 16 GEN3 Common Clock 3.1 4.0 2 MHz 2 dB 6.02000E+6 7.30000E-1 2 MHz 1 dB 4.62000E+6 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 17 GEN3 Common Clock 3.1 4.0 4 MHz 0.01 dB 8.96000E+5 1.40000E+1 2 MHz 1 dB 4.62000E+6 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 18 GEN3 Common Clock 3.1 4.0 4 MHz 2 dB 1.20400E+7 7.30000E-1 2 MHz 1 dB 4.62000E+6 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 19 GEN3 Common Clock 3.1 4.0 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 5 MHz 0.01 dB 1.12000E+6 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 20 GEN3 Common Clock 3.1 4.0 2 MHz 2 dB 6.02000E+6 7.30000E-1 5 MHz 0.01 dB 1.12000E+6 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 21 GEN3 Common Clock 3.1 4.0 4 MHz 0.01 dB 8.96000E+5 1.40000E+1 5 MHz 0.01 dB 1.12000E+6 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 22 GEN3 Common Clock 3.1 4.0 4 MHz 2 dB 1.20400E+7 7.30000E-1 5 MHz 0.01 dB 1.12000E+6 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 23 GEN3 Common Clock 3.1 4.0 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 5 MHz 1 dB 1.15300E+7 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 24 GEN3 Common Clock 3.1 4.0 2 MHz 2 dB 6.02000E+6 7.30000E-1 5 MHz 1 dB 1.15300E+7 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 25 GEN3 Common Clock 3.1 4.0 4 MHz 0.01 dB 8.96000E+5 1.40000E+1 5 MHz 1 dB 1.15300E+7 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Delay 9.42478E+6 0.00000E+0 10 ns PCI Express Compliance Report Page 26 of 26 26 GEN3 Common Clock 3.1 4.0 4 MHz 2 dB 1.20400E+7 7.30000E-1 5 MHz 1 dB 1.15300E+7 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 27 GEN4 Common Clock 4.0 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 28 GEN4 Common Clock 4.0 2 MHz 2 dB 6.02000E+6 7.30000E-1 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 29 GEN4 Common Clock 4.0 4 MHz 0.01 dB 8.96000E+5 1.40000E+1 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 30 GEN4 Common Clock 4.0 4 MHz 2 dB 1.20400E+7 7.30000E-1 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 31 GEN4 Common Clock 4.0 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 2 MHz 1 dB 4.62000E+6 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 32 GEN4 Common Clock 4.0 2 MHz 2 dB 6.02000E+6 7.30000E-1 2 MHz 1 dB 4.62000E+6 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 33 GEN4 Common Clock 4.0 4 MHz 0.01 dB 8.96000E+5 1.40000E+1 2 MHz 1 dB 4.62000E+6 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 34 GEN4 Common Clock 4.0 4 MHz 2 dB 1.20400E+7 7.30000E-1 2 MHz 1 dB 4.62000E+6 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 35 GEN4 Common Clock 4.0 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 5 MHz 0.01 dB 1.12000E+6 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 36 GEN4 Common Clock 4.0 2 MHz 2 dB 6.02000E+6 7.30000E-1 5 MHz 0.01 dB 1.12000E+6 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 37 GEN4 Common Clock 4.0 4 MHz 0.01 dB 8.96000E+5 1.40000E+1 5 MHz 0.01 dB 1.12000E+6 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 38 GEN4 Common Clock 4.0 4 MHz 2 dB 1.20400E+7 7.30000E-1 5 MHz 0.01 dB 1.12000E+6 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 39 GEN4 Common Clock 4.0 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 5 MHz 1 dB 1.15300E+7 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 40 GEN4 Common Clock 4.0 2 MHz 2 dB 6.02000E+6 7.30000E-1 5 MHz 1 dB 1.15300E+7 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 41 GEN4 Common Clock 4.0 4 MHz 0.01 dB 8.96000E+5 1.40000E+1 5 MHz 1 dB 1.15300E+7 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns 42 GEN4 Common Clock 4.0 4 MHz 2 dB 1.20400E+7 7.30000E-1 5 MHz 1 dB 1.15300E+7 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns Prepared by Silicon Labs PCIe Clock Jitter Tool v1.0 on 2015-12-07 12:03:22 GMT-08:00 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.