19-2252; Rev 0; 12/01 MAX9205 Evaluation Kit The EV kit requires a single 3.3V supply and a reference clock input with a range of 16MHz to 40MHz to operate. The 10-bit parallel input data is connected to a 24-pin header and the output data is sampled at a separate 24-pin header. The EV kit circuit can be modified to isolate and evaluate the MAX9205 and MAX9206 independently. The MAX9205 and MAX9206 serializer/deserializer pair can be replaced with the MAX9207 and MAX9208 serializer/deserializer pair that operates at a higher maximum data-transfer speed of 600Mbps with a clock input frequency of 40MHz to 60MHz. Features ♦ 3.3V Single Supply ♦ 10-Bit Parallel LVCMOS/LVTTL Interface ♦ Allows Common-Mode Testing ♦ Independent Evaluation of Serializer (MAX9205) and Deserializer (MAX9206) ♦ Allows Testing of Twisted-Pair Cable ♦ Low-Voltage, Low-Power Operation ♦ Fully Assembled and Tested Ordering Information PART TEMP RANGE MAX9205EVKIT 0°C to +70°C IC PACKAGE 28 SSOP Component List DESIGNATION C1–C4 C5–C11, C40 C12–C18, C21–C25, C39, C41 C19, C20 C26 QTY DESCRIPTION 4 10µF ±20%, 10V tantalum capacitors (B) AVX TAJB106M010 or Kemet T494B106K010AS 7 0.001µF ±5%, 50V ceramic capacitors (0603) TDK C1608X7R1H102KT or Murata GRM39X7R102J050AD 14 2 1 DESIGNATION C27–C38 QTY DESCRIPTION 12 10pF, 50V COG ceramic capacitors (0603) TDK C1608COG1H100DT or Murata GRM39COG100D050AD J1, J2 2 2 x 12-pin headers JU1, JU3–JU7 6 3-pin headers 19 2-pin headers 0.1µF ±10%, 16V ceramic capacitors (0603) TDK C1608X7R1C104KT or Murata GRM39X7R104K016AD JU2, JU9, JU10, JU12–JU27 R1–R10, R97 11 10kΩ ±5% resistors (0603) 0 Not installed, resistor (0603) 5.0pF, 50V COG ceramic capacitors (0603) TDK C1608COG1H050CT Murata GRM39COG050B050AD R11–R20, R79–R89, R91–R95 R21–R39, R96 20 49.9Ω ±1% resistors (0603) 2.2µF ±20%, 10V tantalum capacitor (A) AVX TAJA225M010R R40 1 100Ω ±1% resistor (0603) R41–R50, R75 0 Not installed, resistor (0805) R51, R52 0 Not installed, resistor (1206) R53–R74, R77, R78 24 499Ω ±1% resistors (0603) ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 Evaluates: MAX9205–MAX9208 General Description The MAX9205 evaluation kit (EV kit) is a fully assembled and tested circuit board that simplifies the evaluation of the MAX9205 400Mbps, 10-bit serializer and the MAX9206 400Mbps, 10-bit deserializer. The MAX9205 IC transforms 10-bit parallel LVCMOS/LVTTL data into a serial high-speed bus low-voltage differential signaling (BLVDS) data stream. The MAX9206 accepts serial data from the MAX9205 and transforms it back to 10-bitwide LVCMOS/LVTTL parallel data. Evaluates: MAX9205–MAX9208 MAX9205 Evaluation Kit Component List (cont’d) DESIGNATION QTY SYNC2, PWRDN1, DEN, PWRDN2, REN 0 Not installed, SMA PC-mount edge connector TCLK, REFCLK, INA, INB 4 SMA PC-mount edge connectors U1 U2 1 1 MAX9205EAI (28-pin SSOP) MAX9206EAI (28-pin SSOP) U3 1 Buffer/driver three-state output (48-pin TSSOP) Texas Instruments SN74ALVTH16244DGG None 6 Shunts (JU1, JU3–JU7) None 1 MAX9205 PC board None 1 MAX9205 data sheet None 1 MAX9205 EV kit data sheet DESCRIPTION Quick Start The MAX9205 EV kit is a fully assembled and tested surface-mount board. Follow the steps below for EV kit circuit board operation. Do not turn on power supply or enable the function generators until all connections are completed. Recommended Equipment • 3.3VDC power supply • Data generator for LVCMOS/LVTTL 10-bit parallel signal input (e.g., Tektronix DG2020) • Clock pulse generator (e.g., HP 8130A) • Logic analyzer or data-acquisition system • High-speed oscilloscope Procedure 1) Verify that there is a shunt across pins 1 and 2 of jumpers JU1 and JU3–JU7. 2) Verify that JU2 does not have a shunt. 3) Connect the 3.3V power supply to VCC1. Connect the ground terminal of this supply to GND1. 4) Connect the data generator to the 24-pin connector J1 and set it to generate 10-bit parallel data at LVCMOS/LVTTL levels (high-level input from 2.0V to VCC and low-level input from 0.8V to GND). See Table 2 for input bit locations. 5) Connect the pulse generator to SMA connector TCLK and set it for an output with a frequency of 2 Part Selection Table TYPE REF CLOCK RANGE (MHz) SERIAL DATA TRANSFER RATE (Mbps) (max) MAX9205EAI Serializer 16 to 40 400 MAX9206EAI Deserializer 16 to 40 400 MAX9207EAI Serializer 40 to 60 600 MAX9208EAI Deserializer 40 to 60 600 PART 16MHz to 40MHz. Use LVCMOS/LVTTL levels. Note that the TCLK SMA connector is terminated with a 50Ω resistor. Synchronize the pulse generator with the data generator. 6) Set the data-acquisition system for LVCMOS/LVTTLlevel signal input. 7) Connect the data-acquisition system to the signal output 24-pin connector J2. See Table 2 for output bit locations. 8) Turn on the power supply. 9) Enable the pulse generator. 10) Enable the data generator. 11) Enable the data-acquisition system and begin sampling data. Detailed Description The MAX9205 EV kit is a fully assembled and tested circuit board that simplifies the evaluation of the MAX9205 400Mbps maximum data transfer rate, 10-bit serializer and the MAX9206 400Mbps maximum data transfer data rate, 10-bit deserializer. The serializer/deserializer data transfer starts with the serializer initially locking onto the reference clock and then sending synchronizing patterns to the deserializer. Once the deserializer locks onto the embedded clock in the patterns, it pulls the SYNC pin low on the serializer, signaling that it is ready to receive the serial data. The serializer transforms the LVCMOS/LVTTL-level 10-bit parallel data pattern into a serial high-speed BLVDS data stream. The interconnect is terminated with 100Ω at each end of the differential bus for a total 50Ω load. The MAX9206 deserializer accepts the serial data from the MAX9205 and transforms it back to 10-bit-wide LVCMOS/LVTTL parallel data. The EV kit requires a single 3.3V supply to operate and a reference clock input in the 16MHz to 40MHz range. The 10-bit parallel input data can be supplied to the 24pin header J1 with a data generator running at the _______________________________________________________________________________________ MAX9205 Evaluation Kit Power Supplies The MAX9205 EV kit operates from a single 3.3V power supply. The serializer and deserializer power and ground planes are connected with PC board traces through resistor pads R49 and R50. The EV kit circuit can be divided into two independent circuits, a serializer and deserializer circuit with dedicated power and ground planes, by cutting open the PC board shorting traces at resistor pads R49 and R50. If the EV kit circuit is divided into two separate circuits, each circuit requires a 3.3V power supply connected at VCC1 (serializer circuit) and VCC2 (deserializer circuit). Independent power and ground planes allow measurements of the deserializer’s response to ground shift or other common-mode effects. See the Serializer/ Deserializer Circuits section. Clock Signal The MAX9205 EV kit requires a square-wave LVCMOS/LVTTL input clock signal with a frequency in the 16MHz to 40MHz range. The clock signal can be connected to the TCLK SMA connector or to pin 24 in 24-pin header J1. For faster data transfer rates, replace the MAX9205 (U1) and MAX9206 (U2) serializer/deserializer pair with the MAX9207/MAX9208 serializer/deserializer pair and supply a clock signal with a frequency of 40MHz to 60MHz. During independent evaluation of the serializer and deserializer, supply a clock signal to each circuit. See the Serializer/Deserializer Circuits section. The clock input signal to the serializer and deserializer can be monitored at 2-pin headers JU14 and JU15. See Table 1 for details. Input Signal The MAX9205 EV kit accepts 10-bit parallel data at LVCMOS/LVTTL levels (high-level input from 2.0V to Table 1. Clock Signal Monitoring Points HEADER SIGNAL CONNECTOR JU14 Clock input to serializer Differential signal probe JU15 Clock input to deserializer Differential signal probe VCC and low-level input from 0.8V to GND). The 10-bit pattern can be supplied to the EV kit by connecting a data generator to the 24-pin header J1 or by pulling selected J1 bit pins to a low LVCMOS/LVTTL state. All the bit pins on J1 are pulled high (VCC1) with 10kΩ pullup resistors installed on the 10 input signal lines. See Table 2 for input bit locations on the 24-pin header J1. If the serializer circuit is operated independently, either the parallel input can be serialized or a sync pin can be driven high to generate sync patterns. If the deserializer is operated independently, a 12-bit serial pattern (10 data bits plus 2 frame bits) must be supplied to the deserializer circuit. Refer to the Initialization section in the MAX9206/MAX9208 data sheet for details on the deserializer’s input requirements. See the Serializer/Deserializer Circuits section for further discussion of independent evaluation. Output Signal The MAX9205 EV kit outputs 10-bit parallel data at LVCMOS/LVTTL levels on the 24-pin header J2. To sample the 10-bit pattern, connect an acquisition system to J2 or sample the individual bits with a 2-pin header probe. See Table 2 for the output bits’ location on the 24-pin header J2 or Table 3 for the location of the individual output bits. The recovered clock signal is located on pin 23 of J2 and can be used as the external clock input for the acquisition system. Power-Down Reset If no output signal is detected from the deserializer, perform a power-down reset on the serializer by momentarily pulling low the PWRDN pin using jumper JU4. (See Table 5 for JU4 operation.) Serializer/Deserializer Circuits The MAX9205 EV kit board contains a 10-bit parallel serializer (MAX9205)/deserializer (MAX9206) circuit that only requires a 3.3V input power supply, a 10-bit parallel pattern, an acquisition system, and a clock signal for simple board evaluation. JU2 is provided to test the serializer high-impedance (Z) delay time. The EV kit circuit can be divided into two circuits, a serializer and a deserializer circuit, for independent evaluation. To di- _______________________________________________________________________________________ 3 Evaluates: MAX9205–MAX9208 same frequency as the reference clock or the bits can be configured by installing shunts across header J1 pins. The output 10-bit parallel data can be sampled at 24-pin header J2 or individual bits can be tested at the various 2-pin headers installed on the EV kit. The EV kit circuit can be modified to isolate and evaluate the MAX9205 and MAX9206 independently. While isolated, the serializer’s output can be verified with a differential probe or connected to category-5 twistedpair cable. The deserializer’s required LVDS input can be supplied to the EV kit through category-5 twistedpair wire or SMA connectors. The MAX9205 and MAX9206 serializer/deserializer pair can be replaced with the MAX9207 and MAX9208 pair for a higher maximum transfer speed rate of 600Mbps with a maximum clock frequency of 60MHz. Evaluates: MAX9205–MAX9208 MAX9205 Evaluation Kit Table 2. Input/Output Bit Location SIGNAL BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 Input/J1 J1-4 J1-6 J1-8 J1-10 J1-12 J1-14 J1-16 J1-18 J1-20 J1-22 Output/J2 J2-1 J2-3 J2-5 J2-7 J2-9 J2-11 J2-13 J2-15 J2-17 J2-19 Table 3. Individual Parallel Outputs HEADER BIT/SIGNAL JU16 0 JU17 1 JU18 2 JU19 3 JU20* 4 JU21* 5 JU22* 6 JU23 7 JU24 8 JU25 9 JU26* LOCK JU27* RCLK Table 4. LVDS Signals and Connections NONINVERTING SIGNAL INVERTING CONNECTOR SIGNAL Serializer (U1) Output PC board via 1A PC board via 1B Plated through holes for twisted- pair (TP) cable Serializer (U1) Output Header JU9 Header JU10 Differential signal probe Deserializer (U2) Input PC board via 2A (user input) PC board via 2B (user input) Plated through holes for TP cable Deserializer (U2) Input Header JU12 Header JU13 Differential signal probe SIGNAL * Headers are not in sequential order on the EV kit board. vide the circuit into two circuits, cut open the PC board trace shorting the resistor pads at R41–R45, R49, R50, R75, remove resistor R39, and install a shorting resistor on R48. The MAX9205 (U1) serializer circuit generates two types of signals, synchronization and serialized data patterns: 1) Generate synchronization (SYNC) patterns by applying a high-state LVCMOS signal to pin 2 of the 24pin header J1 or the SYNC2 PC board pad. 2) Generate serialized data patterns by asserting a low-state LVCMOS signal to pin 2 of the 24-pin header J1 and provide 10-bit parallel data to the EV kit. For data and clock input signal details, see the Input Signal and Clock Signal sections, respectively. The serializer’s BLVDS output signal is a 12-bit serial pattern that consists of a high-state start bit and lowstate end bit, added internally and used by the deserializer, to the 10-bit parallel input data. Refer to the MAX9205/MAX9207 data sheet for details. To monitor the BLVDS output signal, connect a differential signal probe to JU9 (noninverting single-ended signal) or JU10 (inverting single-ended signal) or connect twisted-pair cable to PC board vias 1A (noninverting signal) 4 and 1B (inverting signal). Terminate the twisted pair at the far end with a 100Ω resistor for a total 50Ω load. See Table 4 for locations and connector type for the LVDS serial signal output. To evaluate the MAX9206 (U2) deserializer circuit, provide a 12-bit BLVDS serial input and a clock signal to the REFCLK SMA connector. Bit 0 of the 12-bit serial input pattern should be BLVDS high state and bit 11 should be BLVDS low state with data bit in between. Refer to the MAX9206/MAX9208 data sheet for further details on the start and end bits. The 12-bit BLVDS pattern can be supplied to the deserializer circuit in two ways: with twisted-pair cable or SMA connectors: 1) Using twisted-pair cable, connect the serial input signal to PC board vias 2A (noninverting signal) and 2B (inverting signal). Terminate the twisted-pair cable at the transmitting end with a 100Ω resistor for a total 50Ω load (including the 100Ω resistor in parallel at the deserializer input). 2) With SMA connectors, install shorting resistors at the R46 and R47 PC board pads and connect the serial signal through SMA connectors INA (noninverting signal) and INB (inverting signal). Monitor the integri- _______________________________________________________________________________________ MAX9205 Evaluation Kit JUMPER SHUNT STATUS JU1 JU2 JU3 JU4 JU5 JU6 JU7 PIN CONNECTION EV KIT OPERATION 1 and 2 TCLK_R/ F to VCC1 2 and 3 TCLK_R/ F to GND1 Installed None Common-mode voltage for serializer high-Z delay test Open None 1 and 2 DEN to VCC1 VOS (offset-voltage probe point) Serial data output enabled Serializer data loads on TCLK rising edge Serializer data loads on TCLK falling edge 2 and 3 DEN to GND1 1 and 2 PWRDN to VCC1 Serializer in normal operation Serial data output in high-Z Serializer in sleep mode, outputs in high-Z 2 and 3 PWRDN to GND1 1 and 2 REN to VCC2 Deserializer parallel outputs enabled 2 and 3 REN to GND2 Deserializer ROUT0–ROUT9 and RCLK pins in high-Z, LOCK is active 1 and 2 PWRDN to VCC2 Deserializer in normal operation 2 and 3 PWRDN to GND2 Deserializer outputs (all) in high-Z 1 and 2 RCLK_R/ F to VCC2 Deserializer output data on RCLK rising edge 2 and 3 RCLK_R/ F to GND2 Deserializer output data on RCLK falling edge Component Suppliers SUPPLIER PHONE FAX WEBSITE AVX 843-448-9411 843-448-1943 www.avxcorp.com Kemet 864-963-6300 864-963-6322 www.kemet.com Murata 770-436-1300 770-436-3030 www.murata.com TDK 847-803-6100 847-390-6296 www.component.tdk.com Texas Instruments 972-644-5580 214-480-7800 www.ti.com Note: Please indicate that you are using the MAX9205 when contacting these component suppliers. ty of the LVDS input signal by connecting a differential signal probe to jumpers JU12 (noninverting signal) or JU13 (inverting signal). See Table 4 for locations and connector type for the serial input. To evaluate the output signal of the deserializer, see the Output Signal section. If LOCK is not low (check JU26 or J2-23), send 200 or more synchronization patterns to the deserializer to lock onto the serial input. Terminations and Layout All signal lines are 50Ω controlled-impedance traces. All the differential output signal traces are terminated with 100Ω resistors at each end. Each differential output pair is laid out with equal trace length. The EV kit is laid out as a four-layer board to minimize noise interference. Jumper Settings The MAX9205 EV kit circuit contains several jumpers that allow the user to put the serializer and deserializer into several operational modes. See Table 5 for jumper settings and EV kit operation descriptions. _______________________________________________________________________________________ 5 Evaluates: MAX9205–MAX9208 Table 5. Jumper Settings Evaluates: MAX9205–MAX9208 MAX9205 Evaluation Kit TP14 SYNC2 TP12 R96 49.9Ω J1-1 VCC1 DVCC SYNC1 28 TP11 R97 10kΩ J1-2 VCC1 1 SYNC1 2 SYNC2 DVCC C5 0.001µF C12 0.1µF C6 0.001µF C13 0.1µF C7 0.001µF C14 0.1µF 27 R1 10kΩ TP1 3 J1-3 J1-4 R11 OPEN AVCC DIN0 VCC1 26 R2 10kΩ TP2 4 J1-5 J1-6 VCC1 R12 OPEN R3 10kΩ DIN1 AGND DIN2 PWRDN 25 VCC1 TP3 5 J1-7 J1-8 R13 OPEN 24 6 J1-10 VCC1 DIN3 R14 OPEN R5 10kΩ U1 AGND R15 OPEN DIN4 VCC1 VCM 1A 7 J1-12 23 MAX9205 TP5 J1-11 DO+ 22 R6 10kΩ 8 R21 49.9Ω 1% GND1 R16 OPEN R7 10kΩ TP7 DO- 9 C21 0.1µF VCC1 JU2 J1-16 R17 OPEN DIN6 1B R42 SHORT VCC2 B C3 10µF 10V C20 5pF JU10 R8 10kΩ VCC1 GND2 TP8 10 J1-17 J1-18 VCC1 DIN7 R18 OPEN R9 10kΩ 11 J1-20 R19 OPEN VT AGND TP9 J1-19 20 VCC1 19 2 DIN8 VCC1 R10 10kΩ DEN DIN9 R20 OPEN VCC1 1 2 3 J1-23 AGND TCLK J1-24 TP13 18 TCLK_R/F AVCC R45 SHORT DEN 13 JU1 14 TCLK JU3 R93 OPEN 12 J1-22 1 3 TP10 J1-21 R23 49.9Ω 1% JU14 DGND DGND 17 16 C8 0.001µF C15 0.1µF 15 CLK (CONTINUED ON FIGURE 2) Figure 1. MAX9205 EV Kit Schematic—Serializer 6 R50 SHORT R49 SHORT R22 49.9Ω 1% 21 C2 10µF 10V VCM DIN5 J1-14 VCC1 J1-15 C1 10µF 10V R41 SHORT A C19 5pF JU9 TP6 J1-13 JU4 PWRDN1 1 R92 OPEN TP4 J1-9 2 3 R4 10kΩ VCC1 _______________________________________________________________________________________ C4 10µF 10V _______________________________________________________________________________________ INA INB R24 49.9Ω 1% REFCLK B 28 3 JU6 2A R94 OPEN R44 SHORT R43 SHORT JU15 R75 SHORT VCC2 PWRDN2 1 2 R25 49.9Ω 1% R47 OPEN R46 OPEN A R26 49.9Ω 1% R48 OPEN CLK REN VCC2 JU7 3 1 2 JU5 VCC2 JU13 JU12 C39 0.1µF 3 1 2 VCC2 8 7 6 5 R95 OPEN R40 100Ω 1% C40 0.001µF 4 3 2 REN PWRDN RIN- RIN+ AVCC REFCLK U2 MAX9205 RCLK_R/F AGND ROUT8 ROUT7 ROUT6 ROUT5 ROUT4 ROUT3 ROUT2 ROUT1 ROUT0 16 17 18 19 24 25 26 27 28 C35 10pF C34 10pF C33 10pF C32 10pF C31 10pF C30 10pF C29 10pF C28 10pF C27 10pF JU24 JU23 JU22 JU21 JU20 JU19 JU18 JU17 JU16 VT VT VT VT VT VT VT VT R69 499Ω 1% R67 499Ω 1% R65 499Ω 1% R63 499Ω 1% R61 499Ω 1% R59 499Ω 1% R57 499Ω 1% R55 499Ω 1% R53 499Ω 1% R87 OPEN R70 499Ω 1% R86 OPEN R68 499Ω 1% R85 OPEN R66 499Ω 1% R84 OPEN R64 499Ω 1% R83 OPEN R62 499Ω 1% R82 OPEN R60 499Ω 1% R81 OPEN R58 499Ω 1% R80 OPEN R56 499Ω 1% R79 OPEN R54 499Ω 1% 37 36 35 33 32 30 29 27 26 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 2A4 2Y4 U3 SN74ALVTHI6244 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 R30 49.9Ω 1% R29 49.9Ω 1% R28 49.9Ω 1% R27 49.9Ω 1% 12 13 14 16 R35 49.9Ω 1% R34 49.9Ω 1% R33 49.9Ω 1% R32 49.9Ω 1% R31 49.9Ω 17 1% 19 20 22 23 J2-8 J2-6 J2-4 J2-17 J2-18 J2-15 J2-16 J2-13 J2-14 J2-11 J2-12 J2-9 J2-10 J2-7 J2-5 J2-3 J2-1 J2-2 VCC2 R52 SHORT R51 SHORT VB C26 2.2µF 10V Evaluates: MAX9205–MAX9208 1 VT MAX9205 Evaluation Kit Figure 2. MAX9205 EV Kit Schematic—Deserializer (Sheet 1 of 2) 7 8 VCC2 C16 0.1µF 14 13 12 C9 0.001µF 11 10 9 DGND AGND AGND AVCC CDCK RCLK DGND DVCC DGND DVCC ROUT9 20 21 22 23 15 VCC2 VT JU27 C38 10pF C41 0.1µF JU26 C18 0.1µF VT R77 499Ω 1% C17 0.1µF VCC2 JU25 C37 10pF C11 0.001µF C10 0.001µF C36 10pF VT VB R89 OPEN R74 499Ω 1% R88 OPEN R72 499Ω 1% C22 0.1µF R91 OPEN R78 499Ω 1% R73 499Ω 1% R71 499Ω 1% C23 0.1µF VB 1A3 1A1 1A2 1A4 42 V CC 31 V CC 2A3 40 2A2 41 2A1 25 3OE 28 GND 34 GND 39 GND 45 GND 48 2OE 38 44 47 46 43 11 5 2 3 VCC VCC 7 18 2Y3 9 2Y2 8 2Y1 24 4OE 21 GND 15 GND 10 GND 4 GND 1 1OE 1Y3 1Y1 1Y2 1Y4 6 R38 49.9Ω 1% R39 49.9Ω 1% R37 49.9Ω 1% R36 49.9Ω 1% C25 0.1µF C24 0.1µF VB VB J2-21 J2-23 J2-19 J2-24 SYNC1 J2-22 J2-20 Evaluates: MAX9205–MAX9208 MAX9205 Evaluation Kit Figure 2. MAX9205 EV Kit Schematic—Deserializer (Sheet 2 of 2) ____________________________________________________________________________________________________ MAX9205 Evaluation Kit Evaluates: MAX9205–MAX9208 Figure 3. MAX9205 EV Kit Component Placement Guide—Component Side Figure 4. MAX9205 EV Kit PC Board Layout—Component Side Figure 5. MAX9205 EV Kit PC Board Layout—Ground Planes _______________________________________________________________________________________ 9 Evaluates: MAX9205–MAX9208 MAX9205 Evaluation Kit Figure 6. MAX9205 EV Kit PC Board Layout—Power Planes Figure 7. MAX9205 EV Kit PC Board Layout– Solder Side Figure 8. MAX9205 EV Kit Component Placement Guide—Solder Side Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.